CN113922815A - Phase-locked loop circuit of leakage compensation structure - Google Patents

Phase-locked loop circuit of leakage compensation structure Download PDF

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Publication number
CN113922815A
CN113922815A CN202111170143.3A CN202111170143A CN113922815A CN 113922815 A CN113922815 A CN 113922815A CN 202111170143 A CN202111170143 A CN 202111170143A CN 113922815 A CN113922815 A CN 113922815A
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compensation
module
capacitor
leakage
phase
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赵超
张�浩
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Nanjing Magnichip Microelectronics Co ltd
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Nanjing Magnichip Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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Abstract

The invention relates to a phase-locked loop circuit with an electric leakage compensation structure, which can solve the electric leakage problem of a loop filter capacitor in a phase-locked loop and provides a feasible scheme for the use of a capacitor with high capacitor density but an electric leakage type in the phase-locked loop; the overall architecture comprises: the device comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider; has the beneficial effects that: firstly, the filter capacitor leakage is compensated through a successive approximation type leakage compensation capacitor array, so that the leakage change caused by the process angle and the temperature of the filter capacitor can be tracked in real time, and the potential mismatch in a leakage compensation path can be calibrated; secondly, the nonlinear problem of capacitor leakage current and VCTRL voltage is solved through a frequency locking and VCTRL clamping mode, and the leakage compensation precision is further improved.

Description

Phase-locked loop circuit of leakage compensation structure
Technical Field
The invention relates to a phase-locked loop circuit with a leakage compensation structure, and belongs to the technical field of semiconductor integrated circuits.
Background
The phase-locked loop circuit is widely applied to various chips and is an indispensable core circuit in the fields of radio frequency and microwave, digital-analog mixing and pure digital. The function and performance of the phase-locked loop are decisive for the success or failure of the whole chip. In an integrated System On Chip (SOC) or a multi-channel interface circuit, a plurality of phase-locked loops are often required to provide a distributed frequency source for radio frequency local oscillator spectrum shifting, a system clock, an audio/video clock, an analog-to-digital conversion sampling clock, and the like. With the development of the SOC, the clock requirement of the chip becomes more and more complex, which leads to the increase of the number of the phase-locked loops, however, the loop filter capacitance required in the phase-locked loops is related to the physical size and cannot be reduced with the process evolution, and how to reduce the area of the phase-locked loops becomes an industrial problem.
Fig. 1 shows a conventional phase-locked loop structure, which includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, where the loop filter of the phase-locked loop based on the voltage-controlled oscillator with a loop structure usually occupies one third or even one half of the area, although the loop filter capacitor is made of low-voltage transistors with high capacitance density, the area of the loop filter capacitor can be effectively reduced, but the leakage problem of the low-voltage transistor will seriously deteriorate the performance of the phase-locked loop, and more seriously, the leakage of the loop filter capacitor changes along with the change of the plate voltage, the process angle and the temperature, which further increases the difficulty of processing the leakage problem, although the problem of leakage between the drain and the source when the transistor is turned off is solved to a certain extent by the appearance of transistors with various structures along with the continuous development of the process, the problem of gate leakage faced by the loop filter capacitor is still not solved effectively. Therefore, the industry still has to adopt a high-voltage tube capacitor or an MOM capacitor with low capacitance density and small leakage as a loop filter capacitor.
Therefore, the problem of electric leakage of the loop filter capacitor greatly limits the available types of capacitors, particularly the low-voltage transistor capacitor with high capacitance density, solves the electric leakage problem of the loop filter capacitor, and improves the capacitance density of the loop filter, which is a technical problem to be solved urgently by technical personnel in the field.
In the prior art, as shown in fig. 2, a leakage compensation technical scheme proposed in the patent "charge pump circuit with capacitance leakage compensation and phase-locked loop circuit" is provided, and the scheme has the main disadvantages: a. b, when the temperature and the frequency change, the voltage of the node VC can change, and the leakage compensation effect is further deteriorated.
Fig. 3 shows a leakage compensation scheme proposed in the patent "phase-locked loop for dynamically compensating gate leakage of V2I transistor in voltage-controlled oscillator", which has the following main disadvantages: a. when the VCTRL voltage (corresponding to the gate voltage of V2I in fig. 3) changes, the leakage compensation accuracy is difficult to guarantee (for example, the VCTRL voltage increases, the leakage of V2I and the filter capacitor Cz increases due to the increase of the VCTRL voltage, but the compensation capacitors C1 to Cn decrease due to the increase of the VCTRL voltage); b. the leakage of the compensation capacitors C1-Cn is directly measured according to the following formula: the 1 offset gives V2I and the filter capacitance Cz, which is typically large in area, resulting in a large area of C1 Cn.
The Leakage Compensation solution proposed in the prior art "a full Integrated Phase-Locked Loop with Leakage Current Compensation in 65-nm CMOS Technology", as shown in fig. 4, has the main disadvantages: a. the dual CP is needed to realize compensation, wasting extra area and power consumption; b. the matching problem of the dual CP and the LCC influences the compensation precision and is difficult to control. Has the advantages that: the dual CP can track the voltage change of VCTRL, and solve the problem that the VCTRL change deteriorates the compensation precision.
Disclosure of Invention
The invention aims to solve the technical problem of providing a phase-locked loop circuit with a leakage compensation structure, which utilizes a successive approximation mode and matched loop control to counteract leakage current of a loop filter capacitor in a leakage current monitoring, calibrating and compensating mode.
The invention adopts the following technical scheme for solving the technical problems: the invention designs a phase-locked loop circuit with a leakage compensation structure, which comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider, wherein the phase frequency detector is connected with the charge pump module;
one input end of the phase frequency detector and the charge pump module is used for accessing a reference clock REFCLK, the output ends of the phase frequency detector and the charge pump module are connected with a node VCTRL through a switch S1, and the node VCTRL is respectively butted with the input end of the filter module, one input end of the successive approximation compensation capacitor module and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module forms the output end of the filter module, and the node VRES is respectively butted with the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is butted with the input end of the electric leakage monitoring compensation module;
the output end of the frequency locking and VCTRL clamping module is butted with the input end of the frequency divider, and the output end of the frequency locking and VCTRL clamping module is used for providing the adjusted frequency and phase for a target circuit; the output end of the frequency divider is in butt joint with the other input ends of the phase frequency detector and the charge pump module, and the frequency divider provides a feedback clock FBCLK after frequency division for the phase frequency detector and the charge pump module.
As a preferred technical scheme of the invention: the successive approximation compensation capacitance module comprises a comparator CMP1, a successive approximation logic SAR and a compensation capacitance array; wherein, the negative input terminal of the comparator CMP1 forms one of the input terminals of the successive approximation compensation capacitance module, and is used for butting the node VCTRL; the positive input end of the comparator CMP1 forms the other input end of the successive approximation compensation capacitance module and is used for butting the node VRES;
the compensation capacitor array comprises compensation capacitors Con, compensation capacitors C1 to Cn and switches corresponding to the compensation capacitors C1 to Cn one by one, wherein the lower pole plates of the compensation capacitors C1 to Cn are respectively connected in series with the corresponding switches and then grounded, the lower pole plate of the compensation capacitor Con is directly grounded, the upper pole plate of the compensation capacitor Con is connected with the upper pole plates of the compensation capacitors C1 to Cn, and the connected ends form the output end of the successive approximation compensation capacitor module;
the output end of the comparator CMP1 is connected to the input end of the successive approximation logic SAR, and the output end of the successive approximation logic SAR is connected to the switches corresponding to the compensation capacitors C1 to Cn.
As a preferred technical scheme of the invention: the leakage monitoring compensation module comprises a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1 and a voltage clamping operational amplifier OP; the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamp OP, and the connection between the two terminals forms the input terminal of the leakage monitoring compensation module; the negative input end of the voltage clamp operational amplifier OP is used for accessing a preset reference voltage VREF; the output end of the voltage clamping operational amplifier OP, the grid electrode of the current monitoring P-type transistor MP2 and the grid electrode of the current compensation P-type transistor MP1 are connected, the drain electrode of the current compensation P-type transistor MP1 forms the output end of the leakage monitoring compensation module, and the source electrode of the current monitoring P-type transistor MP2 and the source electrode of the current compensation P-type transistor MP1 are respectively connected with a preset power supply voltage.
As a preferred technical scheme of the invention: the frequency locking and VCTRL clamping module comprises a clamp comparator CMP2, a digital logic DIG circuit and a voltage controlled oscillator VCO; the negative input end of the clamp comparator CMP2 is used for accessing a preset reference voltage VREF, the positive input end of the clamp comparator CMP2 is connected with the voltage control frequency end of the voltage-controlled oscillator VCO, and the connected position forms the input end of the frequency locking and VCTRL clamping module; the output end of the clamp comparator CMP2 is connected with the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected with a load capacitor ARRAY CAPARRAY in the voltage-controlled oscillator VCO and used for adjusting the frequency of the voltage-controlled oscillator VCO; the output end of the voltage-controlled oscillator VCO forms the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage-controlled oscillator VCO is connected with a preset power supply voltage, and the grounding end of the voltage-controlled oscillator VCO is grounded.
As a preferred technical scheme of the invention: the filter module comprises a capacitor Cz, a capacitor Cp3 and a resistor R; the upper pole plate of the capacitor Cp3 is connected with one end of the resistor R to form an internal node VRES, and the internal node VRES is used as the input end of the filter module; the other end of the resistor R is in butt joint with an upper polar plate of the capacitor Cz, and the butt joint end forms the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and this connection is grounded.
As a preferred technical scheme of the invention: the phase frequency detector and charge pump module comprises switches corresponding to a phase frequency detector PFD, a first current source A1, a second current source A2, a first current source A1 and a second current source A2 respectively; one end of the first current source a1 is connected to a preset power voltage, the other end of the first current source a1 is connected in series with switches corresponding to the first current source a1 and the second current source a2 respectively, and then is connected to one end of the second current source a2, and the other end of the second current source a2 is grounded; two input ends of the phase frequency detector PFD form two input ends of the phase frequency detector and the charge pump module, and are respectively used for accessing a reference clock REFCLK and a feedback clock FBCLK from the frequency divider after frequency division; two output ends of the phase frequency detector PFD are respectively connected with the switches corresponding to the first current source a1 and the second current source a2 in a one-to-one correspondence manner, and are used for controlling the switches, and the output ends of the phase frequency detector and the charge pump module are formed by the connection positions of the two switches.
Compared with the prior art, the phase-locked loop circuit with the leakage compensation structure has the following technical effects by adopting the technical scheme:
the invention designs a phase-locked loop circuit with a leakage compensation structure, which adopts a brand new structure design and comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider, utilizes a successive approximation mode and matched loop control, offsets leakage current of a loop filter capacitor in a leakage current monitoring, calibrating and compensating mode, solves the leakage problem of the loop filter in the traditional phase-locked loop circuit, can be widely applied to various phase-locked loops, provides a feasible scheme for a low-voltage transistor type capacitor with high capacitance density and leakage as the loop filter capacitor, can be used as an effective method for reducing the volume and cost of the phase-locked loop, and designs a leakage compensation method which can overcome the changes of process angle and temperature and calibrate leakage mismatch, the whole circuit is visual in design, simple in structure and easy to realize.
Drawings
FIG. 1 is a diagram illustrating a conventional phase-locked loop;
FIG. 2 is a schematic diagram of a conventional leakage compensation structure;
FIG. 3 is a schematic diagram of a conventional V2I leakage compensation circuit;
FIG. 4 is a schematic diagram of leakage compensation of a dual charge pump;
FIG. 5 is a schematic diagram of a leakage compensation phase-locked loop circuit according to the present invention;
FIG. 6 is a flowchart of a calibration algorithm corresponding to the PLL circuit of the present invention.
Detailed Description
The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.
The invention designs a phase-locked loop circuit with a leakage compensation structure, which comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider as shown in figure 5.
One input end of the phase frequency detector and the charge pump module is used for accessing a reference clock REFCLK, the output ends of the phase frequency detector and the charge pump module are connected with a node VCTRL through a switch S1, and the node VCTRL is respectively butted with the input end of the filter module, one input end of the successive approximation compensation capacitor module and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module forms the output end of the filter module, and the node VRES is respectively butted with the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is connected with the input end of the electric leakage monitoring compensation module.
The output end of the frequency locking and VCTRL clamping module is butted with the input end of the frequency divider, and the output end of the frequency locking and VCTRL clamping module is used for providing the adjusted frequency and phase for a target circuit; the output end of the frequency divider is in butt joint with the other input ends of the phase frequency detector and the charge pump module, and the frequency divider provides a feedback clock FBCLK after frequency division for the phase frequency detector and the charge pump module.
As shown in fig. 5, the phase frequency detector and charge pump module includes switches corresponding to the phase frequency detector PFD, the first current source a1, the second current source a2, and the first current source a1 and the second current source a2, respectively; one end of the first current source a1 is connected to a preset power voltage, the other end of the first current source a1 is connected in series with switches corresponding to the first current source a1 and the second current source a2 respectively, and then is connected to one end of the second current source a2, and the other end of the second current source a2 is grounded; two input ends of the phase frequency detector PFD form two input ends of the phase frequency detector and the charge pump module, and are respectively used for accessing a reference clock REFCLK and a feedback clock FBCLK from the frequency divider after frequency division; two output ends of the phase frequency detector PFD are respectively connected with the switches corresponding to the first current source a1 and the second current source a2 in a one-to-one correspondence manner, and are used for controlling the switches, and the output ends of the phase frequency detector and the charge pump module are formed by the connection positions of the two switches.
As shown in fig. 5, the filter module includes a capacitor Cz, a capacitor Cp3, a resistor R; the upper pole plate of the capacitor Cp3 is connected with one end of the resistor R to form an internal node VRES, and the internal node VRES is used as the input end of the filter module; the other end of the resistor R is in butt joint with an upper polar plate of the capacitor Cz, and the butt joint end forms the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and this connection is grounded.
As shown in fig. 5, the successive approximation compensation capacitance module includes a comparator CMP1, a successive approximation logic SAR, and a compensation capacitance array; wherein, the negative input terminal of the comparator CMP1 forms one of the input terminals of the successive approximation compensation capacitance module, and is used for butting the node VCTRL; the positive input of comparator CMP1 forms the other input of the successive approximation compensation capacitance module for interfacing with node VRES.
The compensation capacitor array comprises compensation capacitors Con, compensation capacitors C1 to Cn and switches corresponding to the compensation capacitors C1 to Cn one by one, wherein the lower pole plates of the compensation capacitors C1 to Cn are respectively connected in series with the corresponding switches and then grounded, the lower pole plate of the compensation capacitor Con is directly grounded, the upper pole plate of the compensation capacitor Con is connected with the upper pole plates of the compensation capacitors C1 to Cn, and the connected ends form the output end of the successive approximation compensation capacitor module; the output end of the comparator CMP1 is connected to the input end of the successive approximation logic SAR, and the output end of the successive approximation logic SAR is connected to the switches corresponding to the compensation capacitors C1 to Cn.
The ratio of the compensation capacitances C1 to Cn to the capacitance Cz in the filter module is 1: n, the electric leakage of the smaller capacitor can be amplified by N times through the current mirror and then injected back to the capacitor Cz to save the area, the electric leakage compensation capacitor array formed by the compensation capacitor Con and the compensation capacitors C1 to Cn and the capacitor Cz are formed by the same minimum unit, and the plates are drawn together to save the area, so that the electric leakage compensation capacitor can well track the process angle and the temperature change of the electric leakage of the capacitor Cz in the filter module to improve the electric leakage compensation precision.
The leakage monitoring compensation module is shown in fig. 5 and includes a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1, and a voltage clamping operational amplifier OP; the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamp OP, and the connection between the two terminals forms the input terminal of the leakage monitoring compensation module; the negative input end of the voltage clamp operational amplifier OP is used for accessing a preset reference voltage VREF; the output end of the voltage clamping operational amplifier OP, the grid electrode of the current monitoring P-type transistor MP2 and the grid electrode of the current compensation P-type transistor MP1 are connected, the drain electrode of the current compensation P-type transistor MP1 forms the output end of the leakage monitoring compensation module, and the source electrode of the current monitoring P-type transistor MP2 and the source electrode of the current compensation P-type transistor MP1 are respectively connected with a preset power supply voltage.
The frequency locking and VCTRL clamping module is shown in fig. 5, and includes a clamp comparator CMP2, a digital logic DIG circuit, and a voltage controlled oscillator VCO; the negative input end of the clamp comparator CMP2 is used for accessing a preset reference voltage VREF, the positive input end of the clamp comparator CMP2 is connected with the voltage control frequency end of the voltage-controlled oscillator VCO, and the connected position forms the input end of the frequency locking and VCTRL clamping module; the output end of the clamp comparator CMP2 is connected with the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected with a load capacitor ARRAY CAPARRAY in the voltage-controlled oscillator VCO and used for adjusting the frequency of the voltage-controlled oscillator VCO; the output end of the voltage-controlled oscillator VCO forms the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage-controlled oscillator VCO is connected with a preset power supply voltage, and the grounding end of the voltage-controlled oscillator VCO is grounded.
The leakage problem of the loop filter capacitor seriously deteriorates the phase-locked loop performance, and is difficult to process and mainly shows two aspects, namely: limited by the chip manufacturing process, the industry is forced to only adopt a capacitor with low capacitance density but small leakage as a loop filter capacitor, which results in low area utilization rate; secondly, the method comprises the following steps: after the phase-locked loop is locked, the control voltage value VCTRL of the voltage-controlled oscillator changes along with the changes of the process and the environment, and the nonlinear relation is presented between the capacitor leakage and the plate voltage, so that the variables influencing the leakage are many and are difficult to process.
The main principle of the phase-locked loop circuit with the leakage compensation structure is as follows: as shown in fig. 5, the phase frequency detector and the charge pump are first disconnected from node VCTRL by switch S1, namely, the voltage of the node VCTRL is biased on the reference voltage VREF, the frequency locking and VCTRL clamping module is opened, the frequency of the voltage-controlled oscillator VCO is adjusted by adjusting CAPARRAY, meanwhile, the voltage drop (VCTRL-VRES) at two ends of a resistor R in the filter module is monitored, the leakage current of a loop filter capacitor Cz is directly reflected on the voltage drop (VCTRL-VREF), a comparator CMP1 compares the VCTRL voltage with the VRES voltage and adjusts the compensation capacitor array through successive approximation logic, the leakage current monitoring and compensating module monitors the current of the compensation capacitor array and injects the current into a node VRES, the capacitance of the compensation capacitor array is adjusted through successive approximation logic by the leakage of the compensation capacitor Cz, when the difference between the voltage at node VCTRL and the voltage at node VRES is minimal, optimal leakage compensation is achieved. After the capacitor ARRAY calibration is completed, the switch S1 is closed to connect the phase frequency detector and the charge pump into a phase-locked loop for phase locking, meanwhile, the CMP2 is kept on, and the voltage of the node VCTRL is monitored and the CAPARRAY of the VCO is dynamically adjusted in real time, so that the VCTRL is always close to the reference voltage VREF, and the uncertainty of the voltage of the Cz plate of the capacitor in the filter along with the change of the process and the temperature is avoided, and the accuracy of the leakage compensation current is improved.
After the capacitor array is calibrated, the switch S1 is closed, and the phase frequency detector and the charge pump are connected to the loop for phase locking. Meanwhile, the VCTRL clamp comparator CMP2 monitors the VCTRL node voltage all the time, and dynamically adjusts the capacitor ARRAY CAPARRAY of the voltage-controlled oscillator, thereby the VCTRL voltage is always approximately equal to VREF voltage after locking, through the cooperation with the clamp operational amplifier OP, the matching degree between the current mirror MP1 and the MP2 can be improved, and the change of the leakage current of the capacitor Cz caused by the voltage change of the VCTRL node can be reduced, the leakage current compensation precision is further improved through the mode, and the problem of the leakage compensation precision caused by the nonlinear relation between the leakage current and the voltage of a capacitor plate is solved.
The structure of the invention copies the leakage current of the capacitor Cz in the filter module through the leakage current compensation capacitor array (C1 to Cn), and adjusts and calibrates the capacitor array through successive approximation logic, so as to realize the compensation of the leakage current of the capacitor Cz, and the ratio of the compensation capacitor array (C1 to Cn) to the filter capacitor is 1: n; the mirror ratio of the MP1 and the MP2 in the current monitoring compensation module is N:1, and the capacitor in the compensation capacitor array and the loop filter capacitor Cz are both formed by combining the same minimum capacitor unit modules and are matched with each other in layout, so that the compensation capacitor array can keep the same process angle offset and temperature coefficient with the loop filter capacitor, the temperature resistance and process angle change resistance of leakage compensation are improved, and the problem of the first aspect is solved. The load capacitance CAPARRAY of the VCO is dynamically adjusted in real time through the clamp comparator CMP2, the voltage of the VCTRL is always approximately equal to the voltage of VREF, and the fluctuation of capacitance leakage along with the voltage of an electrode plate is reduced, so that the nonlinear influence factors of the capacitance leakage and the current mirror image of the current monitoring compensation module are reduced, the precision of leakage current compensation is improved, and the problem of the second aspect is solved. The algorithm control of the three modes of specific frequency calibration, leakage calibration and phase locking is shown in figure 6. The capacitor Cz is the largest in the phase-locked loop filter module and occupies a main area, so the leakage compensation is performed on the capacitor Cz, and the effective scheme is provided for the Cz leakage compensation to ensure that the capacitor with high capacitor density but large leakage current is used in the phase-locked loop, so that the area of the phase-locked loop can be reduced.
The phase-locked loop circuit with the leakage compensation structure is designed by adopting a brand new structure design and comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider, utilizes a successive approximation mode and matched loop control, offsets the leakage current of a loop filter capacitor in a leakage current monitoring, calibrating and compensating mode, solves the leakage problem of the loop filter in the traditional phase-locked loop circuit, can be widely applied to various phase-locked loops, provides a feasible scheme for a low-voltage transistor type capacitor with high capacitance density and leakage as the loop filter capacitor, can be used as an effective method for reducing the volume and cost of the phase-locked loop, and can overcome the changes of a process angle and temperature and calibrate leakage mismatch, the whole circuit is visual in design, simple in structure and easy to realize.
The embodiments of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (6)

1. A phase-locked loop circuit of a leakage compensation structure; the method is characterized in that: the device comprises a phase frequency detector, a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module and a frequency divider;
one input end of the phase frequency detector and the charge pump module is used for accessing a reference clock REFCLK, the output ends of the phase frequency detector and the charge pump module are connected with a node VCTRL through a switch S1, and the node VCTRL is respectively butted with the input end of the filter module, one input end of the successive approximation compensation capacitor module and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module forms the output end of the filter module, and the node VRES is respectively butted with the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is butted with the input end of the electric leakage monitoring compensation module;
the output end of the frequency locking and VCTRL clamping module is butted with the input end of the frequency divider, and the output end of the frequency locking and VCTRL clamping module is used for providing the adjusted frequency and phase for a target circuit; the output end of the frequency divider is in butt joint with the other input ends of the phase frequency detector and the charge pump module, and the frequency divider provides a feedback clock FBCLK after frequency division for the phase frequency detector and the charge pump module.
2. The phase-locked loop circuit of a leakage compensation structure as claimed in claim 1, wherein: the successive approximation compensation capacitance module comprises a comparator CMP1, a successive approximation logic SAR and a compensation capacitance array; wherein, the negative input terminal of the comparator CMP1 forms one of the input terminals of the successive approximation compensation capacitance module, and is used for butting the node VCTRL; the positive input end of the comparator CMP1 forms the other input end of the successive approximation compensation capacitance module and is used for butting the node VRES;
the compensation capacitor array comprises compensation capacitors Con, compensation capacitors C1 to Cn and switches corresponding to the compensation capacitors C1 to Cn one by one, wherein the lower pole plates of the compensation capacitors C1 to Cn are respectively connected in series with the corresponding switches and then grounded, the lower pole plate of the compensation capacitor Con is directly grounded, the upper pole plate of the compensation capacitor Con is connected with the upper pole plates of the compensation capacitors C1 to Cn, and the connected ends form the output end of the successive approximation compensation capacitor module;
the output end of the comparator CMP1 is connected to the input end of the successive approximation logic SAR, and the output end of the successive approximation logic SAR is connected to the switches corresponding to the compensation capacitors C1 to Cn.
3. The phase-locked loop circuit of a leakage compensation structure as claimed in claim 1, wherein: the leakage monitoring compensation module comprises a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1 and a voltage clamping operational amplifier OP; the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamp OP, and the connection between the two terminals forms the input terminal of the leakage monitoring compensation module; the negative input end of the voltage clamp operational amplifier OP is used for accessing a preset reference voltage VREF; the output end of the voltage clamping operational amplifier OP, the grid electrode of the current monitoring P-type transistor MP2 and the grid electrode of the current compensation P-type transistor MP1 are connected, the drain electrode of the current compensation P-type transistor MP1 forms the output end of the leakage monitoring compensation module, and the source electrode of the current monitoring P-type transistor MP2 and the source electrode of the current compensation P-type transistor MP1 are respectively connected with a preset power supply voltage.
4. The phase-locked loop circuit of a leakage compensation structure as claimed in claim 1, wherein: the frequency locking and VCTRL clamping module comprises a clamp comparator CMP2, a digital logic DIG circuit and a voltage controlled oscillator VCO; the negative input end of the clamp comparator CMP2 is used for accessing a preset reference voltage VREF, the positive input end of the clamp comparator CMP2 is connected with the voltage control frequency end of the voltage-controlled oscillator VCO, and the connected position forms the input end of the frequency locking and VCTRL clamping module; the output end of the clamp comparator CMP2 is connected with the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected with a load capacitor ARRAY CAPARRAY in the voltage-controlled oscillator VCO and used for adjusting the frequency of the voltage-controlled oscillator VCO; the output end of the voltage-controlled oscillator VCO forms the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage-controlled oscillator VCO is connected with a preset power supply voltage, and the grounding end of the voltage-controlled oscillator VCO is grounded.
5. The phase-locked loop circuit of a leakage compensation structure as claimed in claim 1, wherein: the filter module comprises a capacitor Cz, a capacitor Cp3 and a resistor R; the upper pole plate of the capacitor Cp3 is connected with one end of the resistor R to form an internal node VRES, and the internal node VRES is used as the input end of the filter module; the other end of the resistor R is in butt joint with an upper polar plate of the capacitor Cz, and the butt joint end forms the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and this connection is grounded.
6. The phase-locked loop circuit of a leakage compensation structure as claimed in claim 1, wherein: the phase frequency detector and charge pump module comprises switches corresponding to a phase frequency detector PFD, a first current source A1, a second current source A2, a first current source A1 and a second current source A2 respectively; one end of the first current source a1 is connected to a preset power voltage, the other end of the first current source a1 is connected in series with switches corresponding to the first current source a1 and the second current source a2 respectively, and then is connected to one end of the second current source a2, and the other end of the second current source a2 is grounded; two input ends of the phase frequency detector PFD form two input ends of the phase frequency detector and the charge pump module, and are respectively used for accessing a reference clock REFCLK and a feedback clock FBCLK from the frequency divider after frequency division; two output ends of the phase frequency detector PFD are respectively connected with the switches corresponding to the first current source a1 and the second current source a2 in a one-to-one correspondence manner, and are used for controlling the switches, and the output ends of the phase frequency detector and the charge pump module are formed by the connection positions of the two switches.
CN202111170143.3A 2021-10-08 2021-10-08 Phase-locked loop circuit of leakage compensation structure Pending CN113922815A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117560091A (en) * 2024-01-02 2024-02-13 南京美辰微电子有限公司 GPON OLT optical module burst mode receiving end noise detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117560091A (en) * 2024-01-02 2024-02-13 南京美辰微电子有限公司 GPON OLT optical module burst mode receiving end noise detection circuit
CN117560091B (en) * 2024-01-02 2024-03-29 南京美辰微电子有限公司 GPON OLT optical module burst mode receiving end noise detection circuit

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