CN117560091B - GPON OLT optical module burst mode receiving end noise detection circuit - Google Patents
GPON OLT optical module burst mode receiving end noise detection circuit Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/695—Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q2011/0079—Operation or maintenance aspects
- H04Q2011/0083—Testing; Monitoring
Abstract
The invention discloses a GPON OLT optical module burst mode receiving end noise detection circuit, which comprises: the noise detection circuit is used for carrying out noise monitoring on square wave input data with the period of T in a basic logic calculation period. The invention is applied to the burst mode receiving link of the GPON OLT, and the invention converts the frequency information into the voltage information through the charge pump and then carries out noise judgment, thus greatly improving the success rate of detecting the input effective signal when the original amplitude is detected and used. The invention takes the logic circuit and the comparator discrimination circuit as the main components, the parameter adjustment is flexible, and the invention can be simply applied to various application occasions by selecting proper parameters.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a noise detection circuit of a burst mode receiving end of a GPON OLT optical module.
Background
In the burst mode receiving end circuit of the GPON OLT optical module, an input signal needs to be detected, and a high-level indication effective signal is output when a preamble of the input signal arrives, so that the working time sequence of the whole system is determined. The common signal detection scheme is to monitor the amplitude of an input signal, and judge that the input signal is an effective input signal when the amplitude of the input signal is larger than a threshold value, but the amplitude detection method can misunderstand that a normal signal comes when a noise signal with enough amplitude like a burr exists, and the judgment error occurs to influence the work of the whole circuit. Therefore, a noise detection circuit for detecting frequency is added on the basis of amplitude detection, when the frequency of an input signal is in a set range, the input signal is judged to be an effective signal, a high level is output, otherwise, the input signal is judged to be a noise signal, and a low level is output. When the function of the noise detection circuit is turned on, the noise detection circuit output and the original signal detection output are AND logic, so that the finally output level is pulled up only when the amplitude frequency of the input signal meets the set range, otherwise, the output is low level, and the accuracy of the result of the signal detection circuit is greatly improved. In the burst mode, the time from no signal to the arrival of the preamble and then to the arrival of the data packet is short, the circuit is required to be established in a short time and complete judgment in a limited time, and the frequency detection range cannot be too small because the preamble is a square wave with an uncontrollable duty ratio in the range of 30% -70%, so that the occurrence of false diagnosis of the arrival of the effective signal as noise is avoided. Thus, it is a difficulty in noise detection circuit design to complete the detection in a short enough time, and to select a suitable frequency detection range and to be able to accommodate the uncertainty of the preamble duty cycle.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problem that the existing amplitude detection circuit mostly cannot accurately identify burrs, the noise detection circuit of the burst mode receiving end of the GPON OLT optical module is provided, and effective signals and burr signals are better identified.
The technical problems to be solved by the invention are as follows: aiming at the problem that the existing amplitude detection circuit mostly cannot accurately identify burrs, the noise detection circuit of the burst mode receiving end of the GPON OLT optical module is provided, and effective signals and burr signals are better identified.
In order to solve the technical problems, the invention provides the following technical scheme: the GPON OLT optical module burst mode receiving end noise detection circuit comprises: the noise detection circuit is used for carrying out noise monitoring on square wave input data with the period of T in a basic logic calculation period,
the input end of the first logic circuit is used for receiving square wave input data with the period of T and RST signals, the first output end of the first logic circuit is connected with the first input end of the charge pump and outputs UP signals to the charge pump,
the second output end of the first logic circuit is connected with the second input end of the charge pump, and outputs a DN signal to the charge pump;
the third input end of the charge pump is used as a first current source to receive an input voltage VCC, and the fourth input end of the charge pump is used as a second current source to be grounded;
the output end of the charge pump is connected with one end of the capacitor and the input end of the comparator module, and the other end of the capacitor is grounded; the comparator module is used for receiving the voltage output by the charge pump and comparing the voltage with a threshold interval to obtain a result of whether the frequency of the input data is in a preset range or not;
the output end of the comparator module is connected with the input end of the logic AND gate, the logic AND gate carries out logic AND operation on the result output by the comparator module, the output end of the logic AND gate is connected with the input end of the second logic circuit, the input end of the second logic circuit receives the logic AND calculation result output by the logic AND gate and carries out logic calculation, and the output end of the second logic circuit is used as the output end of the noise detection circuit to output the noise monitoring result.
Further, the charge pump includes a PMOS switch and an NMOS switch;
the grid electrode of the PMOS switch is used as a first input end of the charge pump and receives an UP signal from a first output of the first logic circuit, the grid electrode of the NMOS switch is used as a second input end of the charge pump and receives a DN signal from a second output of the first logic circuit;
the source of the PMOS switch receives the input voltage VCC as the third input terminal of the charge pump, the source of the NMOS switch receives the ground as the fourth input terminal of the charge pump, the drain of the PMOS switch is connected to the drain of the NMOS switch, and the connected terminal is the output terminal of the charge pump.
Further, the aforementioned comparator module includes a first comparator and a second comparator;
the positive input end of the first comparator receives a high threshold signal VTH_H, the negative input end of the first comparator is used as a first input end of the comparator module to receive the voltage output by the charge pump, the first comparator is used for comparing the voltage output by the charge pump with the high threshold signal VTH_H, and the output end of the first comparator is used as a first output end of the comparator module;
the inverting input end of the second comparator receives a low threshold signal VTH_L, and the non-inverting input end of the second comparator is used as a second input end of the comparator module to receive the voltage output by the charge pump; the second comparator is used for comparing the voltage output by the charge pump with the low threshold signal VTH_L, the output end of the second comparator is used as the second output end of the comparator module, the output end of the first comparator is used as the first output end and the second output end of the comparator module, and the connected end is used as the output end of the comparator module.
Further, the first LOGIC circuit LOGIC1 has a basic LOGIC calculation period of 4T, and the four calculation periods output the control charge pump to discharge, charge, hold, and operate respectively.
The input signal is divided by the first LOGIC circuit LOGIC1 and a control signal of four cycles is output to the charge pump circuit, which charges the output capacitor CAP to a different level and holds the CP signal for a certain time according to the control signal. During the holding time, the two comparators AMP1, AMP2 compare the CP terminal level, AND the two comparators AMP1, AMP2 output noise detection results through the AND gate AND the second LOGIC circuit LOGIC 2.
Compared with the prior art, the beneficial technical effects of the invention adopting the technical scheme are as follows:
the invention converts frequency information into voltage signals by utilizing frequency division of input signals and charging the capacitor through the charge pump, and detects the signal frequency through comparison of the voltage signals, thereby judging whether the input is a noise signal. The method has the advantages that the influence of input duty ratio distortion on detection can be avoided by dividing the frequency of the signals in advance, the influence of input frequency offset on detection can be reduced by setting the high and low threshold ranges of the comparator, the required establishment time and detection time are short, and the requirement of a burst mode on detection time is met. The invention is used in combination with the original amplitude detection on the system, and can greatly improve the success rate of detecting the input effective signal. The invention takes the logic circuit and the comparator discrimination circuit as the main components, has low power consumption and flexible parameter adjustment, and can be simply applied to various application occasions by selecting proper parameters.
Drawings
Fig. 1 is a circuit diagram of noise detection at a burst mode receiving end of a GPON OLT optical module according to the present invention.
FIG. 2 is a timing diagram of the output of the first LOGIC1 according to the present invention.
Fig. 3 is a waveform diagram of the output of the noise detection circuit at the burst mode receiving end of the GPON OLT optical module according to the present invention.
Fig. 4 is an input frequency scan of the noise detection circuit at the burst mode receiving end of the GPON OLT of the present invention.
Detailed Description
For a better understanding of the technical content of the present invention, specific examples are set forth below, along with the accompanying drawings.
Aspects of the invention are described herein with reference to the drawings, in which there are shown many illustrative embodiments. The embodiments of the present invention are not limited to the embodiments described in the drawings. It is to be understood that this invention is capable of being carried out by any of the various concepts and embodiments described above and as such described in detail below, since the disclosed concepts and embodiments are not limited to any implementation. Additionally, some aspects of the disclosure may be used alone or in any suitable combination with other aspects of the disclosure.
As shown in fig. 1, the present invention provides a noise detection circuit at a burst mode receiving end of a GPON OLT optical module, including: the noise detection circuit is used for carrying out noise monitoring on square wave input data with the period of T in a basic logic calculation period 4T.
The input end of the first logic circuit is used for receiving square wave input data with the period of T and RST signals, the first output end of the first logic circuit is connected with the first input end of the charge pump, and the first output end of the first logic circuit is used for outputting UP signals to the charge pump. The second output end of the first logic circuit is connected with the second input end of the charge pump, and outputs a DN signal to the charge pump; the third input of the charge pump receives an input voltage VCC as a first current source and the fourth input of the charge pump is grounded as a second current source.
The output end of the charge pump is connected with one end of the capacitor and the input end of the comparator module, and the other end of the capacitor is grounded; the comparator module is used for receiving the voltage output by the charge pump and comparing the voltage with a threshold interval to obtain a result of whether the frequency of the input data is within a preset range. The output end of the comparator module is connected with the input end of the logic AND gate, the logic AND gate carries out logic AND operation on the result output by the comparator module, the output end of the logic AND gate is connected with the input end of the second logic circuit, the input end of the second logic circuit receives the logic AND calculation result output by the logic AND gate and carries out logic calculation, and the output end of the second logic circuit is used as the output end of the noise detection circuit to output the noise monitoring result.
As a preferred embodiment of the present invention, the charge pump includes a PMOS switch, and an NMOS switch. The gate of the PMOS switch is used as a first input terminal of the charge pump to receive the UP signal from the first output of the first logic circuit, and the gate of the NMOS switch is used as a second input terminal of the charge pump to receive the DN signal from the second output of the first logic circuit. The source of the PMOS switch receives the input voltage VCC as the third input terminal of the charge pump, the source of the NMOS switch receives the ground as the fourth input terminal of the charge pump, the drain of the PMOS switch is connected to the drain of the NMOS switch, and the connected terminal is the output terminal of the charge pump.
As a preferred embodiment of the present invention, the comparator module includes a first comparator, a second comparator; the positive input end of the first comparator receives a high threshold signal VTH_H, the negative input end of the first comparator is used as a first input end of the comparator module to receive the voltage output by the charge pump, the first comparator is used for comparing the voltage output by the charge pump with the high threshold signal VTH_H, and the output end of the first comparator is used as a first output end of the comparator module; the inverting input end of the second comparator receives a low threshold signal VTH_L, and the non-inverting input end of the second comparator is used as a second input end of the comparator module to receive the voltage output by the charge pump; the second comparator is used for comparing the voltage output by the charge pump with the low threshold signal VTH_L, the output end of the second comparator is used as the second output end of the comparator module, the output end of the first comparator is used as the first output end and the second output end of the comparator module, and the connection section is used as the output end of the comparator module.
Based on the circuit design of the invention, input DATA DATA_IN is input from a first LOGIC circuit LOGIC1, the output UP and DN of the LOGIC circuit LOGIC1 are respectively input to the control end of a charge pump formed by a PMOS switch and an NMOS switch, the output end CP of the charge pump formed by the PMOS switch and the NMOS switch is connected to two comparators CMP1 and CMP2, the results of the two comparators are processed and LOGIC is then output to the LOGIC circuit LOGIC2, and finally the result ND_OUT of the noise detection circuit is output.
The output timing diagram of the first LOGIC circuit LOGIC1 is shown in the output timing diagram of the first LOGIC circuit LOGIC1 in fig. 2, the period of input data is a T square wave, after the first LOGIC circuit LOGIC1 processes that the falling edge of RST comes, counting is started from the first rising edge of data, and counting is started to the fifth rising edge, namely, the total 4*T time period is recorded as a basic LOGIC calculation period. In a basic logic calculation cycle, in which during the first T time, UP, DN both output high level, the PMOS switch is turned off, and the NMOS switch is turned on, i.e. the current source IDC2 discharges the capacitor CAP. The voltage value of the output end CP of the charge pump is compared with a high threshold value VTH_H and a low threshold value VTH_L through two comparators respectively, in the second T time, UP and DN output low level, the PMOS switch is turned on, and the NMOS switch is turned off, namely the first current source IDC1 charges the capacitor CAP. In the third and fourth T time, the UP output is high, the DN output is low, the PMOS switch and the NMOS switch are both disconnected, and the capacitor CAP is not charged or discharged. Because the second current source IDC2 has a large current, the voltage at the output terminal CP of the charge pump will be rapidly discharged to 0 potential in the first T time, and the current of the first current source IDC1 is moderate, so that the output terminal CP of the charge pump will be charged to different potentials according to the difference of T times in the second T time, the output terminal CP of the charge pump is maintained in the third and fourth T times, and the subsequent circuit is judged for use, and then discharged to the ground in the first T time of the next basic logic calculation period, and the cycle is repeated.
When the input data rate is f, the data width is t=1/f, and since the preamble data is a square wave, one data 1 plus one data 0 constitutes one square wave period, i.e., t= 2*t =2/f. When the input is a glitch signal, the rising edge of the first glitch signal triggers the timing of the first T, and the second and third glitch signals may be after a long time, so that the output CP of the charge pump is charged to the power supply voltage VCC (3.3V) for a long time T after being discharged to the 0 potential, and if the input signal is a dense glitch or a white noise-like signal, the interval of each rising edge is very small, T is very small, and the voltage reached by the output CP of the charge pump in the T time is very low. Therefore, when the input is normal data, T is a value within a certain range determined by the input data rate f, by selecting a suitable first current source IDC1, a second current source IDC2, a capacitor CAP capacitance value and other relevant device parameters, the voltage at the output end CP of the charge pump reaches an intermediate value after charging, and then selecting a suitable high threshold vth_h and low threshold vth_l, and determining whether the voltage at the output end CP of the charge pump is between the two thresholds by two comparators, it can be determined whether the input data frequency is within a required range, and combining amplitude detection can achieve the effect of determining whether the input data frequency is a noise false trigger. The data rate of the application occasion of the design is 2.5G, the high threshold value is 2V, the low threshold value is 1V, the frequency range of the signal can be judged to be 1.25G G-5G, the setting of the range can fully ensure that the data can be correctly judged under the condition that the frequency of the input data preamble has a certain deviation, meanwhile, the noise is a pure random signal, the probability of falling in the range is very small, and the rising edge trigger count is adopted, so that the duty ratio deviation of the square wave can not influence the normal operation of the circuit under the condition that the rising time condition of the circuit is met. When the input data is in the selected frequency range, the voltage of the CP terminal is smaller than the high threshold value VTH_H AND is larger than the low threshold value VTH_L, the first comparator CMP1 AND the second comparator CMP2 output 1, the two outputs pass through the AND gate AND AND output 1, AND the other conditions output 0 through the AND gate, AND at the moment, in order to complete a basic logic calculation period, one judgment is completed.
In order to improve the judgment accuracy of the circuit, the AND gate output is connected to the second LOGIC circuit LOGIC2 for processing, the basic LOGIC calculation cycle is repeated three times, the input data frequency is judged three times, when at least two times of judgment reach the set frequency range, the signal is considered to be valid, the ND_OUT is output as a high level, otherwise, the signal is judged as a noise signal, and the ND_OUT is output as a low level. The overall time required by the scheme is three basic logic calculation periods, each basic logic calculation period is 4T, the total time is Ttotal=3x4xT=24xt, the 2.5G rate is taken as an example, the data width is 400ps, the maximum time of noise detection is 9.6ns, and the requirement of a burst mode on detection time can be met. Fig. 3 is a waveform diagram of the noise detection circuit output by the burst mode receiving end of the GPON OLT optical module, in the working process, under the condition that the duty ratio of an input square wave is distorted to 30%, the simulation waveforms of signals in the circuit can be seen, the voltage of a CP end is sequentially discharged, charged, kept AND kept in four T periods, the voltage of the CP end is kept at a high threshold vth_h after being charged, a low threshold vth_l is kept between, AND an AND gate AND output outputs a high level after the first T period, AND an nd_out outputs a high level after finishing a second basic logic calculation period, the detection result is accurate AND consistent with the above description, wherein the detection is started when the falling edge of a RST signal comes, the detection is ended when the rising of the nd_out is ended, AND the next falling edge signal is waited for coming. Fig. 4 is an input frequency scan diagram of the noise detection circuit at the burst mode receiving end of the GPON OLT optical module, as shown in fig. 4, in order to scan the input data frequency, output waveforms in the drawing are nd_out output waveforms when the input data pulse widths t=200 ps to t=1 ns respectively from top to bottom, and the interval is 100ps. As can be seen from fig. 4, when t=300 ps to t=700 ps, nd_out is pulled high after the detection is completed, and nd_out is output at low level at other input frequencies. The data pulse width is converted into data frequency, namely when the input frequency is lower than 1.25G or higher than 5G, the ND_OUT output is low, and when the input frequency is between 1.25G and 5G, the ND_OUT output is pulled to high after detection is completed. When the input is within the set frequency range, the signal is considered as an effective signal, and when the input is outside the set frequency range, the signal is considered as a noise signal, thereby completing the noise detection function.
While the invention has been described in terms of preferred embodiments, it is not intended to be limiting. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.
Claims (4)
- The GPON OLT optical module burst mode receiving end noise detection circuit is characterized by comprising: the noise detection circuit is used for carrying out noise monitoring on square wave input data with the period of T in a basic logic calculation period,the input end of the first logic circuit is used for receiving square wave input data with the period of T and RST signals, the first output end of the first logic circuit is connected with the first input end of the charge pump and outputs UP signals to the charge pump,the second output end of the first logic circuit is connected with the second input end of the charge pump, and outputs a DN signal to the charge pump;the third input end of the charge pump is used as a first current source to receive an input voltage VCC, and the fourth input end of the charge pump is used as a second current source to be grounded;the output end of the charge pump is connected with one end of the capacitor and the input end of the comparator module, and the other end of the capacitor is grounded; the comparator module is used for receiving the voltage output by the charge pump and comparing the voltage with a threshold interval to obtain a result of whether the frequency of the input data is in a preset range or not;the output end of the comparator module is connected with the input end of the logic AND gate, the logic AND gate carries out logic AND operation on the result output by the comparator module, the output end of the logic AND gate is connected with the input end of the second logic circuit, the input end of the second logic circuit receives the logic AND calculation result output by the logic AND gate and carries out logic calculation, and the output end of the second logic circuit is used as the output end of the noise detection circuit to output the noise monitoring result.
- 2. The GPON OLT optical module burst mode receive-side noise detection circuit of claim 1, wherein the charge pump comprises a PMOS switch and an NMOS switch;the grid electrode of the PMOS switch is used as a first input end of the charge pump and receives an UP signal from a first output of the first logic circuit, the grid electrode of the NMOS switch is used as a second input end of the charge pump and receives a DN signal from a second output of the first logic circuit;the source of the PMOS switch receives the input voltage VCC as the third input terminal of the charge pump, the source of the NMOS switch receives the ground as the fourth input terminal of the charge pump, the drain of the PMOS switch is connected to the drain of the NMOS switch, and the connected terminal is the output terminal of the charge pump.
- 3. The GPON OLT optical module burst mode receiving end noise detection circuit of claim 1, wherein the comparator module comprises a first comparator and a second comparator;the positive input end of the first comparator receives a high threshold signal VTH_H, the negative input end of the first comparator is used as a first input end of the comparator module to receive the voltage output by the charge pump, the first comparator is used for comparing the voltage output by the charge pump with the high threshold signal VTH_H, and the output end of the first comparator is used as a first output end of the comparator module;the inverting input end of the second comparator receives a low threshold signal VTH_L, and the non-inverting input end of the second comparator is used as a second input end of the comparator module to receive the voltage output by the charge pump; the second comparator is used for comparing the voltage output by the charge pump with the low threshold signal VTH_L, the output end of the second comparator is used as the second output end of the comparator module, the output end of the first comparator is used as the first output end and the second output end of the comparator module, and the connected end is used as the output end of the comparator module.
- 4. The noise detection circuit of the burst mode receiving end of the GPON OLT optical module according to claim 1, wherein a basic LOGIC calculation period of the first LOGIC circuit LOGIC1 is 4T, and output of the four calculation periods controls the charge pump to perform discharging, charging, holding and holding operations, respectively.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338822A (en) * | 2000-07-28 | 2002-03-06 | 日本电气株式会社 | Switch noise inhibiting semiconductor device phase lock loop circuit and charge pumping circuit |
| CN102801390A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | POP noise suppression circuit in D audio frequency amplifier |
| CN103107776A (en) * | 2011-11-14 | 2013-05-15 | 嘉兴联星微电子有限公司 | Ultralow power consumption band-pass frequency detector and frequency discrimination method of the ultralow power consumption band-pass frequency detector |
| CN103973305A (en) * | 2014-05-23 | 2014-08-06 | 武汉大学 | Low-noise phase-locked loop with automatic frequency correction function |
| CN113922815A (en) * | 2021-10-08 | 2022-01-11 | 南京美辰微电子有限公司 | Phase-locked loop circuit of leakage compensation structure |
| CN116405032A (en) * | 2023-03-10 | 2023-07-07 | 吉林大学 | Noise shaping successive approximation type analog-to-digital converter and control method |
| CN116798449A (en) * | 2022-03-15 | 2023-09-22 | 北京小米移动软件有限公司 | Noise elimination method and device and terminal equipment |
-
2024
- 2024-01-02 CN CN202410002080.8A patent/CN117560091B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338822A (en) * | 2000-07-28 | 2002-03-06 | 日本电气株式会社 | Switch noise inhibiting semiconductor device phase lock loop circuit and charge pumping circuit |
| CN103107776A (en) * | 2011-11-14 | 2013-05-15 | 嘉兴联星微电子有限公司 | Ultralow power consumption band-pass frequency detector and frequency discrimination method of the ultralow power consumption band-pass frequency detector |
| CN102801390A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | POP noise suppression circuit in D audio frequency amplifier |
| CN103973305A (en) * | 2014-05-23 | 2014-08-06 | 武汉大学 | Low-noise phase-locked loop with automatic frequency correction function |
| CN113922815A (en) * | 2021-10-08 | 2022-01-11 | 南京美辰微电子有限公司 | Phase-locked loop circuit of leakage compensation structure |
| CN116798449A (en) * | 2022-03-15 | 2023-09-22 | 北京小米移动软件有限公司 | Noise elimination method and device and terminal equipment |
| CN116405032A (en) * | 2023-03-10 | 2023-07-07 | 吉林大学 | Noise shaping successive approximation type analog-to-digital converter and control method |
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