CN102324931B - Charge pump circuit in frequency synthesizer - Google Patents
Charge pump circuit in frequency synthesizer Download PDFInfo
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- CN102324931B CN102324931B CN 201110125625 CN201110125625A CN102324931B CN 102324931 B CN102324931 B CN 102324931B CN 201110125625 CN201110125625 CN 201110125625 CN 201110125625 A CN201110125625 A CN 201110125625A CN 102324931 B CN102324931 B CN 102324931B
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- charge pump
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Abstract
The invention discloses a charge pump circuit in a frequency synthesizer, which mainly solves the problems that the traditional charge pump circuit generates current peak during the charge and discharge processes, as a result, the big nonideal effect is caused, and comprises an external current source I1, an N-channel metal oxide semiconductor (NMOS) current mirror circuit, a P-channel metal oxide semiconductor (PMOS) current mirror circuit and a switch circuit, wherein the switch circuit consists of n plus 1 groups of sub switching circuits, and each sub switching circuit consists of two current-limiting resistances R1 and R2, two control switching tubes MA and MB, charge differential switching geminate transistors M28 and M29, discharge differential switching geminate transistors M30 and M31 and a unit gain operational amplifier G. The two control switching MA and MB are used for changing the charge-discharge current in each group of sub switching circuit, the two current-limiting resistances R1 and R2 are used for eliminating the current peak which is produced during the charge and discharge processes of the load pump circuit, so the nonideal effect is reduced. The charge pump circuit is applied in the frequency synthesizer, the spectrum purity of the output signal of the frequency synthesizer can be effectively improved, and the accuracy of the locking frequency is improved.
Description
Technical field
The present invention relates to charge pump circuit, the charge pump circuit in a kind of frequency synthesizer particularly can make that the frequency synthesizer non-ideal effects is little, the locking frequency accuracy is high, is used for communication, instrument and meter, high-speed computer and navigation system.
Background technology
Frequency synthesizer is based on equipment or the instrument that the frequency synthesis principle forms, and it is that standard frequency source with a high accuracy and high stability is through a large amount of discrete frequencies that add, subtract, the multiplication and division arithmetic produces same accuracy and stability.Frequency synthesizer is as the high discrete interval type frequency of signal generator of a kind of frequency stability, and it is widely used in communication, instrument and meter, high-speed computer and the navigation system, is the important component part of contemporary electronic systems.In the equipment such as communication, radar and navigation, frequency synthesizer is the exciting signal source of transmitter, is again the local oscillator of receiver; In countermeasures set, it can be used as the interference signal generator; In testing equipment, can be used as standard signal source.
With reference to Fig. 1, frequency synthesizer is a closed loop APC system, and it is comprised of five basic parts: phase frequency detector PFD, charge pump CP, loop filter LPF, voltage controlled oscillator VCO and frequency divider Divider.Phase frequency detector compares the phase place of input reference signal and the phase place of output signal of frequency divider, realize the Phase synchronization of two signals of telecommunication, namely when the phase difference of two signals keeps constant or is zero, loop enters stable state, show that phase place locks, at this moment the frequency f of output signal of frequency divider
DivEqual the frequency f of input reference signal
Ref, i.e. f
Ref=f
DivOtherwise phase frequency detector can be proceeded the phase bit comparison, produces PMOS differential output signal Up, Upb, and nmos differential output signal Dn, Dnb control respectively the respective switch pipe in the charge pump circuit, by charge pump circuit control loop filter is discharged and recharged.This charging and discharging currents is by forming direct-current control voltage V behind the loop filter
TuneRegulate voltage controlled oscillator, make the frequency divider output frequency approach the input reference signal frequency, finally reach lock-out state.
Charge pump is as the key component of frequency synthesizer, receives the output signal that comes from phase frequency detector, and control according to this signal loop filter circuit is charged or the size of discharge, charging and discharging currents, and the time of charging and discharging currents.It converts the digital voltage signal of phase frequency detector output to analog current signal, passes to loop filter, forms control voltage to voltage controlled oscillator, regulation and control output signal frequency by loop filter simultaneously.So phase frequency detector produces phase difference in order to comparator input signal phase place and phase of output signal; And charge pump circuit is in order to this phase difference of accurate Characterization, and converts thereof into the regulatable analog voltage signal of late-class circuit.Analog voltage signal is used for the output of control VCO, and wherein any fluctuation will be introduced with reference to spuious, so that the fluctuation that the output of VCO generation is not expected, thereby affects the normal operation of whole frequency synthesizer system.
Charge pump circuit has many non-ideal effects, particularly because the charge injection and the clock feed-through effect that adopt switching tube to introduce.Charge injection refers to switching tube in the situation that fully conducting, and raceway groove can accumulate many charges of the electron.When switching tube becomes the process of disconnection from conducting, the many charges of the electron that have about half enter into voltage-controlled point, so that voltage-controlled point voltage V
TuneChange; On the contrary, when switching tube becomes from disconnection the process of conducting, voltage-controlled point has some electric charges to enter into raceway groove again, so that the voltage V of voltage-controlled point
TuneChange.Clock feed-through effect refers to that switching tube exists grid leak and grid source electric capacity, and switching tube can be coupled to the variation of control signal Up, Upb, Dn, Dnb on the voltage-controlled point by grid leak and grid source electric capacity, makes voltage-controlled point voltage V
TuneThe variation that generation is not expected produces burr.
The charge mismatch that the clock feedthrough of switching tube and charge injection cause will cause the charge pump charging and discharging currents not mate, simultaneously because the drain terminal of charge pump circuit switching tube is direct and voltage-controlled some V
TuneLink to each other, these effects will directly be introduced spuious composition, make V
TuneThe variation that the voltage generation is not expected.And, traditional charge pump circuit only has one group of switching tube corresponding with it, when requiring charge pump charging and discharging currents value larger for different charging and discharging currents usually, increase owing to flowing through the electric current of each switching tube, thereby the output voltage range of charging and discharging currents size coupling is diminished.For guaranteeing that output voltage range is enough large, can only adopt the switching tube of non-minimum dimension.This will increase grid source, the gate leakage capacitance of switching tube, thereby increase the non-ideal effects of switching tube.
Simultaneously, charge pump circuit is at charge and discharge process meeting generation current spike, and this spike can be introduced non-ideal effects, introduces spuious composition, makes the control voltage V of voltage controlled oscillator
TuneThe variation that generation is not expected.Simultaneously, excessive current spike also can make device failure.
To sum up, conventional charge pump circuit is owing to adopting the switching tube of non-minimum dimension, and can the generation current spike in charge and discharge process, causes its non-ideal effects very large, so that frequency synthesizer can't lock onto accurately frequency, even causes device failure.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art existence, a kind of charge pump circuit for frequency synthesizer is provided, adopt the minimum dimension switching tube and introduce current-limiting resistance, to reduce non-ideal effects, improve the accuracy of frequency synthesizer locking frequency.
For achieving the above object, the present invention includes: external impressed current source I
1, NMOS current mirroring circuit, PMOS current mirroring circuit and switching circuit; External impressed current source I
1Link to each other with the current input terminal of NMOS current mirroring circuit, the NMOS current mirroring circuit provides input current for the PMOS current mirroring circuit, the current output terminal of NMOS current mirroring circuit and PMOS current mirroring circuit links to each other with switching circuit, by switching circuit the charge pump circuit output node is carried out charge or discharge, wherein: switching circuit is organized sub-switching circuit by n+1 and is composed in parallel, and every group of sub-switching circuit is by two current-limiting resistance R
1, R
2, two control switch pipe M
A, M
B, the charging differential switch is to pipe M
28, M
29, the discharge differential switch is to pipe M
30, M
31Form with unit gain operational amplifier G; This charging differential switch is to pipe M
28, M
29Source electrode and the first control switch pipe M
ALink to each other, this discharge differential switch is to pipe M
30, M
31Source electrode and the second control switch pipe M
BLink to each other, unit gain operational amplifier G is connected across switching tube M
28With M
29Drain electrode between; This first control switch pipe M
ABy the first current-limiting resistance R
1Be connected in the charging differential switch to pipe M
28, M
29Source, be used for the switching circuit group number of control charging; This second control switch pipe M
BBy the second current-limiting resistance R
2Be connected in the discharge differential switch to pipe M
30, M
31Source electrode, be used for the switching circuit group number of controlled discharge.
Described n+1 organizes sub-switching circuit, and its input A0～An is connected to the current output terminal of PMOS current mirroring circuit; Its output B0～Bn is connected to NMOS current mirroring circuit current output terminal; PMOS differential input end Up, Upb, nmos differential input Dn, Dnb all are connected to the output of phase frequency detector; The control signal Enb of every group of sub-switching circuit, En are controlled by external signal respectively.
Described charging differential switch is to pipe M
28, M
29Adopt the minimum dimension PMOS pipe that all allows with technique, the discharge differential switch is to pipe M
30, M
31All the minimum dimension NMOS of adopting process permission manages.
Described the first control switch pipe M
AAdopt the PMOS pipe, the second control switch pipe M
BAdopt the NMOS pipe.
Described two current-limiting resistance R
1And R
2All adopt polysilicon resistance.
The present invention compared with prior art has following advantage:
1) switching circuit of the present invention has reduced the charging and discharging currents of every group of sub-switching circuit owing to adopting n+1 sub-switching circuit parallel-connection structure.
2) switching circuit of the present invention is owing to adopting the control switch pipe to select the sub-switching circuit group number of work, change neatly thus and flow through the charging and discharging currents of every group of sub-switching circuit, but the minimum dimension transistor that the difference input switch in the sub-switching circuit is allowed the pipe adopting process.
3) sub-switching circuit of the present invention has been eliminated the current spike that produces in the charge pump circuit charge and discharge process owing to introducing two current-limiting resistances, has guaranteed the stability of charge pump circuit charging and discharging currents, has improved the accuracy of frequency synthesizer locking frequency.
4) the difference input switch of sub-switching circuit of the present invention owing to the minimum dimension transistor that adopting process allows, has reduced the non-ideal effects of charge pump circuit to pipe.
By the said structure characteristics, the charge pump circuit that the present invention realizes is applied in the frequency synthesizer, can reduce the non-ideal effects of frequency synthesizer, improves the spectral purity of output signal, improves the accuracy of locking frequency.
Description of drawings:
Fig. 1 is the frequency synthesizer structured flowchart that the present invention uses;
Fig. 2 is charge pump circuit block diagram of the present invention;
Fig. 3 is the switching circuit structured flowchart in the charge pump of the present invention;
Fig. 4 is the sub-switching circuit schematic diagram among Fig. 3;
Fig. 5 is charge pump circuit charging process simulation result figure of the present invention;
Fig. 6 is charge pump circuit discharge process simulation result figure of the present invention.
Specific implementation
Below in conjunction with accompanying drawing implementation of the present invention is further described.
Referring to Fig. 2, charge pump circuit of the present invention is mainly by external impressed current source I
1, NMOS current mirroring circuit, PMOS current mirroring circuit and switching circuit form.External impressed current source I
1Link to each other with the current input terminal of NMOS current mirroring circuit, the current output terminal 1 of NMOS current mirroring circuit links to each other with the current input terminal of PMOS current mirroring circuit, and switching circuit is connected across the current output terminal of PMOS current mirroring circuit and the current output terminal 2 of NMOS current mirroring circuit.External impressed current source I
1For the NMOS current mirroring circuit provides input current, the NMOS current mirroring circuit provides input current by current output terminal 1 for the PMOS current mirroring circuit, and the NMOS current mirroring circuit provides discharging current I by current output terminal 2 for switching circuit
Dn, the PMOS current mirroring circuit provides charging current I for switching circuit
Up, switching circuit is used for the charge pump circuit output node is carried out charge or discharge, and the structure of this switching circuit is as shown in Figure 3.
With reference to Fig. 3, switching circuit of the present invention is organized sub-switching circuit by n+1 and is composed in parallel, and its input A0～An is connected to the current output terminal of PMOS current mirroring circuit; Its output B0～Bn is connected to NMOS current mirroring circuit current output terminal 2; PMOS differential input end Up, Upb are connected to output Up, the Upb of phase frequency detector, and nmos differential input Dn, Dnb are connected to output Dn, the Dnb of phase frequency detector; The control signal Enb of every group of sub-switching circuit, En are controlled by external signal respectively, and anti-phase each other.When En is high potential, when Enb is electronegative potential, corresponding sub-switching circuit conducting, namely this sub-switching circuit has contribution to exporting the charging and discharging currents size; When En is electronegative potential, when Enb was high potential, corresponding sub-switching circuit turn-offed, and namely this sub-switching circuit is not contributed output charging and discharging currents size.
With reference to Fig. 4, every group of sub-switching circuit is by two current-limiting resistance R
1, R
2, two control switch pipe M
A, M
B, the charging differential switch is to pipe M
28, M
29, the discharge differential switch is to pipe M
30, M
31Form with unit gain operational amplifier G.The charging differential switch is to pipe M
28, M
29, to be realized by the PMOS pipe, its grid meets respectively PMOS differential input signal Up, Upb, and source electrode meets the first current-limiting resistance R
1, drain electrode is connected to respectively the discharge differential switch to pipe M
30, M
31Drain electrode.The discharge differential switch is to pipe M
30, M
31, to realize by the NMOS pipe, its grid meets respectively nmos differential input signal Dn, Dnb, and source electrode meets the second current-limiting resistance R
2, drain electrode is connected to respectively the charging differential switch to pipe M
28, M
29Drain electrode.The first control switch pipe M
ABy the first current-limiting resistance R
1Be connected in the charging differential switch to pipe M
28, M
29Source.The second control switch pipe M
BBy the second current-limiting resistance R
2Be connected in the discharge differential switch to pipe M
30, M
31Source electrode.The inverting input of unit gain operational amplifier G and output short circuit, and be connected to charging differential switch pipe M
28Drain electrode, in-phase input end is connected to charge pump circuit output F point.
Current-limiting resistance R in the described sub-switching circuit
1And R
2, in order to the current spike that reduces to produce in the charge pump circuit charge and discharge process.Namely when charge pump circuit because continually conducting or when turn-offing the generation current spike of switching tube, the large electric current that flows through these two current-limiting resistances makes its both end voltage fall increase, make the transistor in NMOS current mirroring circuit and the PMOS current mirroring circuit enter linear zone by the saturation region, thereby the output current of NMOS current mirroring circuit and PMOS current mirroring circuit is reduced rapidly, current spike is disappeared.This current-limiting resistance R
1And R
2When having protected device, also reduced the non-ideal effects of current over pulse generation to the impact of charge pump circuit, guaranteed the stability of charge pump circuit charging and discharging currents, improved the accuracy of frequency synthesizer locking frequency.
Current-limiting resistance R in the described sub-switching circuit
1And R
2, realize by polysilicon resistance, but be not limited to polysilicon resistance.
Described the first control switch pipe M
AAdopt the PMOS pipe, the second control switch pipe M
BAdopt the NMOS pipe, in order to selecting the sub-switching circuit group number of real work, thereby regulate the charging and discharging currents that flows through every group of sub-switching circuit.Its control principle is as follows:
When requiring charging current I
UpOr discharging current I
DnDuring greater than 50uA, n+1 organizes the control switch pipe M in the sub-switching circuit
AAnd M
BAll conductings, namely n+1 organizes sub-switching circuit and all works, so that the electric current of each way switching circuit only is 1/ (n+1) of total current; And when requiring charging current I
UpOr discharging current I
DnDuring less than 50uA, the control switch pipe M of n+1 way switching circuit
AAnd M
BA conducting part disconnects all the other sub-switching circuits, makes the sub-switching circuit electric current that flows through each road be fixed on the current value that is complementary with the minimum dimension switching tube.Thus, when circuit design, the charging differential switch is to pipe M
28, M
29But the minimum dimension transistor that adopting process allows, the discharge differential switch is to pipe M
30, M
31But the minimum dimension transistor that adopting process allows, grid source, the gate leakage capacitance of differential switch pipe have been reduced, charge injection and the clock feed-through effect of switching tube have been reduced, thereby reduced the non-ideal effects of charge pump circuit, improve the spectral purity of frequency synthesizer output signal, improved the accuracy of locking frequency.
Described PMOS differential input signal Up, Upb are output Up, the Upb of phase frequency detector, and are anti-phase; Described nmos differential input signal Dn, Dnb are output Dn, the Dnb of phase frequency detector, and are anti-phase.When Up, Dnb are high potential, when Upb, Dn were electronegative potential, the charging differential switch was to M in the pipe
28Shutoff, M
29Conducting, the discharge differential switch is to M in the pipe
30Conducting, M
31Turn-off, this moment, switching circuit charged to the charge pump circuit output node.When Up, Dnb are electronegative potential, when Upb, Dn were high potential, the charging differential switch was to M in the pipe
28Conducting, M
29Turn-off, the discharge differential switch is to M in the pipe
30Shutoff, M
31Conducting, this moment, switching circuit discharged to the charge pump circuit output node.
In charging process, from the output current I of PMOS current mirroring circuit
UpBy the first control switch pipe M
AWith the first current-limiting resistance R
AFlow to charging differential switch pipe M
29Source, and by charging differential switch pipe M
29Output node to charge pump circuit charges; Output current I from the NMOS current mirroring circuit
DnBy the second control switch pipe M
AWith the second current-limiting resistance R
BFlow to discharge differential switch pipe M
30Source, and by discharge differential switch pipe M
30Flow to the output of unit gain operational amplifier G.The output end voltage that the output end voltage of unit gain operational amplifier G is followed charge pump circuit changes, so that when the charge pump circuit charging finished, the output end voltage of charge pump circuit can not undergone mutation.
In discharge process, from the output current I of NMOS current mirroring circuit
DnBy the second control switch pipe M
BWith the second current-limiting resistance R
BFlow to discharge differential switch pipe M
31Source, and by discharge differential switch pipe M
31Output node to charge pump circuit discharges; Output current I from the PMOS current mirroring circuit
UpBy the first control switch pipe M
AWith the first current-limiting resistance R
1Flow to charging differential switch pipe M
28Source, and by charging differential switch pipe M
28Flow to the output of unit gain operational amplifier G; The output end voltage that the output end voltage of unit gain operational amplifier G is followed charge pump circuit changes, so that when the charge pump circuit discharge finished, the output end voltage of charge pump circuit can not undergone mutation.
Effect of the present invention can further specify by following emulation:
1) charge pump circuit charging process of the present invention is carried out emulation, its result such as Fig. 5, wherein (a) is charge pump circuit input Up signal, (b) is the control voltage V in the loop filter
TuneAs seen from Figure 5, charge pump circuit charges to loop filter when the Up signal pulse arrives, the control voltage V in the loop filter
TuneBasically increase with linear characteristic, waveform has been eliminated the current spike that produces in the charge pump circuit charging process smoothly without overshoot.This shows, the present invention has reduced the non-ideal effects that produces in the charge pump circuit charging process effectively.
2) charge pump circuit discharge process of the present invention is carried out emulation, its result such as Fig. 6, wherein (a) is charge pump circuit input Dn signal, (b) is the control voltage V in the loop filter
TuneAs seen from Figure 6, charge pump circuit discharges to loop filter when the Dn signal pulse arrives, the control voltage V in the loop filter
TuneBasically reduce with linear characteristic, waveform has been eliminated the current spike that produces in the charge pump circuit discharge process smoothly without overshoot.This shows, the present invention has reduced the non-ideal effects that produces in the charge pump circuit discharge process effectively.
More than be example of the present invention, do not consist of any restriction to the present invention.
Claims (4)
1. the charge pump circuit in the frequency synthesizer comprises external impressed current source I
1, NMOS current mirroring circuit, PMOS current mirroring circuit and switching circuit; External impressed current source I
1Link to each other with the current input terminal of NMOS current mirroring circuit, the NMOS current mirroring circuit provides input current for the PMOS current mirroring circuit, the current output terminal of NMOS current mirroring circuit and PMOS current mirroring circuit links to each other with switching circuit, by switching circuit the charge pump circuit output node is carried out charge or discharge; Switching circuit is organized sub-switching circuit by n+1 and is composed in parallel, and every group of sub-switching circuit is by two current-limiting resistance R
1, R
2, two control switch pipe M
A, M
B, the charging differential switch is to pipe M
28, M
29, the discharge differential switch is to pipe M
30, M
31Form with unit gain operational amplifier G; This charging differential switch is to pipe M
28, M
29Source electrode and the first control switch pipe M
ALink to each other, this discharge differential switch is to pipe M
30, M
31Source electrode and the second control switch pipe M
BLink to each other, unit gain operational amplifier G is connected across switching tube M
28With M
29Drain electrode between; This first control switch pipe M
ABy the first current-limiting resistance R
1Be connected in the charging differential switch to pipe M
28, M
29Source, be used for the switching circuit group number of control charging; This second control switch pipe M
BBy the second current-limiting resistance R
2Be connected in the discharge differential switch to pipe M
30, M
31Source electrode, be used for the switching circuit group number of controlled discharge; It is characterized in that:
Described n+1 organizes sub-switching circuit, and its input A0～An is connected to the current output terminal of PMOS current mirroring circuit; Its output B0～Bn is connected to the current output terminal of NMOS current mirroring circuit; PMOS differential input end Up, Upb, nmos differential input Dn, Dnb all are connected to the output of phase frequency detector; The control signal Enb of every group of sub-switching circuit, En are controlled by external signal respectively;
Described charging differential switch is to pipe M
28, M
29, its grid meets respectively PMOS differential input signal Up, Upb, and source electrode meets the first current-limiting resistance R
1, drain electrode is connected to respectively the discharge differential switch to pipe M
30, M
31Drain electrode;
Described discharge differential switch is to pipe M
30, M
31, its grid meets respectively nmos differential input signal Dn, Dnb, and source electrode meets the second current-limiting resistance R
2, drain electrode is connected to respectively the charging differential switch to pipe M
28, M
29Drain electrode.
2. the charge pump circuit in the frequency synthesizer as claimed in claim 1 is characterized in that: described charging differential switch is to pipe M
28, M
29Adopt the minimum dimension PMOS pipe that all allows with technique, the discharge differential switch is to pipe M
30, M
31All the minimum dimension NMOS of adopting process permission manages.
3. the charge pump circuit in the frequency synthesizer as claimed in claim 1 is characterized in that: described the first control switch pipe M
AAdopt the PMOS pipe, the second control switch pipe M
BAdopt the NMOS pipe.
4. the charge pump circuit in the frequency synthesizer as claimed in claim 1 is characterized in that: described two current-limiting resistance R
1And R
2All adopt polysilicon resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110125625 CN102324931B (en) | 2011-05-17 | 2011-05-17 | Charge pump circuit in frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110125625 CN102324931B (en) | 2011-05-17 | 2011-05-17 | Charge pump circuit in frequency synthesizer |
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| Publication Number | Publication Date |
|---|---|
| CN102324931A CN102324931A (en) | 2012-01-18 |
| CN102324931B true CN102324931B (en) | 2013-04-17 |
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|---|---|---|---|
| CN 201110125625 Expired - Fee Related CN102324931B (en) | 2011-05-17 | 2011-05-17 | Charge pump circuit in frequency synthesizer |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710124B (en) * | 2012-06-19 | 2015-06-17 | 电子科技大学 | Charge pump circuit |
| CN111464182A (en) * | 2020-04-29 | 2020-07-28 | 四川玖越机器人科技有限公司 | Inspection robot |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7092689B1 (en) * | 2003-09-11 | 2006-08-15 | Xilinx Inc. | Charge pump having sampling point adjustment |
| CN101267205A (en) * | 2008-04-24 | 2008-09-17 | 无锡紫芯集成电路系统有限公司 | A current-adjustable charge pump circuit |
| CN201754556U (en) * | 2010-05-12 | 2011-03-02 | 四川和芯微电子股份有限公司 | Charge pump circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4657252B2 (en) * | 2007-06-04 | 2011-03-23 | 三洋電機株式会社 | Charge pump circuit and slice level control circuit |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7092689B1 (en) * | 2003-09-11 | 2006-08-15 | Xilinx Inc. | Charge pump having sampling point adjustment |
| CN101267205A (en) * | 2008-04-24 | 2008-09-17 | 无锡紫芯集成电路系统有限公司 | A current-adjustable charge pump circuit |
| CN201754556U (en) * | 2010-05-12 | 2011-03-02 | 四川和芯微电子股份有限公司 | Charge pump circuit |
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| CN102324931A (en) | 2012-01-18 |
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