CN113921601B - 高压晶体管结构及其制作方法 - Google Patents

高压晶体管结构及其制作方法 Download PDF

Info

Publication number
CN113921601B
CN113921601B CN202010650267.0A CN202010650267A CN113921601B CN 113921601 B CN113921601 B CN 113921601B CN 202010650267 A CN202010650267 A CN 202010650267A CN 113921601 B CN113921601 B CN 113921601B
Authority
CN
China
Prior art keywords
insulating material
layer
metal
gate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010650267.0A
Other languages
English (en)
Other versions
CN113921601A (zh
Inventor
李志成
李凯霖
陈威任
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN202010650267.0A priority Critical patent/CN113921601B/zh
Priority to US16/936,442 priority patent/US11251279B2/en
Priority to US17/564,104 priority patent/US11610973B2/en
Publication of CN113921601A publication Critical patent/CN113921601A/zh
Application granted granted Critical
Publication of CN113921601B publication Critical patent/CN113921601B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开一种高压晶体管结构及其制作方法,其中该高压晶体管结构包含一基底,一金属栅极设置于基底上,至少一绝缘材料结构穿透金属栅极,一金属化合物层设置于金属栅极和基底之间以及绝缘材料结构和基底之间,其中金属化合物层为连续结构,一栅极介电层设置于金属化合物层下方并且接触基底。

Description

高压晶体管结构及其制作方法
技术领域
本发明涉及一种高压晶体管的结构及其制作方法,特别是涉及绝缘材料结构穿透高压晶体管的金属栅极的结构及其制作方法。
背景技术
现今集成电路芯片包含数百万,甚至数十亿的半导体元件形成于半导体基材上。集成电路芯片可使用许多不同类型的晶体管装置,其取决于集成电路芯片的应用。近年来,携带型装置和无线电频率装置的市场逐渐扩大,使得高压晶体管装置的使用有显著的增加。例如:高压晶体管装置因其具有高击穿电压(例如约大于50V)以及高频率,常被使用于无线电频率传送/接收链的功率放大器。
然而由于高压晶体管通常是使用金属栅极,并且因为高压晶体管的栅极面积较大,因此在形成金属栅极时,容易在平坦化金属栅极的步骤时,在金属栅极的上表面产生凹陷(dishing)。
发明内容
根据本发明的一优选实施例,一种高压晶体管结构包含一基底,一金属栅极设置于基底上,至少一绝缘材料结构穿透金属栅极,一金属化合物层设置于金属栅极和基底之间以及绝缘材料结构和基底之间,其中金属化合物层为连续结构,一栅极介电层设置于金属化合物层下方并且接触基底。
根据本发明的一优选实施例,一种高压晶体管结构的制作方法,包含首先提供一基底,依序形成一栅极介电层、一金属化合物层和一虚置栅极材料层覆盖基底,以金属化合物层为停止层,图案化虚置栅极材料层以形成一虚置栅极和至少一孔洞穿透虚置栅极,然后形成一绝缘材料层覆盖虚置栅极和金属化合物层并且绝缘材料层填入孔洞,其中填入孔洞的绝缘材料层构成至少一绝缘材料结构,之后平坦化绝缘材料层以曝露出虚置栅极的上表面,接着移除虚置栅极以形成一沟槽,最后形成一金属栅极填入沟槽并且金属栅极围绕绝缘材料结构。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1至图8为本发明的一优选实施例所绘示的一种高压晶体管结构的制作方法的示意图,其中:
图2和图3为接续图1的制作工艺示意图,其中图3为图2中沿切线AA’所绘示的侧视图;
图4为接续图3的制作工艺示意图;
图5为接续图4的制作工艺示意图;
图6为接续图5的制作工艺示意图;
图7和图8为接续图6的制作工艺示意图,其中图8为图7中沿切线BB’所绘示的侧视图;
图9为本发明的另一优选实施例所绘示的绝缘材料结构的变化型的示意图;
图10为本发明的又一优选实施例所绘示的绝缘材料结构的变化型的示意图。
主要元件符号说明
10:基底
12:浅沟槽隔离
12a:氧化硅
12b:氧化铪
14:金属化合物层
16:虚置栅极材料层
16’:虚置栅极
18:掩模层
20:孔洞
22:间隙壁
24:掺杂区
26:绝缘材料层
26a:蚀刻停止层
26b:层间介电层
28:绝缘材料结构
30:沟槽
32:金属栅极
100:高压晶体管结构
Y:方向
具体实施方式
图1至图8为根据本发明的一优选实施例所绘示的一种高压晶体管结构的制作方法。图9为根据本发明的另一优选实施例所绘示的绝缘材料结构的变化型。图10为根据本发明的又一优选实施例所绘示的绝缘材料结构的变化型。
如图1所示,一种高压晶体管结构的制作方法,包含提供一基底10,在基底10上设置有浅沟槽隔离12埋入于基底10中,接着依序形成一栅极介电层12、一金属化合物层14、一虚置栅极材料层16和一掩模层18覆盖基底。基底10可以为一硅基底、一锗基底、一砷化镓基底、一硅锗基底、一磷化铟基底、一氮化镓基底、一碳化硅基底或是一硅覆绝缘基底。栅极介电层12可以为多层介电材料层堆叠而成,举例而言,栅极介电层12可以包含氧化硅、氮氧化硅、氮化硅、氧化钽(Ta2O5)、氧化铝(Al2O5)、氧化铪(HfO2)、含氮氧化物、含铪氧化物、含钽氧化物、含铝氧化物或高介电常数(K>5)材料等,或上述材料的组合。举例而言,栅极介电层12可以由一层氧化铪12b堆叠在一层氧化硅12a上所构成。金属化合物层14包含金属氧化物或金属氮化物,例如氮化钽、氮化钛、氧化钽或氧化钛。根据本发明的优选实施例,金属化合物层14为氮化钛。虚置栅极材料层16可以为一多晶硅层。掩模层18可以为氮化硅、氧化硅或氮氧化硅。
图2和图3接续图1的制作工艺示意图,其中图3为图2中沿切线AA’所绘示的侧视图。请同时参阅图2和图3,以金属化合物层14为停止层,图案化虚置栅极材料层16以形成一虚置栅极16’和至少一孔洞20穿透虚置栅极16’,在本实施例中以形成多个孔洞20为例,然而在不同实施例中也可以只形成一个孔洞20,由于掩模层18和虚置栅极16’完全重叠,所以图2中掩模层18的位置,即是虚置栅极16’的位置,由图2可知,虚置栅极16’为一连续结构。详细来说形成虚置栅极16’的方式包含利用一光掩模(图未示)先图案化掩模层18,之后以掩模层18为掩模并且以金属化合物层14为停止层,蚀刻虚置栅极材料层16后形成虚置栅极16’和孔洞20。值得注意的是:因为金属化合物层14作为停止层,因此在形成虚置栅极16’之后,金属化合物层14依然是连续结构,换而言之金属化合物层14不但保留在虚置栅极16’之下,也位于孔洞20的底部并且从孔洞20曝露出来。
如图4所示,形成间隙壁22覆盖虚置栅极16’的侧壁和孔洞20侧壁,然后进行一离子注入制作工艺,以间隙壁22和掩模层18为掩模注入掺质以形成掺杂区24,掺杂区24分别形成在虚置栅极16’的两侧和孔洞20的正下方基底10中。形成在虚置栅极16’的两侧的掺杂区24作为源极/漏极掺杂区。视产品不同需求,注入的掺质可以为P型掺杂或N型掺质。然后形成一绝缘材料层26覆盖虚置栅极16’和金属化合物层14并且填入孔洞20。详细来说绝缘材料层26可以包含一蚀刻停止层26a和一层间介电层26b,蚀刻停止层26a较佳为氮化硅,层间介电层26b较佳为氧化硅。详细形成绝缘材料层26的步骤包含首先形成一蚀刻停止层26a顺应地覆盖金属化合物层14、虚置栅极16’和填入孔洞20,之后形成一层间介电层26b覆盖蚀刻停止层26a并且填入孔洞20。接着以蚀刻停止层26a为停止层,利用化学机械研磨制作工艺平坦化层间介电层26b使得层间介电层26b的上表面和蚀刻停止层26a的上表面切齐。如图5所示,继续平坦化层间介电层26b、蚀刻停止层26a、掩模层18和间隙壁22,直至虚置栅极16’曝露出来,此时保留在孔洞20中的绝缘材料层26(包含蚀刻停止层26a和层间介电层26b)构成至少一绝缘材料结构28。由于在本实施例中有多个孔洞20,因此也会有多个绝缘材料结构28,其中绝缘材料结构28包含氮化硅、氧化硅、氧化硅-氮化硅-氧化硅、氮碳化硅(SiCN)、氮氧化硅(SiON)或氮碳氧化硅(SiOCN)。
如图6所示,移除虚置栅极16’以形成至少一沟槽30,在本实施例中以三个沟槽30为例,此外在移除虚置栅极16’时绝缘材料结构28并未被移除。图7和图8为接续图6的制作工艺示意图,其中图8为图7中沿着切线BB’所绘示的侧视图。请同时参阅图7和图8,形成一金属栅极材料层(图未示)覆盖并填入沟槽30,之后进行一平坦化制作工艺以移除在沟槽30之外的金属栅极材料层,也就是以层间介电层26b作为平坦化制作工艺的停止层,而余留在沟槽30内的金属栅极材料层即成为金属栅极32,金属栅极32围绕绝缘材料结构28,此时本发明的高压晶体管结构100业已完成。金属栅极32可以包含一金属层和一功函数层。金属层为具有较佳填洞能力的单层金属层或复合金属层,其可包含铝(Al)、钛(Ti)、钽(Ta)、钨(W)、铌(Nb)、钼(Mo)、铜(Cu)、氮化钛(TiN)、碳化钛(TiC)、氮化钽(TaN)、钛钨(Ti/W)、或钛与氮化钛(Ti/TiN),功函数层可为一P型功函数层或一N型功函数层。P型功函数层包含氮化钛、碳化钛、氮化钽、碳化钽、碳化钨或氮化铝钛。N型功函数层包含铝化钛、铝化锆、铝化钨、铝化钽或铝化铪(HfAl)。
此外,平坦化制作工艺较佳是利用化学机械研磨制作工艺进行,然而因为高压晶体管结构100的金属栅极32面积大,造成在进行化学机械研磨制作工艺到达平坦化制作工艺的停止层后容易发生过度研磨(over-polishing)而在金属栅极32产生凹陷(dishing),然而本发明通过在金属栅极32中加入绝缘材料结构28,让金属栅极32的面积不会是一大片而是有较硬的绝缘材料结构28穿插其中作为支撑,如此即可避免过度研磨和凹陷。
除此之外,如图3中的步骤说明,图案化形成虚置栅极16’时是以金属化合物层14作为停止层,所以造成绝缘材料结构28其下方有金属化合物层14,此金属化合物层14为连续结构,同时设置于绝缘材料结构28和金属栅极32下方。因此虽然在绝缘材料结构28的位置没有金属栅极32,金属栅极32的电流可以通过在绝缘材料结构28下方的金属化合物层14传导,因此金属栅极32的电流不会因为绝缘材料结构28而中断,如此在金属栅极32和绝缘材料结构28下方的电场也会因为有连续的金属化合物层14将电流连通,而成为均匀的电场。
因为有连续的金属化合物层14将电流连通,若是产品需要,也可以将绝缘材料结构28的位置设计成将金属栅极32分割成数块不相连的金属栅极块,后续操作完全利用金属化合物层14电连接数块不相连的金属栅极块。
如图7和图8所示,一种高压晶体管结构100包含一基底10,一金属栅极32设置于基底10上,金属栅极32为一连续结构,至少一绝缘材料结构28穿透金属栅极32,绝缘材料结构28的数量可以为一个,也可以为多个,在本实施例中以多个绝缘材料结构28为例,一金属化合物层14设置于金属栅极32和基底10之间以及绝缘材料结构28和基底10之间,其中金属化合物层14为连续结构,一栅极介电层12设置于金属化合物层14下方并且接触基底10,金属化合物层14接触栅极介电层12、金属栅极32以及绝缘材料结构28。
以下示例数种不同的绝缘材料结构28的形状,但不限于此,依据不同的产品需求,绝缘材料结构28可以设计成不同外形。如图7所示,绝缘材料结构28在平行于基底10的上表面的方向Y上包含一截面,此截面可以为矩形。如图9所示,绝缘材料结构28在平行于基底10的上表面的方向Y上的截面可以为圆形。如图10所示,绝缘材料结构28在平行于基底10的上表面的方向Y上的截面可以为十字形。
若是有多个绝缘材料结构28,各个绝缘材料结构28可以不彼此接触,如图7和图9的情况。然而如图10中的情况,多个绝缘材料结构28也可以互相接触连接。
本发明特意在图案化虚置栅极16’时以金属化合物层14为停止层,使得后续形成的金属栅极32下方和绝缘材料结构28下方有连续不断的金属化合物层14,此金属化合物层14可以保持金属栅极32下方和绝缘材料结构28下方的电场均匀,让高压晶体管结构100有更穏定的效能。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (19)

1.一种高压晶体管结构,其特征在于,包含:
基底;
金属栅极,设置于该基底上;
至少一绝缘材料结构,穿透该金属栅极;
金属化合物层,设置于该金属栅极和该基底之间以及该绝缘材料结构和该基底之间,其中该金属化合物层为连续结构;以及
栅极介电层,设置于该金属化合物层下方并且接触该基底。
2.如权利要求1所述的高压晶体管结构,其中该金属化合物层接触该栅极介电层、该金属栅极以及该绝缘材料结构。
3.如权利要求1所述的高压晶体管结构,其中该金属化合物层包含金属氧化物或金属氮化物。
4.如权利要求1所述的高压晶体管结构,其中该绝缘材料结构包含氮化硅、氧化硅、氧化硅-氮化硅-氧化硅、氮碳化硅(SiCN)、氮氧化硅(SiON)或氮碳氧化硅(SiOCN)。
5.如权利要求1所述的高压晶体管结构,其中该绝缘材料结构在平行于该基底的上表面的方向上包含一截面,该截面包含矩形、十字形或圆形。
6.如权利要求1所述的高压晶体管结构,其中多个该绝缘材料结构穿透该金属栅极。
7.如权利要求6所述的高压晶体管结构,其中该多个绝缘材料结构彼此不接触。
8.如权利要求6所述的高压晶体管结构,其中该多个绝缘材料结构彼此接触。
9.如权利要求1所述的高压晶体管结构,其中该金属栅极为连续结构。
10.一种高压晶体管结构的制作方法,包含:
提供基底;
依序形成栅极介电层、金属化合物层和虚置栅极材料层覆盖该基底;
以该金属化合物层为停止层,图案化该虚置栅极材料层以形成虚置栅极和至少一孔洞穿透该虚置栅极;
形成绝缘材料层覆盖该虚置栅极和该金属化合物层并且该绝缘材料层填入该孔洞,其中填入该孔洞的绝缘材料层构成至少一绝缘材料结构;
平坦化该绝缘材料层以暴露出该虚置栅极的上表面;
移除该虚置栅极以形成沟槽;以及
形成金属栅极填入该沟槽并且该金属栅极围绕该绝缘材料结构。
11.如权利要求10所述的高压晶体管结构的制作方法,其中该金属化合物层包含金属氧化物或金属氮化物。
12.如权利要求10所述的高压晶体管结构的制作方法,其中该绝缘材料结构包含氮化硅、氧化硅、氧化硅-氮化硅-氧化硅、氮碳化硅(SiCN)、氮氧化硅(SiON)或氮碳氧化硅(SiOCN)。
13.如权利要求10所述的高压晶体管结构的制作方法,其中在移除该虚置栅极时,该绝缘材料结构未被移除。
14.如权利要求10所述的高压晶体管结构的制作方法,另包含在形成该虚置栅极的同时一并形成多个该孔洞穿透该虚置栅极。
15.如权利要求14所述的高压晶体管结构的制作方法,其中该绝缘材料层填入各该孔洞以形成多个绝缘材料结构。
16.如权利要求15所述的高压晶体管结构的制作方法,其中该多个绝缘材料结构彼此不接触。
17.如权利要求15所述的高压晶体管结构的制作方法,其中该多个绝缘材料结构彼此接触。
18.如权利要求10所述的高压晶体管结构的制作方法,其中该绝缘材料结构在平行于该基底的上表面的方向上包含一截面,该截面包含矩形、十字形或圆形。
19.如权利要求10所述的高压晶体管结构的制作方法,其中该金属栅极为连续结构。
CN202010650267.0A 2020-07-08 2020-07-08 高压晶体管结构及其制作方法 Active CN113921601B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202010650267.0A CN113921601B (zh) 2020-07-08 2020-07-08 高压晶体管结构及其制作方法
US16/936,442 US11251279B2 (en) 2020-07-08 2020-07-23 High voltage transistor structure and method of fabricating the same
US17/564,104 US11610973B2 (en) 2020-07-08 2021-12-28 High voltage transistor structure and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010650267.0A CN113921601B (zh) 2020-07-08 2020-07-08 高压晶体管结构及其制作方法

Publications (2)

Publication Number Publication Date
CN113921601A CN113921601A (zh) 2022-01-11
CN113921601B true CN113921601B (zh) 2023-07-11

Family

ID=79173865

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010650267.0A Active CN113921601B (zh) 2020-07-08 2020-07-08 高压晶体管结构及其制作方法

Country Status (2)

Country Link
US (2) US11251279B2 (zh)
CN (1) CN113921601B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117352490A (zh) 2022-06-21 2024-01-05 长鑫存储技术有限公司 半导体结构及其制造方法、存储芯片、电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034826A (zh) * 2009-09-24 2011-04-27 旺宏电子股份有限公司 半导体元件及其制造方法
CN102832214A (zh) * 2011-06-14 2012-12-19 台湾积体电路制造股份有限公司 大尺寸器件及其在后栅极工艺中的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140179093A1 (en) * 2012-12-20 2014-06-26 GlobalFoundries, Inc. Gate structure formation processes
US10043802B2 (en) * 2015-04-17 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with additional oxide layer
KR102474431B1 (ko) * 2015-12-08 2022-12-06 삼성전자주식회사 반도체 소자의 제조방법
US10096596B2 (en) * 2015-12-15 2018-10-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having a plurality of gate structures
TWI682546B (zh) * 2016-05-24 2020-01-11 聯華電子股份有限公司 高壓金屬氧化物半導體電晶體及其製作方法
WO2018125174A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Access transmission gate
US11094788B2 (en) * 2019-08-21 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034826A (zh) * 2009-09-24 2011-04-27 旺宏电子股份有限公司 半导体元件及其制造方法
CN102832214A (zh) * 2011-06-14 2012-12-19 台湾积体电路制造股份有限公司 大尺寸器件及其在后栅极工艺中的制造方法

Also Published As

Publication number Publication date
US20220123121A1 (en) 2022-04-21
CN113921601A (zh) 2022-01-11
US11251279B2 (en) 2022-02-15
US20220013648A1 (en) 2022-01-13
US11610973B2 (en) 2023-03-21

Similar Documents

Publication Publication Date Title
CN107492542B (zh) 半导体组件及其制造方法
US11264386B2 (en) Semiconductor device
KR20180035014A (ko) 반도체 장치
US11289470B2 (en) Method of manufacturing trench transistor structure
CN111129123B (zh) 接触场板蚀刻的组合蚀刻停止层、集成芯片及其形成方法
US11495494B2 (en) Methods for reducing contact depth variation in semiconductor fabrication
KR101057243B1 (ko) 반도체 장치
CN111129146A (zh) 半导体装置
CN113555344B (zh) 半导体存储器元件及其制备方法
CN111081757A (zh) 半导体装置与其制作方法
KR102494312B1 (ko) 반도체 디바이스를 위한 콘택트 및 그 형성 방법
CN112216738A (zh) 集成芯片及其形成方法
CN110970433B (zh) 半导体器件
CN113921601B (zh) 高压晶体管结构及其制作方法
US20220367452A1 (en) Semiconductor structure and method of forming thereof
US20230079697A1 (en) Semiconductor device
JP2013191808A (ja) 半導体装置及び半導体装置の製造方法
KR102611247B1 (ko) 패턴 게이트를 갖는 반도체 금속 산화물 트랜지스터 및 이를 형성하는 방법
US20220278209A1 (en) High voltage field effect transistors with metal-insulator-semiconductor contacts and method of making the same
KR101302106B1 (ko) 트랜치 구조의 mim커패시터 및 그 제조 방법
CN216563142U (zh) 半导体结构
US20220208673A1 (en) Semiconductor device
CN114038903A (zh) 半导体结构及其制作方法
CN116264231A (zh) 包括栅接触部的集成电路器件
KR20230041126A (ko) 반도체 소자 및 이의 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant