CN116264231A - 包括栅接触部的集成电路器件 - Google Patents

包括栅接触部的集成电路器件 Download PDF

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CN116264231A
CN116264231A CN202211566542.6A CN202211566542A CN116264231A CN 116264231 A CN116264231 A CN 116264231A CN 202211566542 A CN202211566542 A CN 202211566542A CN 116264231 A CN116264231 A CN 116264231A
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region
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integrated circuit
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郑润永
裵德汉
朴柱勋
李宥利
洪秀姸
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种集成电路器件，包括：衬底，包括器件区和场区；有源区，在器件区中沿第一方向延伸；第一栅结构，在器件区和场区中沿与第一方向相交的第二方向延伸；第二栅结构，在第一方向上与第一栅结构间隔开；第一栅接触部，在器件区中设置在第一栅结构上；以及第二栅接触部，在场区中设置在第二栅结构上，其中，第一栅接触部和第二栅接触部设置在比第一栅结构的上端低的水平处，并且其中，第一栅接触部的第一最小宽度和第二栅接触部的第二最小宽度彼此不同。

Description

包括栅接触部的集成电路器件
相关申请的交叉引用
本申请要求于2021年12月15日在韩国知识产权局递交的韩国专利申请No.10-2021-0179573的优先权，其全部公开内容通过引用合并于此。
技术领域
本发明构思的示例性实施例涉及一种包括栅接触部的集成电路器件。
背景技术
根据元件的精细度，正在开发集成电路器件的高集成度，并且对减小集成电路器件的面积的需求正在增加。因此，正在开发并且期望不仅能够在减小接触部、过孔和布线所占据的面积的同时提供接触部、过孔和布线之间的绝缘距离，而且能够增加集成电路器件的可靠性的技术。
发明内容
根据本发明构思的示例性实施例，一种集成电路器件包括：衬底，包括器件区和场区；有源区，在器件区中沿第一方向延伸；第一栅结构，在器件区和场区中沿与第一方向相交的第二方向延伸；第二栅结构，在第一方向上与第一栅结构间隔开；第一栅接触部，在器件区中设置在第一栅结构上；以及第二栅接触部，在场区中设置在第二栅结构上，其中，第一栅接触部和第二栅接触部设置在比第一栅结构的上端低的水平处，并且其中，第一栅接触部的第一最小宽度和第二栅接触部的第二最小宽度彼此不同。
根据本发明构思的示例性实施例，一种集成电路器件包括：衬底，包括器件区和场区；有源区，在器件区中沿第一方向延伸；第一栅电极，在器件区和场区中沿与第一方向相交的第二方向延伸；第一栅封盖层，设置在第一栅电极上；第二栅电极，在第一方向上与第一栅电极间隔开；第二栅封盖层，设置在第二栅电极上；第一栅接触部，与第一栅电极重叠，并在器件区中延伸穿过第一栅封盖层；以及第二栅接触部，与第二栅电极重叠，并在场区中延伸穿过第二栅封盖层，其中，第一栅接触部的第一最小宽度和第二栅接触部的第二最小宽度彼此不同。
根据本发明构思的示例性实施例，一种集成电路器件包括：衬底，包括器件区和场区；有源区，在器件区中沿第一方向延伸；第一栅电极，在器件区和场区中沿与第一方向相交的第二方向延伸；第一栅封盖层，设置在第一栅电极上；第二栅电极，在第一方向上与第一栅电极间隔开；第二栅封盖层，设置在第二栅电极上；第一栅接触部，在器件区中连接到第一栅电极并穿透第一栅封盖层；第二栅接触部，在场区中连接到第二栅电极并穿透第二栅封盖层；源/漏区，设置在有源区上；以及源/漏接触部，设置在源/漏区上，其中，第一栅接触部的第一最小宽度大于第二栅接触部的第二最小宽度。
附图说明
图1是示出了根据本发明构思的示例性实施例的集成电路器件的平面布局。
图2A是沿图1的线I-I'和II-II'截取的截面图。
图2B是沿图1的线III-III'和IV-IV'截取的截面图。
图3是根据本发明构思的示例性实施例的沿图1的线I-I'和II-II'截取的截面图。
图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图12A、图12B、图13A、图13B、图14A和图14B是示出了根据工艺顺序来示出根据本发明构思的示例性实施例的用于制造集成电路器件的方法的截面图。
图15A示出了根据本发明构思的示例性实施例的沿图1的线I-I'和II-II'截取的截面图。
图15B示出了根据本发明构思的示例性实施例的沿图1的线III-III'和IV-IV'截取的截面图。
具体实施方式
图1是示出了根据本发明构思的示例性实施例的集成电路器件的平面布局。图2A示出了沿图1的线I-I'和II-II'截取的截面图。图2B示出了沿图1的线III-III'和IV-IV'截取的截面图。
参考图1、图2A和图2B，集成电路器件100可以构成包括晶体管的逻辑单元。例如，晶体管可以是鳍式场效应晶体管(FinFET)。集成电路器件100可以包括形成在衬底101上的逻辑单元LC。
集成电路器件100可以包括衬底101。衬底101可以具有在第一方向(例如，X方向)和第二方向(例如，Y方向)上延伸的板的形式，并且可以包括在第三方向(例如，Z方向)上突出的部分。例如，第一方向(例如，X方向)和第二方向(例如，Y方向)可以在同一平面中彼此垂直相交。例如，第三方向(例如，Z方向)可以与第一方向(例如，X方向)和第二方向(例如，Y方向)垂直相交。衬底101可以包括诸如Si或Ge之类的半导体，或者可以包括诸如SiGe、SiC、GaAs、InAs或InP之类的化合物半导体。衬底101可以包括导电区，并且例如可以包括掺杂有杂质的阱或掺杂有杂质的结构。
逻辑单元LC可以包括第一器件区RX1和第二器件区RX2。第一器件区RX1和第二器件区RX2可以在第二方向(例如，Y方向)上彼此间隔开，并且场区FD介于它们之间。有源区105可以形成在第一器件区RX1和第二器件区RX2中。有源区105可以是从衬底101突出的鳍型有源区。有源区105可以在第一方向(例如，X方向)上延伸，并且可以在第二方向(例如，Y方向)上彼此间隔开。
第一元件隔离层107可以覆盖有源区105的下部。有源区105可以向上突出超过第一元件隔离层107的上表面。第二元件隔离层109可以设置在衬底101上的场区FD中。由衬底101和第一元件隔离层107形成的深沟槽DT可以形成在场区FD中，并且第二元件隔离层109可以填充深沟槽DT。第二元件隔离层109可以将第一器件区RX1和第二器件区RX2彼此分开。例如，第一元件隔离层107和第二元件隔离层109中的每一个可以包括氧化物。
栅结构GS可以在第二方向(例如，Y方向)上延伸，同时与有源区105相交。栅结构GS可以形成为与第一器件区RX1、场区FD和第二器件区RX2中的每一个相交。栅结构GS可以设置在第一元件隔离层107和第二元件隔离层109上，并且可以覆盖有源区105的从第一元件隔离层107突出的上部的一部分。栅结构GS可以在第一方向(例如，X方向)上具有相同的宽度，并且可以在第一方向(例如，X方向)上以均匀的间距布置。
晶体管可以沿着第一器件区RX1和第二器件区RX2中的每一个中的栅结构GS形成。每个晶体管可以是例如具有沟道形成在鳍型有源区105上方的三维结构的MOS晶体管。在本发明构思的示例性实施例中，第一器件区RX1可以是NMOS晶体管区，而第二器件区RX2可以是PMOS晶体管区。
每个栅结构GS可以包括栅电极123、栅间隔物SP、栅绝缘层121和栅封盖层125。栅电极123可以具有金属氮化物层、金属层、导电封盖层和间隙填充金属层彼此顺序堆叠的结构。例如，金属氮化物层和金属层可以包括Ti、Ta、W、Ru、Nb、Mo和/或Hf中的至少一种。例如，间隙填充金属层可以包括W或Al。栅电极123可以包括功函数含金属层。功函数含金属层可以包括例如Ti、W、Ru、Nb、Mo、Hf、Ni、Co、Pt、Yb、Tb、Dy、Er和/或Pd中的至少一种。
栅间隔物SP可以设置在栅电极123的相对侧壁上。栅间隔物SP可以包括例如SiN、SiOCN、SiCN或其组合，但不限于此。例如，每个栅间隔物SP可以由多层构成；然而，本发明构思不限于此。
栅绝缘层121可以介于栅电极123和栅间隔物SP之间、栅电极123和有源区105之间、栅电极123和第一元件隔离层107之间、以及栅电极123和第二元件隔离层109之间。栅绝缘层121可以沿着从第一元件隔离层107向上突出的有源区105的轮廓延伸。栅绝缘层121可以包括例如氧化硅、高k电介质或其组合。高k电介质可以包括例如金属氧化物和/或金属氮氧化物中的至少一种。
在本发明构思的示例性实施例中，在第一器件区RX1和第二器件区RX2中的每一个中沿着栅结构GS形成的晶体管可以包括使用负电容器的负电容(NC)FET。在这种情况下，例如，栅绝缘层121可以包括具有铁电特性的铁电材料膜和具有顺电特性的顺电材料膜。
铁电材料膜可以具有负电容，而顺电材料膜可以具有正电容。例如，当两个或更多个电容器串联连接并且每个电容器的电容具有正值时，电容器的总电容可以低于每个单独的电容器的电容。另外，当串联连接的两个或更多个电容器中的至少一个电容器的电容具有负值时，电容器的总电容可以具有正值，并且总电容可以大于每个单独的电容器的绝对值。
当具有负电容的铁电材料膜和具有正电容的顺电材料膜串联连接时，彼此串联连接的铁电材料膜和顺电材料膜的总电容值可以增加。包括铁电材料膜的晶体管可以使用如上所述的总电容值的增加而在常温下具有小于约60mV/decade的亚阈值摆幅(SS)。
铁电材料膜可以具有铁电特性。铁电材料膜可以包括例如氧化铪、氧化铪锆、氧化钡锶钛、氧化钡钛和/或氧化铅锆钛中的至少一种。这里，例如，氧化铪锆可以是通过用锆(Zr)掺杂氧化铪而产生的材料。在另一示例中，氧化铪锆可以是铪(Hf)、锆(Zr)和氧(O)的化合物。
铁电材料膜还可以包括掺杂剂。例如，掺杂剂可以包括铝(Al)、钛(Ti)、铌(Nb)、镧(La)、钇(Y)、镁(Mg)、硅(Si)、钙(Ca)、铈(Ce)、镝(Dy)、铒(Er)、钆(Gd)、锗(Ge)、钪(Sc)、锶(Sr)和/或锡(Sn)中的至少一种。包括在铁电材料膜中的掺杂剂的种类可以根据哪种铁电材料被包括在铁电材料膜中而改变。
当铁电材料膜包括氧化铪时，包括在铁电材料膜中的掺杂剂可以包括例如钆(Gd)、硅(Si)、锆(Zr)、铝(Al)和/或钇(Y)中的至少一种。当掺杂剂是铝(Al)时，铁电材料膜可以包括约3至约8原子百分比(at％)的铝。这里，掺杂剂的比率可以是铝与铪和铝之和的比率。当掺杂剂是硅(Si)时，铁电材料膜可以包括约2至约10at％的硅。当掺杂剂是钇(Y)时，铁电材料膜可以包括约2至约10at％的钇。当掺杂剂是钆(Gd)时，铁电材料膜可以包括约1至约7at％的钆。当掺杂剂是锆(Zr)时，铁电材料膜可以包括约50至约80at％的锆。
顺电材料膜可以具有顺电特性。顺电材料膜可以包括例如氧化硅和/或具有高介电常数的金属氧化物中的至少一种。包括在顺电材料膜中的金属氧化物可以包括例如氧化铪、氧化锆和/或氧化铝中的至少一种，并且本发明构思不限于此。
铁电材料膜和顺电材料膜可以包括彼此相同的材料。铁电材料膜具有铁电特性，但顺电材料膜可能不具有铁电特性。例如，当铁电材料膜和顺电材料膜都包括氧化铪时，包括在铁电材料膜中的氧化铪的晶体结构可以与包括在顺电材料膜中的氧化铪的晶体结构不同。
铁电材料膜可以具有表现出铁电特性的厚度。铁电材料膜的厚度可以是例如约0.5至约10nm，并且本发明构思不限于此。例如，表现出铁电特性的预定厚度可以根据不同的铁电材料而改变，并且因此，铁电材料膜的厚度可以根据其铁电材料而改变。
在本发明构思的示例性实施例中，栅绝缘层可以包括一个铁电材料膜。在本发明构思的示例性实施例中，栅绝缘层可以包括彼此间隔开的多个铁电材料膜。在本发明构思的示例性实施例中，栅绝缘膜可以具有多个铁电材料膜和多个顺电材料膜彼此交替堆叠的堆叠膜结构。
栅封盖层125可以设置在栅电极123、栅绝缘层121和栅间隔物SP上。例如，栅封盖层125可以包括氮化硅。
在本发明构思的示例性实施例中，栅封盖层125可以在第二方向(例如，Y方向)上具有不同的高度。栅封盖层125可以在第一器件区RX1和第二器件区RX2以及场区FD中具有不同的高度。栅封盖层125可以在第一器件区RX1和第二器件区RX2中具有第一高度Ta，并且可以在场区FD中具有大于第一高度Ta的第二高度Tb。这里，第一高度Ta可以是第一器件区RX1和第二器件区RX2中的栅封盖层125的最大高度，而第二高度Tb可以是场区FD中的栅封盖层125的最大高度。此外，参考衬底101的上表面，第一器件区RX1和第二器件区RX2以及场区FD中的栅封盖层125的最上端E1和E2的水平可以彼此不同。第一器件区RX1和第二器件区RX2中的栅封盖层125的最上端E1的水平LVa可以低于场区FD中的栅封盖层125的最上端E2的水平LVb。栅封盖层125的最下端的水平在第二方向(例如，Y方向)上可以是均匀的。栅结构GS的高度可以根据栅封盖层125的高度变化而在第二方向(例如，Y方向)上改变，并且因此，栅结构GS可以在场区FD中具有比在第一器件区RX1和第二器件区RX2中大的高度。
在有源区105中，可以形成凹陷区，有源区105的从第一元件隔离层107向上突出的上部从该凹陷区部分地去除。例如，凹陷区可以形成在有源区105的从第一元件隔离层107向上突出的相邻上部之间。凹陷区可以形成在栅结构GS之间。源/漏区S/D可以设置在栅结构GS之间的凹陷区中。源/漏区S/D可以包括外延生长的半导体层。例如，源/漏区S/D可以包括外延生长的Si层、外延生长的SiC层和/或外延生长的SiGe层中的至少一种。
源/漏接触图案CA可以设置在源/漏区S/D上。源/漏区S/D可以经由源/漏接触图案CA电连接到上布线层。每个源/漏接触图案CA可以包括阻挡层145和插塞层147。阻挡层145可以覆盖插塞层147的侧壁和底表面。例如，阻挡层145可以包括Ti、Ta、TiN、TaN或其组合，而插塞层147可以包括W、Co、Cu、Ru、Mn或其组合。
硅化物膜141可以形成在源/漏区S/D和源/漏接触图案CA之间。例如，硅化物膜141可以包括硅化钛。接触间隔物143可以形成在源/漏接触图案CA的侧壁处。例如，接触间隔物143可以包括SiN、SiCN、SiCON或其组合，并且本发明构思不限于此。
源/漏接触图案CA可以基于其各自的位置而具有不同的高度。源/漏接触图案CA可以包括第一部分P1和第二部分P2，该第一部分P1和第二部分P2在具有彼此不同的高度的同时互连以彼此集成。在有源区105上，源/漏接触图案CA的第一部分P1可以具有第一高度，而源/漏接触图案CA的第二部分P2可以具有大于第一高度的第二高度。在本发明构思的示例性实施例中，参考衬底101的上表面，第一部分P1的上端的水平低于栅电极123的上表面的水平，并且第二部分P2的上端的水平可以高于栅电极123的上表面的水平。本发明构思不限于上述条件，并且第一部分P1和第二部分P2的相应上端的水平可以高于栅电极123的上表面的水平。
栅接触部CB可以连接到栅电极123，同时在第三方向(例如，Z方向)上延伸穿过栅封盖层125。参考衬底101的上表面，栅接触部CB可以设置在比栅结构GS的最上端的水平LVb低的水平处。例如，栅接触部CB可以设置在比栅封盖层125的最上端E2低的水平处。
在本发明构思的示例性实施例中，栅结构GS可以包括在第一方向(例如，X方向)上彼此间隔开的第一栅结构GS1和第二栅结构GS2，并且栅接触部CB可以包括第一栅接触部CB1和第二栅接触部CB2。第一栅接触部CB1可以连接到第一栅结构GS1，并且第二栅接触部CB2可以连接到第二栅结构GS2。第一栅接触部CB1可以连接到第一器件区RX1中的第一栅结构GS1，并且第二栅接触部CB2可以连接到场区FD中的第二栅结构GS2。
第一栅接触部CB1可以连接到栅电极123(第一栅电极)，同时延伸穿过第一栅结构GS1的栅封盖层125(第一栅封盖层)。第一栅接触部CB1可以具有第一最小宽度Wa。第一最小宽度Wa可以是第一栅接触部CB1在第一方向(例如，X方向)上的宽度，并且可以是第一栅接触部CB1的一个侧壁的下端和第一栅接触部CB1的面向该一个侧壁的另一侧壁的下端之间的最小水平距离。例如，第一栅接触部CB1可以具有锥形形状。第一栅接触部CB1可以具有第一高度Ha。第一高度Ha可以是从第一栅接触部CB1的下端到上端的竖直距离。
第二栅接触部CB2可以连接到栅电极123(第二栅电极)，同时延伸穿过第二栅结构GS2的栅封盖层125(第二栅封盖层)。第二栅接触部CB2可以具有与第一最小宽度Wa不同的第二最小宽度Wb。第二最小宽度Wb可以是第二栅接触部CB2在第一方向(例如，X方向)上的宽度，并且可以是第二栅接触部CB2的一个侧壁的下端和第二栅接触部CB2的面向该一个侧壁的另一侧壁的下端之间的最小水平距离。例如，第二最小宽度Wb可以小于第一最小宽度Wa。例如，第二栅接触部CB2可以具有锥形形状。第二栅接触部CB2可以具有第二高度Hb。第二高度Hb可以是从第二栅接触部CB2的下端到上端的竖直距离。第二高度Hb可以大于第一高度Ha。由于第一栅接触部CB1设置在第一器件区RX1中，所以第一栅接触部CB1可以有助于通过减小场区FD所需的面积来减小逻辑单元LC的尺寸。此外，与第二栅接触部CB2相比，第一栅接触部CB1可以具有相对较大的宽度和相对较小的长度，并且因此，可以减小电阻值。
在本发明构思的示例性实施例中，第一栅接触部CB1的第一最大宽度可以大于第二栅接触部CB2的第二最大宽度。第一最大宽度可以是第一栅接触部CB1在第一方向(例如，X方向)上的宽度，并且可以是第一栅接触部CB1的上表面的宽度。第二最大宽度可以是第二栅接触部CB2在第一方向(例如，X方向)上的宽度，并且可以是第二栅接触部CB2的上表面的宽度。结果，第一栅接触部CB1在其上端和下端处都可以具有比第二栅接触部CB2大的宽度，并且因此，可以具有比第二栅接触部CB2低的电阻值。
在本发明构思的示例性实施例中，在与第一栅接触部CB1的相对侧相邻设置的源/漏接触图案CA中的每一个中包括的第二部分P2可以在第一方向(例如，X方向)上不与第一栅接触部CB1重叠。具有相对较小的高度的第一部分P1可以设置在第一栅接触部CB1的相对侧处，并且因此，可以确保第一栅接触部CB1和源/漏接触图案CA之间的距离，由此防止寄生电容的生成。
掩埋绝缘层150可以设置在源/漏接触图案CA上。掩埋绝缘层150可以设置在源/漏接触图案CA的第一部分P1上，并且可以接触第二部分P2的侧表面的至少一部分。掩埋绝缘层150可以覆盖栅封盖层125的一部分。掩埋绝缘层150可以包括例如氧化硅、SiOC、SiOCN、SiON、SiCN、SiN或其组合，并且本发明构思不限于此。
第一层间绝缘层110可以设置在第一元件隔离层107和第二元件隔离层109上。第一层间绝缘层110可以设置在场区FD中的栅结构GS之间。例如，第一层间绝缘层110可以设置在场区FD中的栅结构GS的相对侧表面上。第一层间绝缘层110可以覆盖源/漏区S/D、接触间隔物143和掩埋绝缘层150。第二层间绝缘层170可以设置在第一层间绝缘层110上。第二层间绝缘层170可以覆盖第一器件区RX1和第二器件区RX2中的栅封盖层125的上表面和掩埋绝缘层150的上表面。第二层间绝缘层170可以覆盖场区FD中的栅封盖层125的上表面和第一层间绝缘层110的上表面。
第一层间绝缘层110和第二层间绝缘层170中的每一个可以包括例如氧化物、氮化物、具有约2.2至约2.4的超低介电常数K的超低k电介质或其组合。例如，第一层间绝缘层110和第二层间绝缘层170中的每一个可以包括原硅酸四乙酯(TEOS)、高密度等离子体(HDP)氧化物、硼磷硅玻璃(BPSG)、可流动化学气相沉积(FCVD)氧化物、SiON、SiN、SiOC、SiCOH或其组合。
第一过孔VA1可以设置在源/漏接触图案CA上。例如，第一过孔VA1可以接触源/漏接触图案CA的第二部分P2的上表面，同时延伸穿过第二层间绝缘层170。第二过孔VA2可以设置在栅接触部CB上。例如，第二过孔VA2可以接触栅接触部CB的上表面，同时延伸穿过第二层间绝缘层170。
第一过孔VA1和第二过孔VA2中的每一个可以包括例如阻挡层和掩埋金属层。例如，阻挡层可以包括Ti、Ta、TiN、TaN或其组合，并且掩埋金属层可以包括Co、Cu、W、Ru、Mn或其组合。
在逻辑单元LC中，电力线VDD可以经由源/漏接触图案CA的一部分连接到设置在第一器件区RX1中的有源区105，并且地线VSS可以经由源/漏接触图案CA的另一部分连接到设置在第二器件区RX2中的有源区105。电力线VDD和地线VSS可以设置在比源/漏接触图案CA的上表面高的水平处。电力线VDD和地线VSS中的每一个可以包括例如阻挡层和导电布线层。阻挡层可以包括例如Ti、Ta、TiN、TaN或其组合，并且导电布线层可以包括例如Co、Cu、W、其合金或其组合。
图3示出了根据本发明构思的示例性实施例的沿图1的线I-I'和II-II'截取的截面图。
参考图3，第一栅接触部CB1的第一最小宽度Wa'可以小于第二栅接触部CB2的第二最小宽度Wb'。由于第一栅接触部CB1具有相对较小的宽度，所以第一栅接触部CB1可以确保距与其相邻设置的源/漏接触图案CA的第二部分P2的距离，并且因此，可以减小寄生电容。此外，可以确保第一栅接触部CB1和源/漏接触图案CA的第二部分P2之间的工艺裕度，并且因此，可以防止第一栅接触部CB1和第二部分P2之间的短路。由于第二栅接触部CB2具有相对较大的宽度，所以第二栅接触部CB2可以减小电阻值。
在本发明构思的示例性实施例中，第一栅接触部CB1可以具有比第二栅接触部CB2小的最大宽度。这里，最大宽度可以是第一栅接触部CB1的上表面在第一方向X上的宽度。
图4A至图14B是示出了根据工艺顺序来示出根据本发明构思的示例性实施例的用于制造集成电路器件的方法的截面图。图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A、图13A和图14A是沿图1中的线I-I'和II-II'截取的并参考工艺顺序示出的截面图。图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B、图13B和图14B是沿图1中的线III-III'和IV-IV'截取的并参考工艺顺序示出的截面图。
参考图1、图4A和图4B，可以部分地蚀刻衬底101，由此形成从衬底101的上表面向上(例如，在Z方向上)突出并同时在第一方向(例如，X方向)上延伸的有源区105。有源区105可以是具有鳍形状的鳍型有源区。可以在第一器件区RX1和第二器件区RX2中的每一个中形成有源区105。
可以在有源区105的下侧壁上形成第一元件隔离层107。有源区105可以从第一元件隔离层107的上表面向上突出。可以蚀刻第一元件隔离层107的一部分和衬底101的一部分，由此形成将第一器件区RX1和第二器件区RX2彼此分开的深沟槽DT，并且可以形成第二元件隔离层109以填充深沟槽DT。可以在第一器件区RX1和第二器件区RX2之间的场区FD中形成第二元件隔离层109。场区FD可以与形成深沟槽DT和第二元件隔离层109的区域相对应。
参考图5A和图5B，可以形成虚设栅结构DG以在第二方向(例如，Y方向)上延伸同时与有源区105相交，并且可以形成在第一元件隔离层107和第二元件隔离层109上。每个虚设栅结构DG可以包括虚设栅线DL和虚设栅封盖层DC。例如，虚设栅线DL可以包括氧化硅和/或多晶硅，并且虚设栅封盖层DC可以包括氮化硅。
可以在每个虚设栅结构DG的相对侧壁处形成栅间隔物SP，并且可以部分地蚀刻在每个虚设栅结构DG的相对侧处暴露的有源区105，由此在每个虚设栅结构DG的相对侧处形成凹陷区。可以分别在凹陷区中形成源/漏区S/D。可以形成第一层间绝缘层110以在虚设栅结构DG之间覆盖第一元件隔离层107、第二元件隔离层109、源/漏区S/D和栅间隔物SP。
参考图6A和图6B，可以从图5A和图5B的所得结构中去除虚设栅结构DG，由此在栅间隔物SP之间形成栅空间。可以在栅空间中形成栅绝缘层121、栅电极123和栅封盖层125。首先，可以形成栅绝缘层121和栅电极123以填充栅空间。此后，可以通过回蚀刻工艺部分地去除栅绝缘层121和栅电极123的上部。在回蚀刻工艺期间，也可以部分地去除栅间隔物SP的上部。随后，可以形成栅封盖层125以覆盖栅绝缘层121、栅电极123和栅间隔物SP中的每一个的上表面。
在本发明构思的示例性实施例中，可以在形成栅绝缘层121之前形成覆盖有源区105的通过栅空间暴露的表面的界面层。可以通过氧化有源区105的一部分来形成界面层。
参考图7A和图7B，可以形成第一上绝缘层130以覆盖栅封盖层125的上表面和第一层间绝缘层110的上表面。此后，可以形成源/漏接触孔CH以延伸穿过第一上绝缘层130和第一层间绝缘层110，由此暴露源/漏区S/D。在形成源/漏接触孔CH的过程中，可以部分地蚀刻源/漏区S/D。随后，可以形成接触间隔物143以覆盖源/漏接触孔CH的内侧壁。可以通过形成共形地覆盖源/漏接触孔CH的内侧壁的绝缘层并通过各向异性蚀刻部分地蚀刻绝缘层来形成接触间隔物143。由于通过各向异性蚀刻部分地去除绝缘层，可以暴露源/漏区S/D，并且可以部分地去除源/漏区S/D。
可以在源/漏接触孔CH中形成硅化物层141并可以覆盖源/漏区S/D，并且可以在硅化物层141上形成源/漏接触部CP以填充源/漏接触孔CH。源/漏接触部CP可以包括阻挡层145和插塞层147。
参考图8A和图8B，可以形成蚀刻停止层ST以覆盖源/漏接触部CP和第一上绝缘层130的上表面，并且可以在蚀刻停止层ST上形成掩模图案MP。可以将掩模图案MP形成为与源/漏接触部CP的一部分竖直重叠。例如，可以将掩模图案MP形成为分别设置在与图1所示的第一过孔VA1相对应的位置处。
蚀刻停止层ST可以包括例如SiOC、SiN或其组合。掩模图案MP可以包括例如氧化硅、旋涂硬掩模、光刻胶层或其组合。
参考图9A和图9B，可以使用掩模图案MP作为蚀刻掩模通过蚀刻工艺来蚀刻蚀刻停止层ST，并且可以在第一蚀刻气氛中部分地蚀刻源/漏接触部CP的暴露部分。由于在第一蚀刻气氛中部分地蚀刻源/漏接触部CP的暴露部分，所以可以形成具有根据部分的不同位置而具有不同高度的部分的源/漏接触图案CA。可以将每个源/漏接触图案CA形成为包括第一部分P1和第二部分P2，该第一部分P1和第二部分P2在具有彼此不同的高度的同时互连以彼此集成。
第一蚀刻气氛可以是用于蚀刻构成源/漏接触部CP的含金属层的蚀刻气氛。第一蚀刻气氛可以是构成源/漏接触部CP的含金属层的蚀刻量大于分别构成栅封盖层125和第一上绝缘层130的绝缘层的蚀刻量的蚀刻气氛，但是分别构成栅封盖层125和第一上绝缘层130的绝缘层的蚀刻量大于0。
在本发明构思的示例性实施例中，在用于蚀刻源/漏接触部CP的暴露部分的第一蚀刻气氛中，构成源/漏接触部CP的含金属层(例如，钨层)的蚀刻量可以大于构成栅封盖层125的绝缘层(例如，氮化硅层)的蚀刻量，并且可以大于构成第一上绝缘层130的绝缘层(例如，氧化硅层)的蚀刻量。在第一蚀刻气氛中，构成栅封盖层125的绝缘层的蚀刻量可以大于构成第一上绝缘层130的绝缘层的蚀刻量。例如，构成源/漏接触部CP的含金属层的蚀刻量、构成栅封盖层125的绝缘层的蚀刻量、以及构成第一上绝缘层130的绝缘层的蚀刻量的比例可以是约6:3:1，并且本发明构思不限于此。
结果，可以蚀刻在使用掩模图案MP作为蚀刻掩模蚀刻源/漏接触部CP的暴露部分期间同时暴露于第一蚀刻气氛的栅封盖层125的部分和第一上绝缘层130的至少一部分。例如，可以去除几乎所有的第一上绝缘层130，因此，可以暴露栅封盖层125的上表面，并且可以部分地去除栅封盖层125的上部，由此使栅封盖层125具有减小的高度。
在第一蚀刻气氛中，栅封盖层125在第一器件区RX1和第二器件区RX2以及场区FD中可以具有不同的蚀刻量。例如，栅封盖层125可以在第一蚀刻气氛中在其沿第一方向(例如，X方向)设置在源/漏接触部CP之间的部分与其沿第一方向(例如，X方向)未设置在源/漏接触部CP之间的部分之间具有不同的蚀刻量。在第一蚀刻气氛中，可以以比栅封盖层125高的速率蚀刻源/漏接触部CP，并且因此，源/漏接触部CP的高度可以低于栅封盖层125的高度。因此，可以部分地暴露栅封盖层125的侧表面。由于栅封盖层125的设置在源/漏接触部CP之间的部分不仅在其上表面处暴露，而且在其侧表面处暴露，所以可以增加源/漏接触部CP的暴露面积。结果，栅封盖层125的设置在第一器件区RX1和第二器件区RX2中的部分的蚀刻量可以相对较高。此外，由于栅封盖层125的设置在场区FD中的部分仅在其上表面处暴露，并且其侧表面被具有相对低的蚀刻速率的第一层间绝缘层110覆盖，所以栅封盖层125的设置在场区FD中的部分可以具有相对小的蚀刻量。结果，通过在第一蚀刻气氛中的蚀刻工艺，栅封盖层125可以在第一器件区RX1和第二器件区RX2以及场区FD中具有不同的高度。例如，栅封盖层125可以在其设置在源/漏接触部CP之间的部分与其未设置在源/漏接触部CP之间的部分之间具有不同的高度。第一器件区RX1和第二器件区RX2中的栅封盖层125的高度Ta可以小于场区FD中的栅封盖层125的高度Tb。此外，第一器件区RX1和第二器件区RX2中的每个栅封盖层125的最上端的水平LV1可以低于场区FD中的每个栅封盖层125的最上端的水平LV2。这里，第一器件区RX1和第二器件区RX2中的栅封盖层125的高度Ta可以是第一器件区RX1和第二器件区RX2中的栅封盖层125的最大高度，并且场区FD中的栅封盖层125的高度Tb可以是场区FD中的栅封盖层125的最大高度。
在栅封盖层125中，与掩模图案MP相邻设置的栅封盖层125可以具有随着栅封盖层125朝向掩模图案MP延伸而逐渐减小的蚀刻量，同时具有随着栅封盖层125远离掩模图案MP延伸而逐渐增加的蚀刻量。因此，在掩模图案MP仅形成在两个相邻的源/漏接触部CP之一上以在第一方向(例如，X方向)上延伸的情况下，栅封盖层125可以包括在两个源/漏接触部CP之间沿第一方向(例如，X方向)具有变化的厚度的非对称封盖层。一个源/漏接触图案CA的第一部分P1可以设置在非对称封盖层的一侧处，而另一源/漏接触图案CA的第二部分P2可以设置在非对称封盖层的另一侧处。例如，栅封盖层125的厚度可以从该另一源/漏接触图案CA的第二部分P2增加到该一个源/漏接触图案CA的第一部分P1。
参考图10A和图10B，可以在图9A和图9B的所得结构上形成掩埋绝缘层150。掩埋绝缘层150可以覆盖源/漏接触图案CA，并且可以覆盖栅封盖层125和第一层间绝缘层110。此外，掩埋绝缘层150可以覆盖掩模图案MP。此后，可以在掩埋绝缘层150上形成第二上绝缘层155。例如，第二上绝缘层155可以包括氧化物。
参考图11A和图11B，可以执行化学机械抛光(CMP)工艺，由此去除第二上绝缘层155、掩模图案MP和蚀刻停止层ST。此外，化学机械抛光工艺可以去除源/漏接触图案CA的一部分和掩埋绝缘层150的一部分。可以通过CMP工艺暴露源/漏接触图案CA的第二部分P2的上表面。通过CMP工艺，掩埋绝缘层150的上表面150us可以暴露在第一器件区RX1和第二器件区RX2中，并且栅封盖层125的上表面125us和第一层间绝缘层110的上表面110us可以暴露在场区FD中。例如，至少部分栅封盖层125可以不暴露在第一器件区RX1和第二器件区RX2中。当然，当栅封盖层125包括非对称封盖层时，可以暴露非对称层的上端。
在本发明构思的示例性实施例中，可以使用栅封盖层125和/或第一层间绝缘层110作为抛光停止层来执行CMP工艺。例如，可以执行CMP工艺直到暴露栅封盖层125的上表面125us为止。当使用栅封盖层125和/或第一层间绝缘层110作为抛光停止层来执行CMP工艺时，在CMP工艺中使用的浆料相对于构成掩埋绝缘层150的绝缘材料可以比相对于分别构成栅封盖层125和第一层间绝缘层110的绝缘材料具有更大的选择性。结果，第一器件区RX1和第二器件区RX2中的掩埋绝缘层150的上表面150us的水平LV4可以与场区FD中的栅封盖层125的上表面125us和第一层间绝缘层110的上表面110us的水平LV3不同。例如，在执行CMP工艺之后所得的结构可以在第一器件区RX1和第二器件区RX2与场区FD之间具有不同的高度。例如，第一器件区RX1和第二器件区RX2中的掩埋绝缘层150的上表面150us的水平LV4可以分别低于场区FD中的栅封盖层125的上表面125us和第一层间绝缘层110的上表面110us的水平LV3。
参考图12A和图12B，可以在图11A和图11B的所得结构上形成第三上绝缘层160。第三上绝缘层160可以覆盖掩埋绝缘层150的上表面。例如，第三上绝缘层160可以包括氧化物。
此后，可以形成暴露栅电极123的一部分的栅接触孔CTH。栅接触孔CTH可以包括形成在第一器件区RX1和第二器件区RX2中的第一栅接触孔CTH1，以及形成在场区FD中的第二栅接触孔CTH2。在第一器件区RX1和第二器件区RX2中，可以形成第一栅接触孔CTH1以暴露栅电极123，同时延伸穿过第三上绝缘层160、掩埋绝缘层150和栅封盖层125。在场区FD中，可以形成第二栅接触孔CTH2以暴露栅电极123，同时延伸穿过第三上绝缘层160和栅封盖层125。
可以通过在第三上绝缘层160上形成包括第一开口和第二开口的掩模图案来形成第一栅接触孔CTH1和第二栅接触孔CTH2。掩模图案的第一开口可以暴露第三上绝缘层160的上表面的与将形成第一栅接触孔CTH1的区域相对应的部分，并且第二开口可以暴露第三上绝缘层160的与将形成第二栅接触孔CTH2的区域相对应的上表面。此外，可以通过随后使用掩模图案作为蚀刻掩模执行各向异性蚀刻工艺来形成第一栅接触孔CTH1和第二栅接触孔CTH2。可以通过各向异性蚀刻工艺同时形成第一栅接触孔CTH1和第二栅接触孔CTH2。在本发明构思的示例性实施例中，第一开口的尺寸和第二开口的尺寸可以彼此相等；然而，本发明构思不限于此。
在本发明构思的示例性实施例中，第一栅接触孔CTH1的第一最小宽度W1和第二栅接触孔CTH2的第二最小宽度W2可以彼此不同。例如，第一最小宽度W1可以大于第二最小宽度W2。当通过各向异性蚀刻工艺形成第一栅接触孔CTH1时蚀刻的栅封盖层125的高度Ta可以小于当通过各向异性蚀刻工艺形成第二栅接触孔CTH2时蚀刻的栅封盖层125的高度Tb。此外，参考衬底101的上表面，当形成第一栅接触孔CTH1时蚀刻的栅封盖层125的最上端的水平LV4可以低于当形成第二栅接触孔CTH2时蚀刻的栅封盖层125的最上端的水平LV3。因此，栅封盖层125的蚀刻开始以用于形成第一栅接触孔CTH1的水平可以与栅封盖层125的蚀刻开始以用于形成第二栅接触孔CTH2的水平不同，并且当形成第一栅接触孔CTH1时的栅封盖层125的蚀刻高度(或蚀刻量)可以与当形成第二栅接触孔CTH2时的栅封盖层125的蚀刻高度(或蚀刻量)不同。结果，第一栅接触孔CTH1和第二栅接触孔CTH2可以形成为使得在第一栅接触孔CTH1的下端处的第一最小宽度W1与在第二栅接触孔CTH2的下端处的第二最小宽度W2不同。此外，在栅封盖层125的蚀刻开始的水平之间的差和栅封盖层125的蚀刻高度之间的差可以影响随后要形成的最终结构(即，第一栅接触部(参见图14A中的“CB1”)和第二栅接触部(参见图14A中的“CB2”))的形成，使得第一栅接触部的上端的宽度和第二栅接触部的上端的宽度彼此不同。
参考图13A和图13B，可以在栅接触孔CTH中形成栅接触部CB。栅接触部CB可以包括阻挡层171和插塞层172。可以在第一栅接触孔CTH1中形成第一栅接触部CB1，并且可以在第二栅接触孔CTH2中形成第二栅接触部CB2。可以分别根据第一栅接触孔CTH1的宽度和第二栅接触孔CTH2的宽度来确定第一栅接触部CB1的宽度和第二栅接触部CB2的宽度。
参考图14A和图14B，可以通过CMP工艺暴露源/漏接触图案CA的第二部分P2的上表面。通过CMP工艺，可以去除第三上绝缘层160、掩埋绝缘层150的一部分、第一栅接触部CB1的一部分和第二栅接触部CB2的一部分，并且还可以通过CMP工艺去除栅封盖层125的一部分和第一层间绝缘层110的一部分。由于去除了掩埋绝缘层150的一部分，栅封盖层125的上表面可以暴露在第一器件区RX1和第二器件区RX2中。由于去除了第三上绝缘层160，栅封盖层125的上表面和第一层间绝缘层110的上表面可以暴露在场区FD中。在执行CMP工艺之后所得的结构可以在第一器件区RX1和第二器件区RX2与场区FD之间具有不同的高度，并且因此，栅封盖层125可以具有高度差，并且第一栅接触部CB1和第二栅接触部CB2可以具有高度差。在执行CMP工艺之后所得的结构在第一器件区RX1和第二器件区RX2与场区FD之间具有不同高度的原因是CMP工艺中使用的浆料相对于构成掩埋绝缘层150的绝缘材料的选择性与该浆料相对于构成栅封盖层125和/或第一层间绝缘层110的绝缘材料的选择性彼此不同。例如，CMP工艺可以使用栅封盖层125和/或第一层间绝缘层110作为抛光停止层。
图15A示出了根据本发明构思的示例性实施例的沿图1的线I-I'和II-II'截取的截面图。图15B示出了根据本发明构思的示例性实施例的沿图1的线III-III'和IV-IV'截取的截面图。
集成电路器件可以包括有源区105和201，并且有源区105和201可以包括鳍型有源区105和多个布线图案201。鳍型有源区105可以从衬底101突出，同时沿第一方向(例如，X方向)延伸，并且多个布线图案201可以设置为在第三方向(例如，Z方向)上与鳍型有源区105间隔开。布线图案201可以在第三方向(例如，Z方向)上彼此间隔开。可以在衬底101处形成覆盖鳍型有源区105的侧表面的元件隔离层107。
可以在鳍型有源区105上设置栅结构GS。栅结构GS可以包括栅绝缘层121、栅电极123、栅间隔物SP和栅封盖层125。栅绝缘层121可以接触布线图案201。栅电极123可以至少部分地围绕布线图案201，并且可以在栅电极123的相对侧壁上设置栅间隔物SP。可以在栅电极123上设置栅封盖层125。
栅间隔物SP可以包括内间隔物203和外间隔物205。内间隔物203可以设置在比布线图案201中的设置在最上侧处的布线图案201的水平低的水平处，并且外间隔物205可以设置在比设置在最上侧处的布线图案201的水平高的水平处。内间隔物203可以接触源/漏区S/D。在本发明构思的示例性实施例中，可以省略内间隔物203。
根据本发明构思的示例性实施例的集成电路器件可以包括源/漏接触图案CA、掩埋绝缘层150、第一栅接触部CB1、第二栅接触部CB2、第一层间绝缘层110、第二层间绝缘层170、第一过孔VA1和第二过孔VA2，并且其配置可以具有与参考图2A和图2B描述的配置相同或相似的特性。
根据本发明构思的示例性实施例，栅接触部不仅可以设置在场区中，而且可以设置在器件区中，并且因此，可以确保栅接触部和源/漏接触图案之间的绝缘距离，并减小栅接触部的电阻，同时减小所得集成电路器件的整个面积。由此，可以增加集成电路器件的可靠性。
尽管已经参考本发明构思的示例性实施例描述了本发明构思，但是本领域普通技术人员将理解的是，在不脱离本发明构思的精神和范围的情况下，可以进行形式和细节上的多种改变。

Claims (20)

1.一种集成电路器件，包括：
衬底，包括器件区和场区；
有源区，在所述器件区中沿第一方向延伸；
第一栅结构，在所述器件区和所述场区中沿与所述第一方向相交的第二方向延伸；
第二栅结构，在所述第一方向上与所述第一栅结构间隔开；
第一栅接触部，在所述器件区中设置在所述第一栅结构上；以及
第二栅接触部，在所述场区中设置在所述第二栅结构上，
其中，所述第一栅接触部和所述第二栅接触部设置在比所述第一栅结构的上端低的水平处，并且
其中，所述第一栅接触部的第一最小宽度和所述第二栅接触部的第二最小宽度彼此不同。
2.根据权利要求1所述的集成电路器件，其中，所述第一栅接触部的所述第一最小宽度大于所述第二栅接触部的所述第二最小宽度。
3.根据权利要求1所述的集成电路器件，其中，所述第一栅接触部的所述第一最小宽度小于所述第二栅接触部的所述第二最小宽度。
4.根据权利要求1所述的集成电路器件，其中，所述第一栅接触部的第一高度和所述第二栅接触部的第二高度彼此不同。
5.根据权利要求4所述的集成电路器件，其中，所述第二栅接触部的所述第二高度大于所述第一栅接触部的所述第一高度。
6.根据权利要求1所述的集成电路器件，其中，所述第一栅结构在所述器件区中具有比在所述场区中小的高度。
7.根据权利要求1所述的集成电路器件，其中：
所述第一栅结构包括栅电极和设置在所述栅电极上的栅封盖层，并且
所述栅封盖层在所述器件区中的高度小于所述栅封盖层在所述场区中的高度。
8.根据权利要求7所述的集成电路器件，其中，参考所述衬底的上表面，所述栅封盖层在所述器件区中的最上端的水平低于所述栅封盖层在所述场区中的最上端的水平。
9.根据权利要求1所述的集成电路器件，还包括：
源/漏区，在所述第一栅结构和所述第二栅结构之间设置在所述有源区上；以及
源/漏接触部，设置在所述源/漏区上，
其中，所述源/漏接触部包括第一部分和第二部分，其中，所述第一部分具有第一高度，并且所述第二部分具有大于所述第一高度的第二高度。
10.根据权利要求9所述的集成电路器件，其中，所述第二部分在所述第一方向上不与所述第一栅接触部重叠。
11.根据权利要求10所述的集成电路器件，还包括：
层间绝缘层，设置在所述第一栅结构、所述第二栅结构和所述源/漏区上；以及
掩埋绝缘层，接触所述源/漏接触部和所述层间绝缘层。
12.一种集成电路器件，包括：
衬底，包括器件区和场区；
有源区，在所述器件区中沿第一方向延伸；
第一栅电极，在所述器件区和所述场区中沿与所述第一方向相交的第二方向延伸；
第一栅封盖层，设置在所述第一栅电极上；
第二栅电极，在所述第一方向上与所述第一栅电极间隔开；
第二栅封盖层，设置在所述第二栅电极上；
第一栅接触部，与所述第一栅电极重叠，并在所述器件区中延伸穿过所述第一栅封盖层；以及
第二栅接触部，与所述第二栅电极重叠，并在所述场区中延伸穿过所述第二栅封盖层，
其中，所述第一栅接触部的第一最小宽度和所述第二栅接触部的第二最小宽度彼此不同。
13.根据权利要求12所述的集成电路器件，其中，所述第一栅接触部的所述第一最小宽度大于所述第二栅接触部的所述第二最小宽度。
14.根据权利要求12所述的集成电路器件，其中，所述第一栅接触部的所述第一最小宽度小于所述第二栅接触部的所述第二最小宽度。
15.根据权利要求12所述的集成电路器件，其中，所述第一栅接触部的第一高度和所述第二栅接触部的第二高度彼此不同。
16.根据权利要求15所述的集成电路器件，其中，所述第二栅接触部的所述第二高度大于所述第一栅接触部的所述第一高度。
17.根据权利要求12所述的集成电路器件，其中，所述有源区包括分别由所述第一栅电极和所述第二栅电极围绕并彼此间隔开的布线图案。
18.根据权利要求12所述的集成电路器件，其中：
所述器件区包括第一器件区和第二器件区，并且
所述场区设置在所述第一器件区和所述第二器件区之间。
19.一种集成电路器件，包括：
衬底，包括器件区和场区；
有源区，在所述器件区中沿第一方向延伸；
第一栅电极，在所述器件区和所述场区中沿与所述第一方向相交的第二方向延伸；
第一栅封盖层，设置在所述第一栅电极上；
第二栅电极，在所述第一方向上与所述第一栅电极间隔开；
第二栅封盖层，设置在所述第二栅电极上；
第一栅接触部，在所述器件区中连接到所述第一栅电极并穿透所述第一栅封盖层；
第二栅接触部，在所述场区中连接到所述第二栅电极并穿透所述第二栅封盖层；
源/漏区，设置在所述有源区上；以及
源/漏接触部，设置在所述源/漏区上，
其中，所述第一栅接触部的第一最小宽度大于所述第二栅接触部的第二最小宽度。
20.根据权利要求19所述的集成电路器件，其中：
所述源/漏接触部包括第一部分和第二部分，其中，所述第一部分具有第一高度，并且所述第二部分具有大于所述第一高度的第二高度，并且
所述第一栅接触部的第一高度和所述第二栅接触部的第二高度彼此不同。
CN202211566542.6A 2021-12-15 2022-12-07 包括栅接触部的集成电路器件 Pending CN116264231A (zh)

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