CN113903735A

CN113903735A - DRAM having double-layer capacitor structure, semiconductor device and method of manufacturing the same

Info

Publication number: CN113903735A
Application number: CN202010574939.4A
Authority: CN
Inventors: 崔栽荣; 贺晓彬; 李亭亭; 杨涛; 李俊峰; 王文武
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-06-22
Filing date: 2020-06-22
Publication date: 2022-01-07

Abstract

The present application relates to a memory cell structure, a memory and a semiconductor device including the memory, the memory cell including: a semiconductor substrate; a trench capacitor on the semiconductor substrate; a stacked capacitor located over the trench capacitor. The memory having the double-layer capacitor structure according to the embodiment of the present application has a small unit area (4F)²) Under the condition, the storage capacity is greatly improved.

Description

DRAM having double-layer capacitor structure, semiconductor device and method of manufacturing the same

Technical Field

The present application relates to a DRAM having a double-layer capacitor structure and a method of manufacturing the same, and also relates to a semiconductor device including the DRAM, an electronic apparatus, and a method of manufacturing the same.

Background

A typical semiconductor device includes a plurality of memory cell arrays having a plurality of unit cells for storing and outputting data according to addresses, and a plurality of sense amplifier arrays for amplifying and outputting data signals output from the cell arrays.

In order to rapidly improve the integration and scalability of the memory, the integration density of the semiconductor device is continuously increased, and the design size standard of the semiconductor device is also continuously reduced. In order to cope with the problem of improving the integration, increasing the Net Die (Net Die), improving the memory performance and reducing the manufacturing cost, there has been proposed a vertical Surrounding Gate Transistor (SGT) having a columnar semiconductor layer formed on a semiconductor substrate and a Gate (Gate) formed on a sidewall of the columnar semiconductor layer in a manner of Surrounding the columnar semiconductor layer, specifically, a Surrounding Gate Transistor memory cell as shown in fig. 1, in which a drain 11 is disposed between a word line (word, WL) and a bit line (bit, BL), a channel 12 and a Gate insulator 13 Surrounding the channel 12 are disposed in the word line WL above the drain 11; and the source 14 is disposed above the channel 12 and the gate insulator 13, while the capacitor 15 is disposed above the source 14, the upper portion of the capacitor 15 being grounded. Here, the drain 11, the gate insulator 13 and the source 14 form a transistor, and the transistor and the capacitor 15 form a memory cell 10, and the memory cell 10 is vertically formed at an intersection of the bit line BL and the word line WL.

When a DRAM (dynamic random access Memory) is formed using the SGT type Memory Cell, a Cross Point (Cross Point) type Memory Cell Array (Memory Cell Array) can be formed in the SGT because a Drain (Drain), a Gate (Gate), and a Source (Source) are arranged in a vertical direction, and thus, theoretically, 4F can be realized²Cell Size (Cell Size) of (F is the minimum distance between Fine patterns (Fine Pattern), representing the minimum critical dimension). Thus, with use of a composition having 6F²Or 8F²The cell size of the conventional Planar Transistor (DRAM) can be reduced significantly as compared with the cell size of the conventional Planar Transistor (DRAM).

The memory Cell is a 1T/1C embedded DRAM Cell (DRAM Cell) in a general sense, i.e., one T (transistor) corresponds to one C (Capacitor), and a Gate structure (Gate) and a Capacitor structure (Capacitor) are provided on a bit line BT.

Disclosure of Invention

The purpose of the application is realized by the following technical scheme:

in accordance with one or more embodiments, the present application discloses a memory cell structure comprising:

a semiconductor substrate;

a trench capacitor located within the semiconductor substrate;

a first gate word line extending in a first direction;

a bit line extending in a second direction over the first gate word line;

a second gate word line extending in the first direction over the bit line;

a stacked capacitor over the second gate word line;

the vertical active region is embedded in the substrate and is electrically connected with the trench capacitor, the first grid word line, the bit line, the second grid word line and the stacked capacitor respectively.

According to one or more embodiments, the application further discloses a memory structure, which comprises a plurality of memory modules, wherein the memory modules are composed of the memory cell structure.

In accordance with one or more embodiments, the present application also discloses a method of manufacturing a memory cell structure, comprising the process steps of:

providing a semiconductor substrate, and forming a trench capacitor in the semiconductor substrate;

forming a first gate word line over the substrate in a first direction;

forming a bit line over the first gate word line in a second direction;

forming a second gate word line along a first direction over the bit line;

forming a vertical active region at the intersection of the first gate word line, the second gate word line and the bit line;

a stacked capacitor is formed over the active region.

According to one or more embodiments, the application also discloses a semiconductor device, an electronic device and the like comprising the memory structure or the memory structure prepared by the manufacturing method.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic view of a 4F²The structure of the memory cell with the size of 1T/1C is shown schematically;

FIG. 2 is a schematic plan view of a memory cell structure having a double-layer capacitor structure according to an embodiment of the present invention;

FIG. 3 is a three-dimensional schematic diagram of a memory cell structure having a double-layer capacitor structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a memory module comprising a plurality of memory cell structures having double layer capacitor structures according to an embodiment of the present application;

fig. 5 is a schematic diagram of a connection structure between memory modules according to an embodiment of the present invention.

Detailed Description

The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" and the like include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.

Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the lower side of another element would then be turned over to be on the upper side of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary term "below" or "beneath.

Embodiments of the present application are described herein with reference to cross-sectional (and/or plan) views that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, can be expected. Thus, embodiments of the present application are not to be considered as limiting the particular shapes of regions illustrated herein, but to include deviations in shapes that result, for example, from manufacturing. For example, etched areas illustrated or described as rectangles typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood by those skilled in the art that references to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.

The application discloses a memory cell structure with a double-layer capacitor and a manufacturing method thereof. The double layer capacitors may be vertically arranged on the same vertical line, the capacitor of the lower layer may be a trench type capacitor, and the capacitor of the upper layer may be a stacked type capacitor, although the above-described capacitors are merely exemplified, the present application is not limited thereto. In one embodiment of the present invention, the detailed structure and process of the memory cell are as follows:

the embodiment of the application illustrates a semiconductor device of a memory composed of storage units with double-layer capacitors, and the semiconductor device can be used for certain electronic equipment, such as a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply and the like. As shown in fig. 2, the memory cell with a double-layer Capacitor constituting the memory may first provide a semiconductor substrate (not shown), on which a plurality of Trench capacitors 100(Trench Type capacitors), such as Pillar capacitors (pilar Type), may be disposed in the substrate of the memory cell, a plurality of stacked capacitors 200(Stack Type capacitors), such as Cylinder capacitors (Cylinder Type), may be disposed above the memory cell, and a first gate word line 300 (1)^stWord line), second gate Word line 400 (2)^ndWord Line), and a Bit Line 500(Bit Line) between two gate Word lines, a vertical type active region 600. The vertical active region 600 may be partially buried in the substrate and may be electrically connected to the trench capacitor 100, the first gate word line 300, the bit line 500, the second gate word line 400, and the stacked capacitor 200, respectively. The gate of the first gate word line 300 may be a vertical type 3D gate, the first gate word line 300 may extend along a first direction, and the vertical type 3D gate of the first gate word line 300May be orthogonal to the active region 600 at its channel so that a wrap-around gate transistor may be formed as shown in fig. 1; likewise, the gate of the second gate word line 400 may also be a vertical type 3D gate, the second gate word line 400 may also extend along the first direction, and the vertical type 3D gate of the second gate word line 400 may be orthogonal to the active region 600 at its channel, so that a surrounding gate transistor as shown in fig. 1 may also be formed. The entire semiconductor device may be partially embedded in the substrate and partially located in a dielectric layer above the substrate. In some embodiments of the present invention, the trench capacitor 100 is buried in the substrate, and the first gate word line 300, the bit line 500, the second gate word line 400 and the stacked capacitor 200 are all located on the substrate and surrounded by a dielectric layer. The structure of the first gate word line 300 and the second gate word line 400 may include a gate dielectric layer and a gate conductor layer. Wherein the gate dielectric layer may extend along the sidewalls of the active region and, in some embodiments, may also extend over the dielectric layer at a height substantially level with the bottom of each word line. The gate conductor layer extends on the side wall and the bottom wall of the corresponding gate dielectric layer. Of course, the vertical 3D gate is not limited to the above structure, and may be any other suitable structure; in the present embodiment, the first and second gate word lines 400 share the active region 600 for cost saving and process convenience. The trench capacitor 100 may be electrically connected to the active region 600 through a first Landing pad (not shown), and the stacked capacitor 200 may be electrically connected to the active region 600 through a second Landing pad (not shown). The middle portion of the active region 600 is electrically connected to cross vertically through the center of the bit line 500. The first gate word line 300 and the second gate word line 400 may be parallel lines extending in the first direction, which are located on the same plane (i.e., the direction of the paper shown in fig. 2), and the bit line 500 extending in the second direction may exactly intersect the plane perpendicularly (i.e., the bit line 500 is perpendicular to the direction of the paper shown in fig. 2, and the first direction is perpendicular to the second direction), and the intersection point of the bit line 500 with the plane may exactly be the same distance from the first gate word line 300 and the second gate word line 400. With the above arrangement, the trench capacitor 100, the active region 600, the first gate word line 300 and the second gate word line 300The vertical type 3D gate of the gate word line 400 and the stacked capacitor 200 may be substantially located on the same line, which is located in the above-mentioned plane and is orthogonal to the first gate word line 300 at the vertical type 3D gate thereof and the second gate word line 400 at the vertical type 3D gate thereof. In the present embodiment, the trench capacitor 100 and the stacked capacitor 200 may have the same storage capacity, and may be designed to have the same storage capacity based on different structures. In addition, the memory may further include a first metal connection 700 and a second metal connection 800, the first metal connection 700 connects the first gate word line 300 with a metal wiring layer (not shown), and the second metal connection 800 connects the second gate word line 400 with a metal wiring layer (not shown), and the first metal connection 700 and the second metal connection 800 may be separately controlled by the metal wiring layer.

As shown in fig. 4 to 5, the present application further provides a memory composed of the above memory cells, and specifically, the memory may have a plurality of memory blocks (Cell blocks), where each memory Block may be composed of a plurality of the above memory Cell structures. In the memory, the first word lines between adjacent memory blocks are arranged in the same region of the same word line driving region (SWD), and the second word lines between adjacent memory blocks are also arranged in the same region of the same word line driving region. The word line driving region includes word lines and Peripheral gates (Peripheral gates) corresponding to the word lines, and a group shared Source (Source) including the word lines and the Peripheral gates corresponding to the word lines arranged between adjacent memory modules. Meanwhile, adjacent bit lines of a plurality of memory cells of one memory module are respectively arranged in Sense amplifier regions (Sense Amplifiers) at opposite ends, and an odd number of bit lines are arranged at one end and an even number of bit lines are arranged at the other end of the Sense Amplifiers at opposite ends. The distance between the bit lines and between the storage modules, the distance between the first word line and the distance between the first word line and the first word line are the same, the length between the bit lines and between the storage modules, the length between the first word line and the length between the second word line and the second word line are the same, and the word lines and the bit lines form an orderly array with the same size.

Next, a process of manufacturing the memory according to an embodiment of the present application is described in further detail:

first, a semiconductor substrate may be provided and ion implantation may be performed in a region of the substrate corresponding to a location of the memory cell. Subsequently, a Trench Type capacitor 100(Trench Type), which may be a common Trench Type Pillar capacitor (pilar Type), for example, may be formed within the semiconductor substrate. Subsequently, a first landing pad mold layer may be formed over the semiconductor substrate, and a first landing pad (not shown) may be formed in a position corresponding to the trench capacitor 100 within the first landing pad mold layer. Subsequently, a dielectric material can be deposited above the first landing pad mold layer to form a dielectric layer, the position where the active region is to be formed is reserved, and the dielectric layer is etched back to the height where the word line is to be formed. A first word line material layer may then be formed on the dielectric layer, and then the first word line material layer may be etched along a first direction at a position corresponding to the trench type capacitor 100 to form a first gate word line 300 extending along the first direction, wherein the gate may be a vertical type 3D gate-all-around structure. The word line material layer may include a gate dielectric material layer and a gate conductor material layer, the gate dielectric material layer may extend along the sidewall of the active region and the top surface of the etched-back dielectric layer, and the gate conductor material layer may also extend along the sidewall and the bottom wall of the gate dielectric layer, and then the gate dielectric material layer and the gate conductor material layer may be etched by photolithography or other methods to form the first gate word line 300. A dielectric layer may then be formed over the first gate word line 300; subsequently, a bit line material layer may be formed over the dielectric layer on the first gate word line, and then the bit line material layer may be etched along a second direction perpendicular to the first direction at a corresponding position of the trench capacitor 100 to form a formed bit line 500 extending along the second direction, and then a dielectric material may be deposited again for node separation and a dielectric layer may be formed over the bit line 500. Subsequently, a second word line material layer may be formed over the dielectric layer on the bit line 500, and then the second word line material layer may be etched along the first direction at a position corresponding to the trench type capacitor 100 to form a second gate word line 400 extending along the first direction, wherein the gate may be a vertical type 3D gate-all-around structure. The forming method of the second gate word line 400 can refer to the forming method of the first gate word line 300, and is not described herein again. A dielectric layer may then be formed over the first gate word line 400; the projections of the first gate word line 300, the second gate word line 400 and the bit line 500 on the horizontal plane may intersect at the same point, the point may correspond to the position of the trench capacitor 100, and the gates of the first gate word line and the second gate word line are located at the intersection; subsequently, the dielectric layer on the second gate word line may be etched vertically downward at a position corresponding to the intersection of the first gate word line 300, the second gate word line 400 and the bit line 500 to form a through active region 600, so that the first gate word line 300, the second gate word line 400 and the bit line 500 may share the active region 600, thereby saving the process; subsequently, a second landing pad mold layer may be formed over the active region 600, and a second landing pad (not shown) may be formed in a position corresponding to the active region 600 within the second landing pad mold layer; subsequently, a stacked capacitor 200(Stack Type) may be formed over the second landing pad, and the stacked capacitor 200 structure may employ, for example, a common stacked cylindrical capacitor (Cylinder Type) manufacturing method; after the stacked capacitor 200 is formed, the first word line 300 may be electrically connected to the metal wiring layer through the first metal contact 700, and the second word line 400 may be electrically connected to the metal wiring layer through the second metal contact 800, thereby achieving communication of the memory cell with the outside.

The heat removal structure of the memory cell in the embodiment of the present application maintains the same structure as the existing structure, the design is easy, and the 4F of the memory cell²The word lines and bit lines of the structure are also designed to be right-angled structures, and the SWD/SA design structure in the existing memory can be directly utilized without bit change.

The memory with the double-layer capacitor structure in the embodiment of the application has a smaller unit size area(4F²) Under the condition, the storage capacity is greatly improved, the manufacturing process is simple, and the cost is reduced.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A memory cell structure comprising:

a semiconductor substrate;

a trench capacitor located within the semiconductor substrate;

a first gate word line extending in a first direction;

a bit line extending in a second direction over the first gate word line;

a second gate word line extending in the first direction over the bit line;

a stacked capacitor over the second gate word line;

and the vertical active region of the partially-buried substrate is electrically connected with the trench capacitor, the first grid word line, the bit line, the second grid word line and the stacked capacitor respectively.

2. The memory cell structure of claim 1, wherein:

the active region is orthogonal to the first gate word line at the central position of the first gate word line, and/or the active region is orthogonal to the second gate word line at the central position of the second gate word line.

3. The memory cell structure of claim 1, wherein:

the active region is orthogonal to the bit line at a central position of the bit line.

4. A memory cell structure according to any one of claims 1 to 3, wherein:

the grid of the first grid word line and/or the second grid word line is of a vertical 3D grid structure.

5. A memory cell structure according to any one of claims 1 to 3, wherein:

the trench capacitor and the stacked capacitor have the same storage capacity.

6. The memory cell structure of claim 5, wherein: the trench capacitor is a cylindrical capacitor, and the stacked capacitor is a cylindrical capacitor.

7. A memory cell structure according to any one of claims 1 to 3, wherein:

the first grid word line is electrically connected with the first metal connecting part;

the second gate word line is electrically connected to the second metal connection portion.

8. A memory structure comprising a plurality of memory modules, said memory modules being comprised of a plurality of memory cell structures as claimed in any one of claims 1 to 6.

9. The memory structure of claim 8, wherein:

the first grid word lines between the adjacent memory modules are arranged in the same area of the same word line driving area; the second gate word lines between the adjacent memory modules are arranged in the same region of the same word line driving region.

10. The memory structure of claim 9, wherein:

the word line drive region includes the configured word line and peripheral gate, which share a source.

11. The memory structure of claim 9, wherein:

adjacent bit lines of a plurality of memory cells of the memory module are respectively configured in the sense amplifier regions at two opposite ends, and one end of the sense amplifiers at the two opposite ends is configured with odd number of the bit lines, and the other end is configured with even number of the bit lines.

12. The memory structure of claim 9, wherein:

the distance between bit lines among the memory modules, the distance between a first grid word line and the distance between a second grid word line and a second grid word line are the same;

the lengths of bit lines and bit lines between the memory modules, the lengths of the first grid word lines and the first grid word lines, and the lengths of the second grid word lines and the second grid word lines are the same.

13. The memory structure of claim 8, wherein:

the first metal connection and the second metal connection are separately controlled on a metal wiring layer.

14. A method for manufacturing a memory cell structure comprises the following process steps:

forming a first gate word line over the substrate in a first direction;

forming a bit line over the first gate word line in a second direction;

forming a second gate word line along a first direction over the bit line;

a stacked capacitor is formed over the active region.

15. The manufacturing method according to claim 14, comprising the following process steps:

the forming of the first grid word line is that after a dielectric layer is deposited above the substrate, a first word line material layer is deposited, then the first word line material layer is etched along a first direction to form a first grid word line along the first direction, and then the dielectric layer is deposited;

forming a bit line material layer on the dielectric layer above the first gate word line, etching the bit line material layer along a second direction to form a bit line along the second direction, and depositing the dielectric layer;

forming a second word line material layer on the dielectric layer above the bit line, then etching the second word line material layer along a first direction to form a second gate word line along the first direction, and then depositing the dielectric layer;

and forming a vertical active region by forming a vertical groove at the intersection of the first gate word line, the second gate word line and the bit line and filling the groove with the active region.

16. The manufacturing method according to claim 14, comprising the following process steps:

before forming the first gate word line, forming a first landing pad so that the active region is electrically connected to the trench capacitor through the landing pad.

17. The manufacturing method according to claim 14, comprising the following process steps:

before forming the stacked capacitor, forming a second landing pad so that the active region is electrically connected to the stacked capacitor through the second landing pad.

18. Manufacturing method according to any of claims 14-17, comprising the following process steps:

and before the groove type capacitor is formed, ion implantation is carried out on the substrate area at the corresponding position of the memory cell.

19. Manufacturing method according to any of claims 14-17, comprising the following process steps:

after the forming of the stacked capacitor, the method further includes electrically connecting the memory cell with a metal wiring layer through a metal contact.

20. A semiconductor device comprising a memory structure as claimed in any one of claims 8 to 13.

21. An electronic device comprising the semiconductor device according to claim 20.

22. The electronic device of claim 21, the electronic device having a DRAM.

23. The electronic device of claim 21 or 22, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.