CN111900165A - Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment - Google Patents
Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment Download PDFInfo
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- CN111900165A CN111900165A CN202010575080.9A CN202010575080A CN111900165A CN 111900165 A CN111900165 A CN 111900165A CN 202010575080 A CN202010575080 A CN 202010575080A CN 111900165 A CN111900165 A CN 111900165A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 238000000465 moulding Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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Abstract
The disclosure provides a semiconductor structure, a manufacturing method thereof, a semiconductor memory and an electronic device. The semiconductor structure of the present disclosure includes: a substrate; a plurality of lower electrodes disposed on the substrate and arranged at intervals in a first direction and a second direction perpendicular to the first direction; a first support pattern supporting the plurality of lower electrodes, having a plurality of oval open areas, each of the open areas connecting a predetermined number of the lower electrodes and exposing a portion of a sidewall of each of the connected lower electrodes. The support pattern of the semiconductor structure adopts the oval open area, so that the open proportion of the lower electrode can be improved, and sufficient process margin is provided for the formation of a subsequent dielectric film and an upper electrode, so as to improve the reliability of a semiconductor capacitor, and further improve the refresh characteristic of a semiconductor memory.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a semiconductor memory, and an electronic device.
Background
Dynamic Random Access Memory (DRAM) is a type of semiconductor Memory that generally includes an array of Memory cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing charge (i.e., a bit of information) and a transistor that provides an access signal to the capacitor during read and write operations. The transistor is connected between the bit line and the capacitor, and is gated (turned on or off) by a word line signal. During a read operation, a bit of stored information is read from the cell via the associated bit line. During a write operation, a bit of information is stored in the cell from the bit line via the transistor. The cells are dynamic in nature (due to leakage) and must therefore be refreshed periodically.
The capacitor includes an upper electrode, a lower electrode, and a dielectric between the upper electrode and the lower electrode, and a support for supporting the lower electrode is included in the capacitor because a high aspect ratio of the lower electrode in the capacitor may cause the lower electrode to collapse or break before the dielectric film is formed.
The characteristics of the capacitor are important factors in determining the refresh characteristics of the DRAM, and as the semiconductor devices are increasingly miniaturized, the process difficulty is also increased, and the distribution of the support structures is an important factor affecting the characteristics of the capacitor.
Disclosure of Invention
The purpose of the present disclosure is to provide a semiconductor structure, a method for manufacturing the semiconductor structure, a semiconductor memory and an electronic device.
A first aspect of the present disclosure provides a semiconductor structure comprising:
a substrate;
a plurality of lower electrodes disposed on the substrate and arranged at intervals in a first direction and a second direction perpendicular to the first direction;
a first support pattern supporting the plurality of lower electrodes, having a plurality of oval open areas, each of the open areas connecting a predetermined number of the lower electrodes and exposing a portion of a sidewall of each of the connected lower electrodes.
A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including:
providing a semiconductor substrate;
sequentially forming a molding layer and a support-forming layer on the semiconductor substrate;
forming a plurality of holes exposing the semiconductor substrate by etching the molding layer and the support forming layer;
forming a plurality of lower electrodes by coating a conductive material onto inner walls of the plurality of holes; and the number of the first and second groups,
the support formation layer is etched using a photolithography process to form a plurality of oval-shaped open areas and to form a first support pattern connecting the plurality of lower electrodes.
A third aspect of the present disclosure provides a semiconductor memory comprising:
the semiconductor structure as described in the first aspect.
A fourth aspect of the present disclosure provides an electronic device, comprising:
the semiconductor memory as described in the third aspect.
This disclosure compares advantage with prior art and lies in:
the support pattern of the semiconductor structure provided by the present disclosure adopts the oval opening region, which can improve the opening ratio of the lower electrode, and provide sufficient process margin for the formation of the subsequent dielectric film and the upper electrode, so as to improve the reliability of the semiconductor capacitor, thereby improving the refresh characteristics of the semiconductor memory.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a top view of a semiconductor structure provided by the present disclosure;
FIG. 2 illustrates a cross-sectional view of the semiconductor structure along line a of FIG. 1;
fig. 3 shows a flow chart of a method for fabricating a semiconductor structure provided by the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a semiconductor memory and an electronic device, which are described below with reference to the accompanying drawings.
Fig. 1 illustrates a top view of a semiconductor structure provided by the present disclosure. Fig. 2 shows a cross-sectional view of the semiconductor structure along line a in fig. 1. As shown in fig. 1 and 2, the semiconductor structure 10 may include: a substrate 100, a lower electrode 200, and a first supporter pattern 300.
Wherein a plurality of lower electrodes 200 are disposed on the substrate 100 and spaced apart in a first direction (e.g., x-direction) and a second direction (e.g., y-direction) perpendicular to the first direction, and the first supporter patterns 300 are integrally connected to have a plurality of open regions 310 having an elliptical shape. The plurality of open regions 310 connect and support the plurality of lower electrodes 200 and open a portion of each of the plurality of lower electrodes 200. Specifically, each of the open regions 310 connects a predetermined number of the lower electrodes 200 and exposes a portion of the sidewall of each of the connected lower electrodes, and the predetermined number may be 4 as shown in fig. 1. (for convenience of explanation, the dielectric film and the upper electrode are omitted in the figure)
The plurality of lower electrodes 200 may form a plurality of rows and columns in the first direction and the second direction. In order to secure the space between the plurality of lower electrodes 200, the lower electrodes 200 in adjacent rows are disposed in a staggered manner, i.e., the plurality of lower electrodes 200 may be disposed in a honeycomb structure. And the plurality of open areas 310 may be arranged to: the two adjacent open areas in the first direction are oriented differently, and preferably, the included angle between the major axes of the two adjacent elliptical open areas in the first direction is 90 degrees. Two adjacent open areas in the second direction are oriented in the same direction, that is, parallel to the major axes of two adjacent elliptical open areas in the second direction, as shown in fig. 1. Each of the open regions 310 may expose a portion of the sidewall of each of the 4 lower electrodes 200. By the arrangement of the lower electrode 200 and the open region 310 described above, the purpose of exposing a larger proportion of the lower electrode 200 can be achieved.
According to an embodiment of the present disclosure, the semiconductor structure 10 may further include a second support pattern 400 (not shown), the second support pattern 400 being located between the substrate 100 and the first support pattern 300 and also used to support the plurality of lower electrodes 200 to further keep the stability of the lower electrodes 200, and the second support pattern 400 having the same pattern as the first support pattern 300, and the aspect ratio of the lower electrodes 200 may be very large by the arrangement of the second support pattern 400. The first support pattern 300 may be formed on a sidewall of upper ends of the plurality of lower electrodes 200, the second support pattern 400 may be formed on a sidewall of a middle portion of the plurality of lower electrodes 200, and the first support pattern 300 may expose upper surfaces of the plurality of lower electrodes 200.
In one embodiment according to the present disclosure, as shown in fig. 1, the substrate 100 may include two regions: the semiconductor device includes a first electrode region 110 and a second electrode region 120 surrounding the first electrode region 110, a plurality of lower electrodes 200 are disposed in the first electrode region 110, and a plurality of dummy lower electrodes 210 are disposed in the second electrode region 120, thereby preventing the plurality of lower electrodes 200 from collapsing and improving the defective distribution of a plurality of open regions 310, and even if a certain number of dummy lower electrodes 210 are used in the open regions 310, the characteristics of the semiconductor structure are not affected.
A plurality of capacitors including a plurality of lower electrodes 200 may be formed in the first electrode region 110. It is understood that the semiconductor structure 10 may further include: a capacitor dielectric film (not shown) disposed on the lower electrode 200, and an upper electrode (not shown) disposed on the capacitor dielectric film.
It is worth mentioning that as the ratio of the opened lower electrode 200 becomes higher, the subsequent processes such as the dielectric film formation process and the like can be performed in a smoother and more uniform manner, and vice versa with difficulty. That is, if there are many lower electrodes 200 that are not opened, the formation of the dielectric film or the like on the lower electrodes 200 may be incomplete and uneven, resulting in deterioration of the characteristics of the semiconductor structure 10. The open ratio of the existing support pattern to the lower electrode is about 87%, whereas the open ratio to the lower electrode can reach 98% with the support pattern proposed by the present disclosure.
The support pattern of the semiconductor structure provided by the present disclosure adopts the oval opening region, which can improve the opening ratio of the lower electrode, and provide sufficient process margin for the formation of the subsequent dielectric film and the upper electrode, so as to improve the reliability of the semiconductor capacitor, thereby improving the refresh characteristics of the semiconductor memory.
The present disclosure also provides a method for manufacturing a semiconductor structure, which is used for manufacturing the semiconductor structure in the above embodiments. Fig. 3 shows a flow chart of a method for fabricating a semiconductor structure provided by the present disclosure, the method comprising the steps of:
step S101: providing a semiconductor substrate;
step S102: sequentially forming a molding layer and a support-forming layer on the semiconductor substrate;
step S103: forming a plurality of holes exposing the semiconductor substrate by etching the molding layer and the support forming layer;
step S104: forming a plurality of lower electrodes by coating a conductive material onto inner walls of the plurality of holes;
step S105: the support formation layer is etched using a photolithography process to form a plurality of oval-shaped open areas and to form a first support pattern connecting the plurality of lower electrodes.
Referring to fig. 1 and 2, a substrate 100 is provided, a molding layer (not shown) and a support formation layer are sequentially formed on the substrate 100, a plurality of holes exposing the substrate 100 are formed by etching the molding layer and the support formation layer, a plurality of lower electrodes 200 are formed by coating a conductive material on inner walls of the plurality of holes, and the support formation layer is etched by using a photolithography process to form a plurality of oval-shaped open regions 310 and form first support patterns 300 connecting the plurality of lower electrodes 200, which may be prepared by using a conventional related process, and detailed processes thereof are not described herein.
As shown in fig. 1, each open region 310 connects 4 lower electrodes 200 and exposes a portion of the sidewall of each of the connected lower electrodes 200.
In the above method, the two adjacent open regions 310 in the first direction have different orientations, and the two adjacent open regions 310 in the second direction have the same orientation, as shown in fig. 1.
In one embodiment of the present disclosure, the method further includes forming a second support pattern 400 (not shown), the second support pattern 400 being formed between the substrate 100 and the first support pattern 300 to support the plurality of lower electrodes 200, having the same pattern as the first support pattern 300.
In one embodiment according to the present disclosure, the substrate 100 includes a first electrode region 110 and a second electrode region 120 surrounding the first electrode region 110. A plurality of lower electrodes 200 are disposed in the first electrode region 110.
According to an embodiment of the present disclosure, the method further includes: a plurality of dummy lower electrodes 210 are formed in the second electrode region 120.
According to an embodiment of the present disclosure, the method further includes: a capacitor dielectric film is formed on the lower electrode 200, and an upper electrode is formed on the capacitor dielectric film.
Compared with the prior art, the semiconductor structure manufactured by the method has the advantages that the support pattern adopts the oval open area, so that the open proportion of the lower electrode can be increased, and sufficient process margin is provided for the formation of the subsequent dielectric film and the upper electrode, so that the reliability of the semiconductor capacitor is improved, and the refresh characteristic of the semiconductor memory is improved.
The embodiment of the present disclosure also provides a semiconductor memory, which includes the semiconductor structure described in the above embodiment, and the semiconductor memory may be, for example, a memory such as a DRAM.
As shown in fig. 1 and 2, the semiconductor structure 10 may include: a substrate 100, a lower electrode 200, and a first supporter pattern 300.
Wherein a plurality of lower electrodes 200 are disposed on the substrate 100 and spaced apart in a first direction (e.g., x-direction) and a second direction (e.g., y-direction) perpendicular to the first direction, and the first supporter patterns 300 are integrally connected to have a plurality of open regions 310 having an elliptical shape. The plurality of open regions 310 connect and support the plurality of lower electrodes 200 and open a portion of each of the plurality of lower electrodes 200. Specifically, each of the open regions 310 connects a predetermined number of the lower electrodes 200 and exposes a portion of the sidewall of each of the connected lower electrodes, and the predetermined number may be 4 as shown in fig. 1. (for convenience of explanation, the dielectric film and the upper electrode are omitted in the figure)
The plurality of lower electrodes 200 may form a plurality of rows and columns in the first direction and the second direction. In order to secure the space between the plurality of lower electrodes 200, the lower electrodes 200 in adjacent rows are disposed in a staggered manner, i.e., the plurality of lower electrodes 200 may be disposed in a honeycomb structure. And the plurality of open areas 310 may be arranged to: the two adjacent open areas in the first direction are oriented differently and the two adjacent open areas in the second direction are oriented identically, as shown in fig. 1. Each of the open regions 310 may expose a portion of the sidewall of each of the 4 lower electrodes 200. By the arrangement of the lower electrode 200 and the open region 310 described above, the purpose of exposing a larger proportion of the lower electrode 200 can be achieved.
According to an embodiment of the present disclosure, the semiconductor structure 10 may further include a second support pattern 400 (not shown), the second support pattern 400 being located between the substrate 100 and the first support pattern 300 and also used to support the plurality of lower electrodes 200 to further keep the stability of the lower electrodes 200, and the second support pattern 400 having the same pattern as the first support pattern 300, and the aspect ratio of the lower electrodes 200 may be very large by the arrangement of the second support pattern 400. The first support pattern 300 may be formed on a sidewall of upper ends of the plurality of lower electrodes 200, the second support pattern 400 may be formed on a sidewall of a middle portion of the plurality of lower electrodes 200, and the first support pattern 300 may expose upper surfaces of the plurality of lower electrodes 200.
In one embodiment according to the present disclosure, as shown in fig. 1, the substrate 100 may include two regions: the semiconductor device includes a first electrode region 110 and a second electrode region 120 surrounding the first electrode region 110, a plurality of lower electrodes 200 are disposed in the first electrode region 110, and a plurality of dummy lower electrodes 210 are disposed in the second electrode region 120, thereby preventing the plurality of lower electrodes 200 from collapsing and improving the defective distribution of a plurality of open regions 310, and even if a certain number of dummy lower electrodes 210 are used in the open regions 310, the characteristics of the semiconductor structure are not affected.
A plurality of capacitors including a plurality of lower electrodes 200 may be formed in the first electrode region 110. It is understood that the semiconductor structure 10 may further include: a capacitor dielectric film (not shown) disposed on the lower electrode 200, and an upper electrode (not shown) disposed on the capacitor dielectric film.
It is worth mentioning that as the ratio of the opened lower electrode 200 becomes higher, the subsequent processes such as the dielectric film formation process and the like can be performed in a smoother and more uniform manner, and vice versa with difficulty. That is, if there are many lower electrodes 200 that are not opened, the formation of the dielectric film or the like on the lower electrodes 200 may be incomplete and uneven, resulting in deterioration of the characteristics of the semiconductor structure 10.
The embodiment of the present disclosure also provides an electronic device, which includes the semiconductor memory in the above embodiment. The electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, or a mobile power source.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (12)
1. A semiconductor structure, comprising:
a substrate;
a plurality of lower electrodes disposed on the substrate and arranged at intervals in a first direction and a second direction perpendicular to the first direction;
a first support pattern supporting the plurality of lower electrodes, having a plurality of oval open areas, each of the open areas connecting a predetermined number of the lower electrodes and exposing a portion of a sidewall of each of the connected lower electrodes.
2. The semiconductor structure of claim 1, wherein two adjacent open regions in the first direction are oriented differently and two adjacent open regions in the second direction are oriented identically.
3. The semiconductor structure of claim 2, further comprising:
a second support pattern between the substrate and the first support pattern, supporting the plurality of lower electrodes, and having the same pattern as the first support pattern.
4. The semiconductor structure of claim 1, wherein the substrate comprises a first electrode region and a second electrode region surrounding the first electrode region; the plurality of lower electrodes are disposed within the first electrode region.
5. The semiconductor structure of claim 4, further comprising:
and a plurality of dummy lower electrodes disposed in the second electrode regions.
6. The semiconductor structure of claim 1, further comprising:
a capacitor dielectric film disposed on the lower electrode; and the number of the first and second groups,
an upper electrode disposed on the capacitor dielectric film.
7. The semiconductor structure of any of claims 1 to 6, wherein the predetermined number is 4.
8. The semiconductor structure of claim 2, wherein the major axes of two adjacent elliptical open areas in the first direction are oriented at an angle of 90 degrees.
9. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
sequentially forming a molding layer and a support-forming layer on the substrate;
forming a plurality of holes exposing the substrate by etching the molding layer and the support-forming layer;
forming a plurality of lower electrodes by coating a conductive material onto inner walls of the plurality of holes; and the number of the first and second groups,
the support formation layer is etched using a photolithography process to form a plurality of oval-shaped open areas and to form a first support pattern connecting the plurality of lower electrodes.
10. A semiconductor memory, comprising:
a semiconductor structure as in any of claims 1-8.
11. An electronic device, comprising:
the semiconductor memory according to claim 10.
12. The electronic device of claim 11, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010575080.9A CN111900165A (en) | 2020-06-22 | 2020-06-22 | Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010575080.9A CN111900165A (en) | 2020-06-22 | 2020-06-22 | Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment |
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| US20150041973A1 (en) * | 2013-08-12 | 2015-02-12 | Samsung Electronics Co., Ltd. | Semiconductor devices including unitary supports |
| US20180026040A1 (en) * | 2016-07-25 | 2018-01-25 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
| US20180158829A1 (en) * | 2016-12-02 | 2018-06-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including support patterns |
| CN108183097A (en) * | 2016-12-08 | 2018-06-19 | 三星电子株式会社 | Semiconductor devices |
| CN108231775A (en) * | 2016-12-14 | 2018-06-29 | 三星电子株式会社 | Semiconductor devices |
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2020
- 2020-06-22 CN CN202010575080.9A patent/CN111900165A/en active Pending
Patent Citations (7)
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|---|---|---|---|---|
| US20120235279A1 (en) * | 2011-03-14 | 2012-09-20 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating the same |
| CN103151244A (en) * | 2011-12-07 | 2013-06-12 | 华邦电子股份有限公司 | Stackable capacitor and manufacturing method thereof |
| US20150041973A1 (en) * | 2013-08-12 | 2015-02-12 | Samsung Electronics Co., Ltd. | Semiconductor devices including unitary supports |
| US20180026040A1 (en) * | 2016-07-25 | 2018-01-25 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
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