CN114824078A - Semiconductor structure and manufacturing method thereof and DRAM - Google Patents
Semiconductor structure and manufacturing method thereof and DRAM Download PDFInfo
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- CN114824078A CN114824078A CN202110113945.4A CN202110113945A CN114824078A CN 114824078 A CN114824078 A CN 114824078A CN 202110113945 A CN202110113945 A CN 202110113945A CN 114824078 A CN114824078 A CN 114824078A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
The invention provides a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random access memory), which relate to the technical field of semiconductors and comprise a semiconductor substrate; a plurality of lower electrodes formed on at least a partial region of the semiconductor substrate; the lower electrodes are distributed into a multi-row structure, and the lower electrodes in adjacent rows are arranged in a staggered manner; the support piece comprises a plurality of support openings, each support opening passes through a plurality of adjacent lower electrodes capable of enclosing into a hexagonal prism shape, and the adjacent lower electrodes enclosing into the hexagonal prism shape belong to three adjacent rows. In the above-mentioned technical solution, by simultaneously connecting a single support opening to a larger number of adjacent lower electrodes, the support opening needs to have a considerable area, and even if the entire semiconductor structure is subjected to the downsizing process, the lower electrodes and the corresponding support openings are both correspondingly downsized, so that the number of the lower electrodes connected to the single support opening is maintained at a larger level.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random Access memory).
Background
The bottom electrode is generally used in an integrated circuit, and the lateral dimension of the bottom electrode is reduced, so that valuable semiconductor substrate area is saved. In order to ensure the falling of the lower electrode, a supporting layer is generally used to support the lower electrode and maintain the stability of the lower electrode. However, as the size of the lower electrode is reduced, the distance between adjacent support openings in the support layer is also gradually reduced, and the reduction of the distance between the support openings increases the difficulty of the photolithography process and increases the manufacturing cost.
Disclosure of Invention
The invention aims to provide a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random access memory), so as to solve the technical problem that the photoetching process difficulty is increased due to the reduction of the spacing of supporting openings in the prior art.
The invention provides a semiconductor structure, comprising:
a semiconductor substrate;
a plurality of lower electrodes formed on at least a partial region of the semiconductor substrate; the lower electrodes are distributed into a multi-row structure, and the lower electrodes in adjacent rows are arranged in a staggered manner;
the support piece comprises a plurality of support openings, each support opening passes through a plurality of adjacent lower electrodes capable of forming a hexagonal prism shape, and the adjacent lower electrodes forming the hexagonal prism shape belong to three adjacent rows.
The invention also provides a DRAM, which comprises the semiconductor structure; the number of the semiconductor structures is multiple, and the semiconductor structures are uniformly distributed; the semiconductor substrate also comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line, and the other active region is electrically connected to the landing pad.
The invention also provides a manufacturing method of the electronic structure, which comprises the following steps:
providing a semiconductor substrate;
forming a stacked structure comprising at least one mold oxide layer and support members alternating on the semiconductor substrate;
etching the laminated structure to form a contact hole;
forming a lower electrode in the contact hole;
and patterning the at least one supporting layer to form a supporting part, wherein the supporting part is provided with a plurality of supporting openings, each supporting opening passes through a plurality of adjacent lower electrodes capable of forming a hexagonal shape, and the adjacent lower electrodes forming the hexagonal shape belong to three adjacent rows.
In the above technical solution, by simultaneously connecting a single support opening to a larger number of adjacent lower electrodes, the support opening needs to have a considerable area, which is equivalent to enlarging the area of the single support opening. Therefore, even if the entire semiconductor structure is subjected to the miniaturization process, the lower electrodes and the corresponding support openings are correspondingly shrunk, so that the number of the lower electrodes connected with a single support opening is maintained at a higher level, the support opening can still be formed in a single photoetching mode, the difficulty of the support opening forming process cannot be improved, and the manufacturing cost is further ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in accordance with one embodiment of the present invention;
fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor structure according to an embodiment of the invention.
Reference numerals:
1. a lower electrode; 2. a support layer; 3. a semiconductor substrate;
21. supporting the opening.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The present invention will be described in detail below with embodiments of the present invention applied to capacitors in DRAM products.
As shown in fig. 1 to fig. 2, the present embodiment provides a capacitor, including:
a semiconductor substrate 3;
a plurality of lower electrodes 1, the lower electrodes 1 being formed on at least a partial region of the semiconductor substrate 3; the lower electrodes 1 are distributed in a multi-row structure, and the lower electrodes 1 in adjacent rows are arranged in a staggered manner;
at least one layer of supporting pieces 2, the supporting pieces 2 comprise a plurality of supporting openings 21, each supporting opening 21 passes through a plurality of adjacent lower electrodes 1 capable of enclosing into a hexagonal shape, and the adjacent lower electrodes 1 enclosing into the hexagonal shape belong to three adjacent rows.
Referring to fig. 1, the lower electrodes 11 of the capacitor are supported by the support openings 21, so that the lower electrodes 11 can be kept stable even in a high aspect ratio structure, and the problems of inclination and collapse are avoided. After the support layer 2 is patterned, the patterned support openings 21 may be uniformly distributed, and then, in the area where the support openings 21 are distributed, each support opening 21 needs to be connected with a plurality of lower electrodes 1 at the same time. While the specific shape of the supporting openings 21 can be set by those skilled in the art according to the requirement, for example, the shapes of the supporting openings 21 can be all the same, that is, all the lower electrodes 1 can be connected in the same way, as long as the lower electrodes 1 passed by the adjacent supporting openings 21 can be connected in the arrangement of the lower electrodes 1.
Besides, the shapes of the support openings 21 may also be partially the same, that is, the support openings 21 may be in various shapes, so that the support openings 21 in each different shape may connect all the lower electrodes 1 in the same manner, as long as the lower electrodes 1 through which the adjacent support openings 21 pass can be connected in the arrangement of the lower electrodes 1.
It can be seen that, compared to the connection method between the support openings 21 and the lower electrodes 1 in the prior art, in this method, by simultaneously connecting a single support opening 21 to a larger number of adjacent lower electrodes 1, for example, each support opening 21 is connected between more than 6 lower electrodes 1 in adjacent three rows, it is necessary to have a considerable area of the support opening 21, which is equivalent to enlarging the area of the single support opening 21. Therefore, even if the entire capacitor is subjected to the downsizing process, the lower electrodes 1 and the corresponding support openings 21 are both correspondingly downsized, so that the number of the lower electrodes 1 connected to a single support opening 21 is maintained at a relatively large level, and the support opening 21 can still be formed by a single photolithography method, thereby not increasing the difficulty of the formation process of the support opening 21, and further ensuring the manufacturing cost.
That is, for example, in the prior art, only 3 to 4 lower electrodes 1 are connected to a single support opening 21, or a single support opening 21 covers only two rows of lower electrodes 1 in the width direction although the number of the connected lower electrodes 1 is large, so that the area of the conventional support opening 21 is small or the width is narrow, and when the capacitor is subjected to the downsizing process, the area of the support opening 21 is also small, and thus the difficulty of the formation process of the support opening 21 is increased. The lower electrodes 1 connected to the single support opening 21 are expanded to 6 or more and simultaneously cover three adjacent rows, so that the area of the support opening 21 is ensured, and even if the area of the support opening 21 is reduced, the lower electrodes can be formed by a single photolithography process without increasing difficulty.
As shown in fig. 2, at this time, when the support opening 21 supports the adjacent lower electrode 1, it may be connected to the outer wall of the adjacent lower electrode 1, and specifically, the support opening 21 may be connected to the storage node position of the lower electrode 1. Therefore, the storage nodes adjacent to the lower electrode 1 can be opened by the support opening 21, and all the storage nodes can be opened in the same condition in the subsequent process.
In one embodiment, the number of the lower electrodes 1 connected to each of the support openings 21 can be selected to be 6, the support openings are uniformly connected to 6 lower electrodes in the circumferential direction, and the 6 lower electrodes are connected to form a hexagonal prism shape. Meanwhile, the support opening 21 may be a circular opening, so that the circumference of the circular opening is uniformly connected with 6 lower electrodes 1. In this case, the circular opening has a large area, and even if the support opening 21 is reduced, it can be formed by a single photolithography process without increasing difficulty.
The plurality of support openings 21 may be distributed in a multi-row structure, and the adjacent lower electrodes 1 are correspondingly connected to the plurality of support openings 21. At the same time, a plurality of rows of the support openings 21 are arranged obliquely.
Further, the number of the support layer 2 is multiple; different layers of the support layer 2 are located at different heights of the lower electrode 1, and/or the support openings 21 of different layers of the support layer 2 are arranged in a staggered manner in the horizontal direction of the lower electrode 1. When the support layers 2 of different layers support and fix the lower electrode 1 at different heights of the lower electrode 1, stability of the lower electrode 1 at different positions in the height direction can be guaranteed. Wherein, the supporting layers 2 of different layers can also be arranged in a staggered way in the horizontal direction.
Wherein the support 2 is located on the outer sidewall of the lower electrode 1; and in the opening, the inner wall and/or the outer wall of the lower electrode 1 comprises a capacitance medium layer and an upper electrode. The semiconductor substrate comprises a landing pad, and the lower electrode 1 is electrically connected with the landing pad.
The invention also provides a DRAM, which comprises the capacitor; the number of the capacitors is multiple, and the capacitors are uniformly distributed; the semiconductor substrate 3 further comprises a buried channel array transistor therein; one of the active regions of the buried channel array transistor is connected to a bit line, and the other active region is electrically connected to the landing pad. Thus, in the chip structure of one DRAM, independent cells can be constituted by a plurality of the capacitors, so that the entire chip structure of the DRAM is constituted by the capacitors of a plurality of cells. Those skilled in the art can set the setting specifically according to the requirement, and details are not described herein. Since the detailed structure, functional principle and technical effect of the capacitor are described in detail in the foregoing, detailed description is omitted here. Therefore, reference can be made to the above description for any technical contents related to the capacitor.
The invention also provides a manufacturing method of the capacitor, which comprises the following steps: providing a semiconductor substrate 3; forming a stack structure comprising at least one patterned oxide layer and support members alternating on said semiconductor substrate 3; etching the laminated structure to form a contact hole; forming a lower electrode 1 in the contact hole; patterning the at least one support layer to form a support 2, the support 2 having a plurality of support openings 21, each of the support openings 21 passing through a plurality of adjacent lower electrodes 1 that may form a hexagonal prism shape, and the adjacent lower electrodes 1 that form the hexagonal prism shape belong to adjacent three rows.
Each of the support openings 21 exposes at least a portion of each of the lower electrodes 1 in two adjacent rows, and the support 2 supports the exposed sidewalls of the other portions of the lower electrodes 1. And respectively forming a capacitance dielectric layer and an upper electrode on the inner wall and/or the outer wall of the contact hole.
A stack structure formed by overlapping a mold oxide layer and a support layer may be formed on the semiconductor substrate 3, and then a hard mask layer may be disposed on the stack structure, and a photoresist pattern may be formed on the hard mask layer and patterned. And etching the stacked structure by taking the hard mask layer pattern as a mask, thereby forming the honeycomb-shaped distributed contact holes.
Next, a lower electrode is formed in the contact hole, and a lower electrode including TiN or the like may be formed in the contact hole by deposition, for example. Then, elliptical mask patterns distributed in a staggered mode are formed on the whole semiconductor substrate with the contact holes formed, and the residual stacked structures on the periphery of the contact holes are etched by taking the elliptical mask patterns as masks until circular openings with the same depth as the contact holes are formed. And then depositing a dielectric layer and an upper electrode on the inner wall and the outer wall of the lower electrode in the circular opening, wherein the upper electrode can be made of TiN, TaN or doped polysilicon and the like.
In addition, the skilled person can also pattern the support layer according to other ways, which is not limited herein. Correspondingly, there is a contact plug under the molding structure to mate with the storage node of the lower electrode 1, and the conductive pattern on the hard mask layer may be matched with the pattern of the contact plug and enable the lower electrode 1 to be matched with the pattern of the contact plug. At this time, the patterned structure on the support layer 2 may be matched with the conductive pattern of the hard mask layer.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (12)
1. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of lower electrodes formed on at least a partial region of the semiconductor substrate; the lower electrodes are distributed into a multi-row structure, and the lower electrodes in adjacent rows are arranged in a staggered manner;
the support piece comprises a plurality of support openings, each support opening passes through a plurality of adjacent lower electrodes capable of enclosing into a hexagonal prism shape, and the adjacent lower electrodes enclosing into the hexagonal prism shape belong to three adjacent rows.
2. The semiconductor structure of claim 1, wherein the number of the lower electrodes connected to each of the support openings is 6, and the support openings are uniformly connected to 6 lower electrodes in the circumferential direction, and the 6 lower electrodes are connected to form a hexagonal prism.
3. The semiconductor structure of claim 2, wherein the support opening is a circular opening.
4. The semiconductor structure of any one of claims 1-3, wherein a plurality of the support openings are distributed in a plurality of rows, and adjacent bottom electrodes are correspondingly connected to the plurality of rows of the support openings.
5. The semiconductor structure of claim 4, wherein the plurality of rows of support openings are arranged obliquely.
6. The semiconductor structure of claim 4, wherein the number of layers of the support layer is multiple; the supporting layers of different layers are positioned at different heights of the lower electrode, and/or the supporting openings of the supporting layers of different layers are arranged in a staggered manner in the horizontal direction of the lower electrode.
7. The semiconductor structure of claim 4, wherein the support is located on an outer sidewall of the lower electrode; and in the opening, the inner wall and/or the outer wall of the lower electrode comprise a capacitance medium layer and an upper electrode.
8. The semiconductor structure of claim 4, wherein the semiconductor substrate includes a landing pad thereon, and wherein the lower electrode is electrically connected to the landing pad.
9. A DRAM comprising the semiconductor structure of claim 8; the number of the semiconductor structures is multiple, and the semiconductor structures are uniformly distributed; the semiconductor substrate also comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line, and the other active region is electrically connected to the landing pad.
10. A method for fabricating an electronic structure, comprising the steps of:
providing a semiconductor substrate;
forming a stacked structure comprising at least one mold oxide layer and support members alternating on the semiconductor substrate;
etching the laminated structure to form a contact hole;
forming a lower electrode in the contact hole;
and patterning the at least one supporting layer to form a supporting part, wherein the supporting part is provided with a plurality of supporting openings, each supporting opening passes through a plurality of adjacent lower electrodes capable of forming a hexagonal shape, and the adjacent lower electrodes forming the hexagonal shape belong to three adjacent rows.
11. The method of claim 10, wherein each of the supporting openings exposes at least a portion of each of the bottom electrodes in two adjacent rows, and the supporting members support sidewalls of the other exposed portions of the bottom electrodes.
12. The method of claim 10, wherein a capacitor dielectric layer and an upper electrode are formed on an inner wall and/or an outer wall of the contact hole, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110113945.4A CN114824078A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110113945.4A CN114824078A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
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| Publication Number | Publication Date |
|---|---|
| CN114824078A true CN114824078A (en) | 2022-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110113945.4A Pending CN114824078A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
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- 2021-01-27 CN CN202110113945.4A patent/CN114824078A/en active Pending
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