CN114824081A - Semiconductor structure and manufacturing method thereof and DRAM - Google Patents
Semiconductor structure and manufacturing method thereof and DRAM Download PDFInfo
- Publication number
- CN114824081A CN114824081A CN202110113961.3A CN202110113961A CN114824081A CN 114824081 A CN114824081 A CN 114824081A CN 202110113961 A CN202110113961 A CN 202110113961A CN 114824081 A CN114824081 A CN 114824081A
- Authority
- CN
- China
- Prior art keywords
- support
- openings
- opening
- row
- lower electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random access memory), which relate to the technical field of semiconductors and comprise a semiconductor substrate; the lower electrodes are arranged on the semiconductor substrate and distributed into a multi-row structure, and the lower electrodes of adjacent rows are arranged in a staggered manner; the support piece comprises a plurality of support openings, the support openings are distributed in a multi-row structure, and each row of support openings at least comprises a first support opening and a second support opening which are staggered in sequence and are mutually complemented; the first and second support openings each simultaneously expose a plurality of adjacent lower electrodes. In the technical scheme, the support openings in different shapes are arranged in a staggered and mutually complementary mode, so that all the lower electrodes are connected in the region through which each row of support openings passes, the area of the lower electrode separation region in the unit region is effectively enlarged, and the sizes of the support openings in different unit regions for the lower electrode separation region are kept consistent.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random access memory).
Background
The bottom electrode is generally used in an integrated circuit, and the lateral dimension of the bottom electrode is reduced, so that valuable semiconductor substrate area is saved. The lower electrode is easy to fall along with the increase of the aspect ratio of the lower electrode, so the support is adopted to support the lower electrode, and the stability of the lower electrode is kept. However, when the support opening of the support member supports the lower electrode in the prior art, the support opening has different sizes of regions separating the lower electrode in different unit regions, which may cause differences in performance of the lower electrode, and ultimately may result in poor products.
Disclosure of Invention
The invention aims to provide a semiconductor structure, a manufacturing method thereof and a DRAM (dynamic random access memory), so as to solve the technical problem that the performance of a lower electrode is influenced by different sizes of regions for separating the lower electrode in different unit regions in the prior art.
The invention provides a semiconductor structure, comprising:
a semiconductor substrate;
the lower electrodes are arranged on the semiconductor substrate and distributed into a multi-row structure, and the lower electrodes in adjacent rows are arranged in a staggered mode;
the support piece comprises a plurality of support openings, the support openings are distributed in a multi-row structure, and each row of the support openings at least comprises a first support opening and a second support opening which are staggered in sequence and are mutually supplemented;
the first supporting opening and the second supporting opening are connected with a plurality of adjacent lower electrodes at the same time.
The invention also provides a DRAM, which comprises the semiconductor structure; the number of the semiconductor structures is multiple, and the semiconductor structures are uniformly distributed; the semiconductor substrate also comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line, and the other active region is electrically connected to the landing pad.
The invention also provides a manufacturing method of the electronic structure, which comprises the following steps:
providing a semiconductor substrate;
forming a stacked structure comprising at least one mold oxide layer and support members alternating on the semiconductor substrate;
etching the laminated structure to form a contact hole;
forming a lower electrode in the contact hole;
patterning the at least one support member to form a plurality of support members, wherein a plurality of rows of support openings are formed in the support members, each row of support openings forms a first support opening and a second support opening which are sequentially staggered and mutually complemented, and the first support opening and the second support opening are simultaneously connected with a plurality of adjacent contact holes.
In the technical scheme, the support openings in different shapes are arranged in a staggered and mutually complementary mode in sequence, so that all the lower electrodes are connected in the region through which each row of support openings passes, any lower electrode cannot be missed, and the area of the lower electrode separation region in the unit region is effectively enlarged. At the moment, after all the supporting openings are arranged according to the regular quadrilateral structure in the same way, the sizes of the areas of the supporting openings for separating the lower electrodes in different unit areas can be kept consistent, the areas of the separating areas can be enlarged, and the yield of products is finally improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in accordance with one embodiment of the present invention;
fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor structure according to an embodiment of the invention.
Reference numerals:
1. a lower electrode; 2. a support member; 3. a semiconductor substrate;
21. supporting the opening.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The present invention will be described in detail below with embodiments of the present invention applied to capacitors in DRAM products.
As shown in fig. 1 to fig. 2, the present embodiment provides a capacitor, including: a semiconductor substrate 3; the lower electrodes 1 are arranged on the semiconductor substrate 3, the lower electrodes 1 are distributed in a multi-row structure, and the lower electrodes 1 in adjacent rows are arranged in a staggered manner; at least one layer of supporting member 2, the supporting member 2 includes a plurality of supporting openings 21 therein, the supporting openings 21 are distributed in a multi-row structure, each row of the supporting openings includes at least a first supporting opening and a second supporting opening which are staggered in sequence and are mutually complementary; the first support opening and the second support opening each simultaneously expose a plurality of adjacent lower electrodes 1.
Referring to fig. 1, the lower electrodes 11 of the capacitor are supported by the support openings 21, so that the lower electrodes 11 can be kept stable even in a high aspect ratio structure, and the problems of inclination and collapse are avoided. After the support 2 is patterned, the support openings 21 formed by patterning need to have a plurality of different shapes, and when the support openings 21 are arranged, the plurality of support openings 21 may be distributed in a plurality of rows in the central region. When the support openings 21 are arranged in each row, the support openings 21 with different shapes in each row are formed in a mode of sequentially staggering and mutually supplementing each other. For example, the first support opening is an elliptical opening, the second support opening is a circular opening, and the elliptical opening and the circular opening are staggered in sequence and complement each other to form each row of support openings.
Referring to fig. 1, in such an arrangement manner that the support openings 21 of different shapes are staggered in sequence and are complementary to each other, it can be ensured that all the lower electrodes 1 are connected in the region through which each row of the support openings 21 passes, and any one of the lower electrodes 1 is not missed, so that the area of the separation region of the lower electrode 1 in the cell region is effectively enlarged, and correspondingly, only a small part of the unseparated region is provided around the cell region.
At this time, after all the support openings 21 are arranged according to the regular quadrilateral structure in the same manner, the sizes of the regions, separated from the lower electrode 1, of the support openings 21 in different unit regions can be kept consistent, the area of the separated regions can be enlarged, and the yield of products is finally improved.
As shown in fig. 2, at this time, when the support opening 21 supports the adjacent lower electrode 1, it may be connected to the outer wall of the adjacent lower electrode 1, and specifically, the support opening 21 may be connected to the storage node position of the lower electrode 1. Therefore, the storage nodes adjacent to the lower electrode 1 can be opened by the support opening 21, and all the storage nodes can be opened in the same condition in the subsequent process.
As shown in fig. 1, when the kinds of the support openings 21 are selected to be two, the support openings 21 may be provided as an elliptical opening and a circular opening, and at this time, the elliptical opening and the circular opening are sequentially staggered and complement each other to constitute each row of the support openings 21. In the arrangement mode, the elliptical openings and the circular openings are arranged in a staggered and mutually complementary arrangement mode in sequence, so that all the lower electrodes 1 are connected by the elliptical openings and the circular openings in the area where each row of the elliptical openings and the circular openings pass through, any one lower electrode 1 cannot be missed, and the separation area surface of the lower electrode 1 in the unit area is enlarged.
For example, the multiple rows of structures are rectangular or rhombic, so that when the rectangular or rhombic structures are arranged mutually, the area utilization rate is higher. When arranging the support openings 21, firstly, some of the support openings 21 may be uniformly arranged at the middle position of the central region, and then the other support openings 21 are additionally arranged around the central region, so that all the support openings 21 are arranged in a rectangular or rhombic shape on the central region.
In one embodiment, when the multiple rows are selected to be rectangular, the differently shaped support openings 21 may be staggered and complementary to each other in sequence both in the transverse and longitudinal directions of the rectangle. For example, the plurality of rows of structures form a rectangle, and the first support openings and the second support openings are sequentially staggered and complement each other in both the lateral direction and the longitudinal direction of the rectangle. In this arrangement, the support openings 21 of different shapes are arranged in a staggered and mutually complementary arrangement in sequence, so that all the lower electrodes 1 are connected in the region where each row of support openings 21 passes through, and any lower electrode 1 cannot be missed, which is arranged in a transverse direction.
Meanwhile, in the longitudinal arrangement, that is, between adjacent rows of the support openings 21, the support openings 21 of different shapes are arranged in a staggered and mutually complementary manner in sequence, so that all the lower electrodes 1 are connected in the region through which the longitudinal support openings 21 pass, and any one lower electrode 1 cannot be missed, which can effectively enlarge the separation region area of the lower electrode 1 in the unit region in the whole region.
For example, as shown in fig. 1, the kinds of the support openings 21 are selected to be two, and the support openings 21 may be selected to be an elliptical opening and a circular opening, which are sequentially staggered and complement each other in both the transverse direction and the longitudinal direction of the rectangle. Through with oval opening and circular opening in order crisscross and the mode of arranging that complements each other in proper order, can guarantee in the region that every row of oval opening and circular opening passed through, all lower electrodes 1 all are connected by oval opening and circular opening, can not leak down any lower electrode 1, and this is horizontal row cloth.
Meanwhile, in the longitudinal arrangement, namely between the adjacent rows of support openings 21, the elliptical openings and the circular openings are arranged in a staggered and mutually complementary manner, so that all the lower electrodes 1 are connected by the elliptical openings and the circular openings in the region through which the longitudinal support openings 21 pass, any lower electrode 1 cannot be missed, and the separation region area of the lower electrode 1 in the unit region is effectively enlarged in the whole region.
In this embodiment, each of the elliptical openings is simultaneously connected between adjacent 4 of the lower electrodes 1; and/or, each circular opening is connected between 3 adjacent lower electrodes 1 at the same time. The oval opening can be obliquely arranged in the horizontal direction, and the long axis direction of the opening is parallel to the arrangement direction of the multiple rows of structures.
Further, the number of layers of the support member 2 is multiple, and the support members 2 of different layers are located at different heights of the lower electrode 1. When the support members 2 of different layers support and fix the lower electrode 1 at different heights of the lower electrode 1, the stability of the lower electrode 1 at different positions in the height direction can be guaranteed. Wherein the supporting members 2 of different layers may also be arranged in a staggered manner in the horizontal direction.
In the manufacturing of the capacitor, a plurality of lower electrodes 1 and at least one layer of support member 2 may be first provided on the semiconductor substrate 3, the support member 2 may be patterned to form the patterned support openings 21 in different shapes, and the plurality of support openings 21 may be distributed in a multi-row structure on the central region. When the support openings 21 are arranged in each row, the support openings 21 with different shapes in each row are formed in a mode of sequentially interleaving and mutually complementing, so that all the lower electrodes 1 passing through are connected by the support openings 21.
During the manufacturing process, a mold structure may be first disposed on the semiconductor substrate 3, a hard mask layer may be disposed on the mold structure, and a conductive pattern corresponding to the patterned structure of the support 2 may be formed on the hard mask layer. Then, the support member 2 is etched according to the structure of the conductive pattern, so that a part of the structure of the support member 2 is exposed, and the support member 2 is continuously etched, so that the support member 2 can be patterned, and the support member 2 can be formed into different shapes.
Besides, the support is located on the outer sidewall of the lower electrode 1; and in the opening, the inner wall and/or the outer wall of the lower electrode 1 comprises a capacitance medium layer and an upper electrode. The semiconductor substrate 3 includes a landing pad thereon, and the lower electrode 1 is electrically connected to the landing pad. In addition, the skilled person can also pattern the support 2 according to other ways, which are not limited herein. Correspondingly, there is a contact plug under the molding structure to mate with the storage node of the lower electrode 1, and the conductive pattern on the hard mask layer may be matched with the pattern of the contact plug and enable the lower electrode 1 to be matched with the pattern of the contact plug. At this time, the patterned structure on the support 2 may be matched with the conductive pattern of the hard mask layer.
The invention also provides a DRAM, which comprises the capacitor; the capacitor is a plurality of, a plurality of the capacitor is evenly arranged. Thus, in the chip structure of one DRAM, independent cells can be constituted by a plurality of the capacitors, so that the entire chip structure of the DRAM is constituted by the capacitors of a plurality of cells. Those skilled in the art can set the setting specifically according to the requirement, and the detailed description is omitted here. Since the detailed structure, functional principle and technical effect of the capacitor are described in detail in the foregoing, further description is omitted here. Therefore, reference is made to the above description for any technical content related to the capacitor.
The invention also provides a manufacturing method of the capacitor, which comprises the following steps: providing a semiconductor substrate 3; forming a stack structure comprising at least one patterned oxide layer and support members alternating on said semiconductor substrate 3; etching the laminated structure to form a contact hole; forming a lower electrode 1 in the contact hole; patterning the at least one support 2 to form a plurality of supports 2, forming a plurality of rows of support openings 21 in the supports 2, such that each row of support openings 21 constitutes a first support opening and a second support opening which are staggered in sequence and complement each other, and the first support opening and the second support opening both connect a plurality of adjacent contact holes simultaneously.
Each of the first support opening and the second support opening exposes at least a portion of each of the lower electrodes 1 in two adjacent rows, and the support supports sidewalls of the other exposed portions of the lower electrodes 1. And respectively forming a capacitance dielectric layer and an upper electrode on the inner wall and/or the outer wall of the contact hole.
A stack structure formed by overlapping a mold oxide layer and a support layer may be formed on the semiconductor substrate 3, and then a hard mask layer may be disposed on the stack structure, and a photoresist pattern may be formed on the hard mask layer and patterned. And then, etching the stacked structure by taking the hard mask layer pattern as a mask, thereby forming the contact holes distributed in a honeycomb shape.
Next, a lower electrode is formed in the contact hole, and a lower electrode including TiN or the like may be formed in the contact hole by deposition, for example. Then, elliptical mask patterns distributed in a staggered mode are formed on the whole semiconductor substrate with the contact holes formed, and the residual stacked structures on the periphery of the contact holes are etched by taking the elliptical mask patterns as masks until elliptical openings or circular openings with the same depth as the contact holes are formed. And then depositing a dielectric layer and an upper electrode on the inner wall and the outer wall of the lower electrode in the oval opening or the circular opening, wherein the upper electrode can be made of TiN, TaN or doped polysilicon and the like.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. A semiconductor structure, comprising:
a semiconductor substrate;
the lower electrodes are arranged on the semiconductor substrate and distributed into a multi-row structure, and the lower electrodes in adjacent rows are arranged in a staggered mode;
the support piece comprises a plurality of support openings, the support openings are distributed in a multi-row structure, and each row of the support openings at least comprises a first support opening and a second support opening which are staggered in sequence and are mutually supplemented; the first support opening and the second support opening each simultaneously expose a plurality of adjacent lower electrodes.
2. The semiconductor structure of claim 1, wherein the first support opening is an elliptical opening and the second support opening is a circular opening, and the elliptical openings and the circular openings are staggered and complement each other to form each row of the support openings.
3. The semiconductor structure of claim 1, wherein the plurality of rows of structures form a rectangle, and the first support openings and the second support openings are sequentially staggered and complementary to each other in both a lateral direction and a longitudinal direction of the rectangle.
4. The semiconductor structure of claim 3, wherein the first support opening is an elliptical opening and the second support opening is a circular opening, and wherein the elliptical and circular openings are sequentially staggered and complementary to each other in both the lateral and longitudinal directions of the rectangle.
5. The semiconductor structure of claim 2 or 4, wherein each of the elliptical openings is simultaneously connected between adjacent 4 of the lower electrodes.
6. The semiconductor structure of claim 2 or 4, wherein the elliptical openings are arranged obliquely in a horizontal direction, and a long axis direction of the openings is parallel to an arrangement direction of the plurality of rows of structures.
7. The semiconductor structure of any one of claims 1-4, wherein the number of layers of the support member is multiple, and different layers of the support member are located at different heights of the lower electrode.
8. The semiconductor structure of any of claims 1-4, wherein the support is located on an outer sidewall of the lower electrode; and in the opening, the inner wall and/or the outer wall of the lower electrode comprise a capacitance medium layer and an upper electrode.
9. The semiconductor structure of any of claims 1-4, wherein the semiconductor substrate includes a landing pad, and wherein the lower electrode is electrically connected to the landing pad.
10. A DRAM comprising the semiconductor structure of claim 9; the number of the semiconductor structures is multiple, and the semiconductor structures are uniformly distributed; the semiconductor substrate also comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line, and the other active region is electrically connected to the landing pad.
11. A method for fabricating an electronic structure, comprising the steps of:
providing a semiconductor substrate;
forming a stacked structure comprising at least one mold oxide layer and support members alternating on the semiconductor substrate;
etching the laminated structure to form a contact hole;
forming a lower electrode in the contact hole;
patterning the at least one support member to form a plurality of support members, wherein a plurality of rows of support openings are formed in the support members, each row of support openings forms a first support opening and a second support opening which are sequentially staggered and mutually complemented, and the first support opening and the second support opening are simultaneously connected with a plurality of adjacent contact holes.
12. The method of claim 11, wherein each of the oval openings exposes at least a portion of each of the bottom electrodes in two adjacent rows, and the supporting member supports sidewalls of the other exposed portions of the bottom electrodes.
13. The method of claim 11, wherein a capacitor dielectric layer and an upper electrode are formed on an inner wall and/or an outer wall of the contact hole, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110113961.3A CN114824081A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110113961.3A CN114824081A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114824081A true CN114824081A (en) | 2022-07-29 |
Family
ID=82523632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110113961.3A Pending CN114824081A (en) | 2021-01-27 | 2021-01-27 | Semiconductor structure and manufacturing method thereof and DRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114824081A (en) |
-
2021
- 2021-01-27 CN CN202110113961.3A patent/CN114824081A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8258574B2 (en) | Semiconductor decoupling capacitor device | |
| US11195837B2 (en) | Semiconductor devices including support patterns | |
| JPH0766299A (en) | Semiconductor storage device | |
| JP2012146993A (en) | Methods of forming capacitor devices | |
| KR101102764B1 (en) | Layout of semiconductor device and method of fabricating the semiconductor device | |
| US10886276B2 (en) | Semiconductor memory device and method of fabricating the same | |
| US20210343833A1 (en) | Double-sided capacitor structure and method for forming the same | |
| JPH10144883A (en) | Semiconductor memory and fabrication thereof | |
| JP5057616B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9461162B2 (en) | Semiconductor integrated circuit device having reduced unit cell area | |
| CN114824081A (en) | Semiconductor structure and manufacturing method thereof and DRAM | |
| US7714372B2 (en) | Dynamic random access memory devices and methods of forming the same | |
| CN114824079A (en) | Semiconductor structure and manufacturing method thereof and DRAM | |
| WO2022028175A1 (en) | Memory forming method and memory | |
| CN113497038B (en) | Semiconductor device and method for forming the same | |
| CN114824076A (en) | Semiconductor structure and manufacturing method thereof and DRAM | |
| CN114824078A (en) | Semiconductor structure and manufacturing method thereof and DRAM | |
| US8394697B2 (en) | Methods of forming capacitors for semiconductor memory devices | |
| CN114628388A (en) | Semiconductor structure and method for manufacturing capacitor | |
| US20050106808A1 (en) | Semiconductor devices having at least one storage node and methods of fabricating the same | |
| US11961881B2 (en) | Method for forming semiconductor structure and semiconductor structure | |
| US20220052151A1 (en) | Method for forming semiconductor structure and semiconductor structure | |
| WO2023245817A9 (en) | Semiconductor structure and manufacturing method therefor, memory chip and electronic device | |
| US20230369145A1 (en) | Semiconductor structure and manufacturing method therefor | |
| CN114678358A (en) | Semiconductor structure and manufacturing process thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |