CN114678358A - Semiconductor structure and manufacturing process thereof - Google Patents
Semiconductor structure and manufacturing process thereof Download PDFInfo
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- CN114678358A CN114678358A CN202011551521.8A CN202011551521A CN114678358A CN 114678358 A CN114678358 A CN 114678358A CN 202011551521 A CN202011551521 A CN 202011551521A CN 114678358 A CN114678358 A CN 114678358A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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Abstract
The invention provides a semiconductor structure and a manufacturing process thereof, which relate to the technical field of semiconductors and comprise the following steps: a semiconductor substrate; the capacitor comprises a lower electrode in a groove shape, a dielectric layer and an upper electrode which are positioned on the inner wall of the lower electrode form a first capacitor, and the dielectric layer and the upper electrode which are positioned on the outer wall of the lower electrode form a second capacitor; at least one layer of supporting piece, the supporting piece is positioned on the outer wall of the lower electrode to support and fix the capacitors; wherein the top of the lower electrode is higher than the topmost support layer. In the above technical solution, the top layer of the topmost supporting layer is covered by a sacrificial supporting layer, and the sacrificial supporting layer can reserve a formation space of the capacitor in a formation process of the capacitor, and after the sacrificial supporting layer is finally removed, the space left by the sacrificial supporting layer can be used for forming the capacitor, thereby effectively expanding the capacity of the capacitor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing process thereof.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory, and the main function of the DRAM is to represent whether a binary bit (bit) is 1 or 0 by the amount of charge stored in a capacitor. In the dram, the capacitor is one of the most important factors determining the characteristics of the dram, and thus it is important to maximize the capacitor when developing a semiconductor device. However, as semiconductor devices are gradually scaled down, the size of capacitors is also gradually reduced, which directly affects the characteristics of the dram.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing process thereof, which can improve the capacitance of a capacitor and solve the technical problem that the size of the capacitor is reduced and the characteristics of a dynamic random access memory are influenced in the prior art.
The invention provides a semiconductor structure, comprising:
a semiconductor substrate;
the capacitor comprises a lower electrode in a groove shape, a dielectric layer and an upper electrode which are positioned on the inner wall of the lower electrode form a first capacitor, and the dielectric layer and the upper electrode which are positioned on the outer wall of the lower electrode form a second capacitor;
at least one layer of supporting piece, wherein the supporting piece is positioned on the outer wall of the lower electrode to form supporting fixation for a plurality of capacitors; wherein the top of the lower electrode is higher than the topmost support layer.
The application also provides a manufacturing process of the semiconductor structure, which comprises the following steps:
providing a semiconductor substrate;
forming a stack structure consisting of a molding layer and a support layer stack on the semiconductor substrate, and forming a sacrificial support layer on a top layer of the stack structure;
forming a plurality of cylindrical capacitors distributed in a honeycomb shape on the stacked structure, and removing the sacrificial support layer in the process of the support layer after the lower electrodes in the groove shape are arranged on the capacitors; and then forming a first capacitor on the dielectric layer on the inner wall of the lower electrode and the upper electrode, and forming a second capacitor on the dielectric layer on the outer wall of the lower electrode and the upper electrode.
In the above technical solution, the top layer of the topmost supporting layer is covered by a sacrificial supporting layer, so that the sacrificial supporting layer can reserve a formation space of a capacitor in a formation process of the capacitor, and after the sacrificial supporting layer is finally removed, the space left by the sacrificial supporting layer can be used for forming the capacitor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram illustrating a first step of a semiconductor structure fabrication process according to an embodiment of the present invention;
FIG. 2 is a structural diagram illustrating a second step of a semiconductor structure fabrication process according to one embodiment of the present invention;
FIG. 3 is a schematic structural diagram illustrating a third step in a process for fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a fourth step of a semiconductor structure fabrication process according to an embodiment of the invention.
Reference numerals:
1. a semiconductor substrate; 2. a stacked structure; 3. a capacitor; 4. a hard mask layer;
21. a sacrificial support layer; 22. a top mold layer; 23. a bottom mold layer; 24. a top support layer; 25. a bottom support layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As a result of research on the semiconductor structure in the prior art, after the capacitor 3 is formed in the stacked structure 2 formed by the support layer and the molding layer, generally, the top layer of the stacked structure 2 is the support layer, and the support layer is not removed in the process of forming the capacitor 3, so that the outermost layer of the stacked structure 2 cannot be used as the capacitor 3, that is, the position of the outermost support layer in the stacked structure 2 determines the height of the capacitor 3, which is one of the factors that limit the capacity of the capacitor 3. In order to solve the above technical problems, the present application provides the following technical solutions.
As shown in fig. 1 to 4, the present embodiment provides a semiconductor structure, which includes a semiconductor substrate 1; the capacitor structure comprises a plurality of cylindrical capacitors 3 distributed in a honeycomb manner, wherein the plurality of cylindrical capacitors 3 are arranged on a substrate, each capacitor 3 comprises a lower electrode in a groove shape, a dielectric layer and an upper electrode which are positioned on the inner wall of each lower electrode form a first capacitor, and a dielectric layer and an upper electrode which are positioned on the outer wall of each lower electrode form a second capacitor; at least one layer of support members, which are positioned on the outer wall of the lower electrode to form a supporting fixation for a plurality of capacitors 3; wherein the top of the lower electrode is higher than the topmost support layer. Wherein the semiconductor substrate 1 includes thereon a transistor including a gate line and a plurality of active regions, one of the active regions being connected to a bit line, the other active regions being in contact with a storage node connected to a lower electrode of the capacitor 3.
The manufacturing process of the semiconductor structure comprises the following steps: providing a semiconductor substrate 1; forming a stack structure 2 composed of a molding layer and a support layer stack on the semiconductor substrate 1, and forming a sacrificial support layer 21 on a top layer of the stack structure 2; forming a plurality of cylindrical capacitors 3 distributed in a honeycomb shape on the stacked structure 2, and removing the sacrificial support layer 21 in a support layer process after arranging groove-shaped lower electrodes on the capacitors; and then forming a first capacitor on the dielectric layer on the inner wall of the lower electrode and the upper electrode, and forming a second capacitor on the dielectric layer on the outer wall of the lower electrode and the upper electrode.
Referring to fig. 1, in this fabrication process, a stack structure 2 formed during the formation of a capacitor 3 is formed by alternately stacking a support layer and a molding layer, and a sacrificial support layer 21 is formed on the top layer of the stack structure. Therefore, the top layer of the topmost support layer is also covered by a sacrificial support layer 21. Therefore, the sacrificial support layer 21 can reserve a forming space for the capacitor 3 in the forming process of the capacitor 3, and after the sacrificial support layer 21 is finally removed, the space left by the sacrificial support layer 21 can be used for forming the capacitor 3, and further, compared with the capacitor 3 in the prior art, the capacitor 3 formed in the manufacturing process can extend to the top layer of the support layer, so that the capacity of the capacitor 3 is effectively expanded, and the limitation of the support layer in the prior art on the height of the capacitor 3 is broken.
For the materials of the sacrificial support layer 21 and the molding layers, the sacrificial support layer 21 and the molding layers may be made of different materials, and at least for the sacrificial support layer 21, a material that can be removed together with an oxide in wet etching may be used to form the sacrificial support layer 21, so that the sacrificial support layer 21 may be removed by using a single step and process, while for the molding layers of other layers, the same material may be used or other materials may be used, and the removal process and step may also be set as required, for example, a silicon nitride material is used to form the sacrificial support layer 21. Alternatively, all of the molding layers may be formed of a silicon nitride material. The technical personnel in the field can set according to the needs, and do not limit here.
When the sacrificial support layer 21 is formed, the sacrificial support layer 21 may be formed by a deposition process, or may be formed by other processes, which is not limited herein. With continued reference to fig. 1 to 4, when etching the molding layers of other layers by dry etching, the support layer at the topmost layer may be patterned first, so that the molding layer below the support layer at the topmost layer is exposed, and at this time, the molding layer at the topmost layer is etched, so that the removal of the molding layer at this time may be completed. By analogy, when the stacked structure 2 is stacked and staggered by the multiple supporting layers and the molding layers, the rest of the supporting layers can be sequentially etched according to the steps, and after the bottommost molding layer is exposed, the bottommost molding layer is etched by adopting a dry etching method.
Preferably, after patterning the support layer by a dry etching process, the sacrificial support layer 21 is removed from the molding layer of the oxide sequence by an etchant used in wet etching. Therefore, the sacrificial support layer 21 is located at the topmost layer of the stacked structure 2, and is adjacent to the hard mask layer 4, so that after other molding layers are removed and the capacitor 3 is formed, the sacrificial support layer 21 can be removed in a final process, for example, when the support layer is patterned by a dry etching process, the sacrificial support layer 21 can be simultaneously removed by using an etchant for etching the support layer, and after the sacrificial support layer 21 is removed, the capacitor 3 can be finally formed, and the capacity of the capacitor 3 is further enlarged by using a space left by the sacrificial support layer 21.
When etching the support layer and the sacrificial support layer 21, a hard mask layer 4 may be formed on the stack structure 2, a conductive pattern may be formed on the hard mask layer 4, and then the support layer may be patterned according to the conductive pattern. Correspondingly, there is a contact plug (not shown) under the stacked structure 2 that mates with the storage node of the capacitor 3, and the conductive pattern on the hard mask layer 4 may mate with the pattern of the contact plug and enable the capacitor 3 to mate with the pattern of the contact plug. At this time, the supporting pattern on the supporting layer and the conductive pattern of the hard mask layer 4 are matched with each other, and a person skilled in the art can set a specific supporting pattern by himself, which is not limited herein.
In one embodiment, referring to fig. 1 to 4, a bottom mold layer 23 is formed on the semiconductor substrate 1, a bottom support layer 25 is formed on the bottom mold layer 23, a top mold layer 22 is formed on the bottom support layer 25, a top support layer 24 is formed on the top mold layer 22, and a sacrificial support layer 21 is formed on the top support layer 24; and removing the sacrificial support layer 21, the top mold layer 22 and the bottom mold layer 23.
Therefore, in this process step, a bottom mold layer 23 may be formed on the substrate 1, a bottom support layer 25 may be formed on the bottom mold layer 23, a top mold layer 22 may be formed on the bottom support layer 25, a top support layer 24 may be formed on the top mold layer 22, and a sacrificial support layer 21 may be formed on the top support layer 24, so that a stacked structure 2 may be constructed by stacking and interleaving three mold layers and two support layers, and then the sacrificial support layer 21, the top mold layer 22, and the bottom mold layer 23 may be etched and removed, and then, after the sacrificial support layer 21, the top mold layer 22, and the bottom mold layer 23 are removed, the capacitor 3 may extend to the top of the top support layer 24, thereby expanding the capacity of the capacitor 3.
Similarly, the sacrificial support layer 21 is formed at least by using a silicon nitride material, and when the top mold layer 22 and the bottom mold layer 23 are removed by using a wet etching process, the sacrificial support layer 21 can be removed at the same time, and after the sacrificial support layer 21 is removed, the capacitor 3 can be finally formed, so that the capacity of the capacitor 3 is enlarged by using the space given out by the sacrificial support layer.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A semiconductor structure, comprising:
a semiconductor substrate;
the capacitor comprises a lower electrode in a groove shape, a dielectric layer and an upper electrode which are positioned on the inner wall of the lower electrode form a first capacitor, and the dielectric layer and the upper electrode which are positioned on the outer wall of the lower electrode form a second capacitor;
at least one layer of supporting piece, wherein the supporting piece is positioned on the outer wall of the lower electrode to form supporting fixation for a plurality of capacitors; wherein the top of the lower electrode is higher than the topmost support layer.
2. The semiconductor structure of claim 1, wherein the semiconductor substrate comprises a transistor comprising a gate line and a plurality of active regions, one of the active regions being connected to a bit line, the other active regions being in contact with a storage node, the storage node being connected to a lower electrode of the capacitor.
3. A manufacturing process of a semiconductor structure is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a stack structure consisting of a molding layer and a support layer stack on the semiconductor substrate, and forming a sacrificial support layer on a top layer of the stack structure;
forming a plurality of cylindrical capacitors distributed in a honeycomb shape on the stacked structure, and removing the sacrificial support layer in the process of the support layer after the lower electrodes in the groove shape are arranged on the capacitors; and then forming a first capacitor on the dielectric layer on the inner wall of the lower electrode and the upper electrode, and forming a second capacitor on the dielectric layer on the outer wall of the lower electrode and the upper electrode.
4. The process of claim 3 wherein the sacrificial support layer is formed using a material that is removed with the oxide during the wet etch.
5. The process of claim 4 wherein the sacrificial support layer is formed of a silicon nitride material.
6. The manufacturing process according to claim 5, wherein the molding layer is formed using a silicon nitride material.
7. The process of claim 3, wherein the sacrificial support layer is formed using a deposition process.
8. A production process according to any one of claims 3 to 7, characterized in that after patterning the support layer by means of a dry etching process, the sacrificial support layer is removed from the molding layer of the oxide sequence by means of an etchant used in wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011551521.8A CN114678358A (en) | 2020-12-24 | 2020-12-24 | Semiconductor structure and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011551521.8A CN114678358A (en) | 2020-12-24 | 2020-12-24 | Semiconductor structure and manufacturing process thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114678358A true CN114678358A (en) | 2022-06-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011551521.8A Pending CN114678358A (en) | 2020-12-24 | 2020-12-24 | Semiconductor structure and manufacturing process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114678358A (en) |
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2020
- 2020-12-24 CN CN202011551521.8A patent/CN114678358A/en active Pending
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