CN111883532B - Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment - Google Patents
Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment Download PDFInfo
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- CN111883532B CN111883532B CN202010597559.2A CN202010597559A CN111883532B CN 111883532 B CN111883532 B CN 111883532B CN 202010597559 A CN202010597559 A CN 202010597559A CN 111883532 B CN111883532 B CN 111883532B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 6
- 101710105312 Branched-chain-amino-acid aminotransferase Proteins 0.000 description 4
- 101710097328 Branched-chain-amino-acid aminotransferase, cytosolic Proteins 0.000 description 4
- 101710194298 Branched-chain-amino-acid aminotransferase, mitochondrial Proteins 0.000 description 4
- 101710158343 Probable branched-chain-amino-acid aminotransferase Proteins 0.000 description 4
- 101710199693 Putative branched-chain-amino-acid aminotransferase Proteins 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- AZPBDRUPTRGILK-UHFFFAOYSA-N benzotriazol-1-ium-1-ylidenemethanediamine;4-methylbenzenesulfonate Chemical compound CC1=CC=C(S(O)(=O)=O)C=C1.C1=CC=C2N(C(=N)N)N=NC2=C1 AZPBDRUPTRGILK-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000005288 electromagnetic effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Abstract
The present disclosure provides a semiconductor structure, a method of manufacturing the same, a semiconductor memory, and an electronic device. The semiconductor structure of the present disclosure includes: a semiconductor substrate comprising a first active region and a second active region, wherein the first active region is provided with a grid groove; a first gate structure filled in the gate trench of the first active region; and a second gate structure formed over the second active region. According to the semiconductor structure, word lines are formed above and below the semiconductor substrate in a staggered mode, the physical distance between the word lines is prolonged, and electromagnetic interference between adjacent word lines is reduced.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a manufacturing method thereof, a semiconductor memory and an electronic device.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory that generally includes an array of memory cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing charge (i.e., bits of information) and a transistor that provides an access signal to the capacitor during read and write operations. The transistor is connected between the bit line and the capacitor and is gated (turned on or off) by the word line signal. During a read operation, bits of stored information are read from the cells via the associated bit lines. During a write operation, bits of information are stored in the cell from the bit line via the transistor. The cells are dynamic in nature (due to leakage) and must therefore be periodically refreshed.
The RowHammer attack is an attack on DRAM. The main working principle is as follows: the electromagnetic effect between adjacent memory units in the high-density memory is utilized to cause errors, such as: an attacker can increase the probability of a mutation of the target memory by frequently accessing the memory of adjacent lines of the target memory, and cause a change in the stored value in a target memory area which is not originally authorized to be accessed.
The RowHammer problem still exists in the existing DRAM, and the physical distance between semiconductor devices in the DRAM is reduced by the progress of DRAM manufacturing technology, so that the physical distance between word lines is also reduced, and the RowHammer problem is more serious due to the increase of the coupling between word lines. The RowHammer problem, which is an important issue regarding DRAM reliability, is expected to be more serious in the future, and the improvement of the coupling between word lines is urgent.
Disclosure of Invention
An object of the present disclosure is to provide a semiconductor structure, a method of manufacturing the semiconductor structure, a semiconductor memory, and an electronic device.
A first aspect of the present disclosure provides a semiconductor structure comprising:
a semiconductor substrate comprising a first active region and a second active region, wherein the first active region is provided with a grid groove;
a first gate structure filled in the gate trench of the first active region;
and a second gate structure formed over the second active region.
A second aspect of the present disclosure provides a method for fabricating a semiconductor structure, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first active region and a second active region;
forming a gate trench in the first active region;
forming a first gate structure in the gate trench of the first active region;
a second gate structure is formed over the second active region.
A third aspect of the present disclosure provides a semiconductor memory, comprising:
a semiconductor structure as claimed in the first aspect.
A fourth aspect of the present disclosure provides an electronic device, comprising:
the semiconductor memory as described in the third aspect.
Compared with the prior art, the utility model has the advantages that:
the semiconductor structure provided by the disclosure is characterized in that word lines are formed above and below a semiconductor substrate in a staggered manner, the physical distance between the word lines is prolonged, and the electromagnetic interference between adjacent word lines is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 shows a schematic structure of a conventional semiconductor structure;
fig. 2 shows a schematic structural diagram of a semiconductor structure provided by the present disclosure;
fig. 3 illustrates a top view of a semiconductor structure provided by the present disclosure;
FIG. 4 illustrates a cross-sectional view of the semiconductor structure taken along line a in FIG. 3;
fig. 5 shows a flow chart of a method of fabricating a semiconductor structure provided by the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional semiconductor structure. As shown in fig. 1, the semiconductor structure is a structure of a buried channel array transistor (BuriedChannel Array Transistor, BCAT) in a vertical direction, or a recessed channel array transistor (RecessChannel Array Transistor, RCAT) including two gates 110, 120, two sources 130, 140, and a common drain 150. The physical distance between the word lines of the semiconductor structure shown in fig. 1 is small, which results in the RowHammer problem becoming more serious.
In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, a semiconductor memory, and an electronic device, which are described below with reference to the accompanying drawings.
Fig. 2 shows a block diagram of a semiconductor structure provided by the present disclosure. As shown in fig. 2, the semiconductor structure includes: the semiconductor substrate 200, the first gate structure 210, the second gate structure 220.
The semiconductor substrate 200 includes a first active region including a first source region, a first channel, and a first drain region, and a second active region including a second source region, a second channel, and a second drain region. According to one embodiment of the present disclosure, the first drain region and the second drain region are the same region. According to one embodiment of the present disclosure, the first channel and the second channel are the same length.
As shown in fig. 2, the first active region is composed of a source 240 and a drain 250, the second active region is composed of a source 230 and a drain 250, and the first active region and the second active region share the drain 250. The first active region has a gate trench therein, and the first gate structure 210 fills the gate trench of the first active region. The second gate structure 220 is formed over the second active region.
In accordance with one embodiment of the present disclosure, the first gate structure 210 is formed in the conventional BCAT or RCAT manner, and the second gate structure 220 is formed in the conventional planar transistor (Planar Transistor) manner or the protruding transistor (Protrusion Transistor) manner, and the detailed process is not repeated here.
According to the semiconductor structure, the adjacent grid electrodes are arranged above and below the semiconductor substrate, so that word lines are formed above and below the semiconductor substrate in a staggered mode, the physical distance between the word lines is prolonged, and electromagnetic interference between the adjacent word lines is reduced.
Fig. 3 illustrates a top view of a semiconductor structure provided by the present disclosure. Fig. 4 shows a cross-sectional view of the semiconductor structure taken along line a in fig. 3.
With continued reference to fig. 3 and 4, in accordance with one embodiment of the present disclosure, the first gate structure 210 includes a first metal gate 211 and a first gate dielectric layer 212, the first gate dielectric layer 212 being formed on the sidewalls and bottom wall of the gate trench, the first metal gate 211 being filled in the gate trench with the first gate dielectric layer 212. The second gate structure 220 includes a protrusion 221, a gate stack having an inverted U shape and covering the protrusion 221, and sidewalls 222 formed at both sides of the gate stack. The gate stack includes a silicon layer 223, a second gate dielectric layer 224, and a second metal gate 225.
Wherein the protrusion 221 comprises a silicon oxide or silicon nitride material. The first gate dielectric layer 212 and the second gate dielectric layer 224 are gate oxide layers. The first metal gate 211 and the second metal gate 225 comprise metal tungsten. The materials of construction of the above parts may be other materials well known to those skilled in the art.
The semiconductor structure shown in fig. 4 further includes a Bit Line Contact (BLC), a Bit Line (BL), a storage node Contact (Storage Node Contact, SNC), and a storage capacitor on top of the storage node Contact SNC. The first gate structure 210 corresponds to word line WLB and the second gate structure 220 corresponds to word line WLA. The interlayer dielectric (ILD) is an oxide, such as silicon oxide.
The disclosure also provides a method for manufacturing the semiconductor structure, which is used for manufacturing the semiconductor structure in the embodiment. Fig. 5 shows a flowchart of a method for fabricating a semiconductor structure provided by the present disclosure, the method comprising the steps of:
step S101: a semiconductor substrate is provided that includes a first active region and a second active region.
Step S102: a gate trench is formed in the first active region.
Step S103: a first gate structure is formed in the gate trench of the first active region.
Step S104: a second gate structure is formed over the second active region.
Referring to fig. 2, a semiconductor substrate 200 is provided, the semiconductor substrate 200 includes a first active region in which a gate trench is formed, a first gate structure 210 is formed in the gate trench of the first active region, and a second active region over which a second gate structure 220 is formed.
As shown in fig. 2, the first active region is composed of a source 240 and a drain 250, the second active region is composed of a source 230 and a drain 250, and the first active region and the second active region share the drain 250. The first active region has a gate trench therein, and the first gate structure 210 fills the gate trench of the first active region. The second gate structure 220 is formed over the second active region.
In accordance with one embodiment of the present disclosure, the first gate structure 210 is formed in the conventional BCAT or RCAT manner, and the second gate structure 220 is formed in the conventional planar transistor (Planar Transistor) manner or the protruding transistor (Protrusion Transistor) manner, and the detailed process is not repeated here.
Compared with the prior art, the semiconductor structure manufactured by the method has the advantages that the adjacent grid electrodes are arranged above and below the semiconductor substrate, so that word lines are formed above and below the semiconductor substrate in a staggered mode, the physical distance between the word lines is prolonged, and electromagnetic interference between the adjacent word lines is reduced.
The embodiment of the disclosure also provides a semiconductor memory, which includes the semiconductor structure described in the above embodiment, and may be, for example, a memory such as a DRAM.
As shown in fig. 2, the semiconductor structure includes: a semiconductor substrate 200, a first gate structure 210, a second gate structure 220.
The semiconductor substrate 200 includes a first active region including a first source region, a first channel, and a first drain region, and a second active region including a second source region, a second channel, and a second drain region. According to one embodiment of the present disclosure, the first drain region and the second drain region are the same region. According to one embodiment of the present disclosure, the first channel and the second channel are the same length.
As shown in fig. 2, the first active region is composed of a source 240 and a drain 250, the second active region is composed of a source 230 and a drain 250, and the first active region and the second active region share the drain 250. The first active region has a gate trench therein, and the first gate structure 210 fills the gate trench of the first active region. The second gate structure 220 is formed over the second active region.
In accordance with one embodiment of the present disclosure, the first gate structure 210 is formed in the conventional BCAT or RCAT manner, and the second gate structure 220 is formed in the conventional planar transistor (Planar Transistor) manner or the protruding transistor (Protrusion Transistor) manner, and the detailed process is not repeated here.
With continued reference to fig. 3 and 4, in accordance with one embodiment of the present disclosure, the first gate structure 210 includes a first metal gate 211 and a first gate dielectric layer 212, the first gate dielectric layer 212 being formed on the sidewalls and bottom wall of the gate trench, the first metal gate 211 being filled in the gate trench with the first gate dielectric layer 212. The second gate structure 220 includes a protrusion 221, a gate stack having an inverted U shape and covering the protrusion 221, and sidewalls 222 formed at both sides of the gate stack. The gate stack includes a silicon layer 223, a second gate dielectric layer 224, and a second metal gate 225.
Wherein the protrusion 221 comprises a silicon oxide or silicon nitride material. The first gate dielectric layer 212 and the second gate dielectric layer 224 are gate oxide layers. The first metal gate 211 and the second metal gate 225 comprise metal tungsten. The materials of construction of the above parts may be other materials well known to those skilled in the art.
The embodiment of the disclosure also provides an electronic device, which comprises the semiconductor memory in the embodiment. The electronic device can be a smart phone, a computer, a tablet computer, a wearable intelligent device, an artificial intelligent device and a mobile power supply.
According to the electronic device, due to the fact that the adjacent grid electrodes are arranged above and below the semiconductor substrate, word lines are formed above and below the semiconductor substrate in a staggered mode, physical distances among the word lines are far, and electromagnetic interference among the adjacent word lines is reduced.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (9)
1. A semiconductor structure, comprising:
a semiconductor substrate comprising a first active region and a second active region, wherein the first active region is provided with a grid groove;
a first gate structure filled in the gate trench of the first active region;
a second gate structure formed over the second active region;
the first gate structure comprises a first metal gate and a first gate dielectric layer, the first gate dielectric layer is formed on the side wall and the bottom wall of the gate trench, and the first metal gate is filled in the gate trench with the first gate dielectric layer;
the second gate structure includes:
a protruding portion;
a gate stack having an inverted U-shape and covering the protruding portion;
the side walls are formed on two sides of the grid stack;
and word lines corresponding to the first gate structure and the second gate structure are formed above and below the semiconductor substrate in a staggered manner.
2. The semiconductor structure of claim 1, wherein the first active region comprises a first source region, a first channel, and a first drain region, and the second active region comprises a second source region, a second channel, and a second drain region.
3. The semiconductor structure of claim 2, wherein the first drain region and the second drain region are the same region.
4. The semiconductor structure of claim 3, wherein the first channel and the second channel are the same length.
5. The semiconductor structure of claim 1, wherein the gate stack comprises a silicon layer, a second gate dielectric layer, and a second metal gate.
6. The semiconductor structure of claim 1, wherein the protrusion comprises silicon oxide or silicon nitride.
7. A semiconductor memory device, comprising:
the semiconductor structure of any one of claims 1 to 6.
8. An electronic device, comprising:
the semiconductor memory according to claim 7.
9. The electronic device of claim 8, comprising a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power source.
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| CN202010597559.2A CN111883532B (en) | 2020-06-28 | 2020-06-28 | Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment |
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| CN202010597559.2A CN111883532B (en) | 2020-06-28 | 2020-06-28 | Semiconductor structure, manufacturing method thereof, semiconductor memory and electronic equipment |
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| CN111883532A CN111883532A (en) | 2020-11-03 |
| CN111883532B true CN111883532B (en) | 2024-04-05 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104332470A (en) * | 2009-04-21 | 2015-02-04 | 旺宏电子股份有限公司 | Integrated circuit device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010147392A (en) * | 2008-12-22 | 2010-07-01 | Elpida Memory Inc | Semiconductor device and method of manufacturing the same |
| KR20150090674A (en) * | 2014-01-29 | 2015-08-06 | 에스케이하이닉스 주식회사 | Transistor having dual work function bruied gate electrode, method for manufacturing the same and electronic device having the same |
| US10418899B2 (en) * | 2014-04-14 | 2019-09-17 | Alpha And Omega Semiconductor Incorporated | MOSFET switch circuit for slow switching application |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104332470A (en) * | 2009-04-21 | 2015-02-04 | 旺宏电子股份有限公司 | Integrated circuit device |
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