CN113871360A - 集成电路芯片和包括其的半导体封装件 - Google Patents

集成电路芯片和包括其的半导体封装件 Download PDF

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CN113871360A
CN113871360A CN202110728564.7A CN202110728564A CN113871360A CN 113871360 A CN113871360 A CN 113871360A CN 202110728564 A CN202110728564 A CN 202110728564A CN 113871360 A CN113871360 A CN 113871360A
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integrated circuit
circuit chip
power bumps
line
power
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CN202110728564.7A
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金永晙
李运基
郑钟先
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN113871360A publication Critical patent/CN113871360A/zh
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Abstract

提供了集成电路芯片和包括其的半导体封装件。集成电路芯片包括在其上设置标准单元的基板。集成电路芯片包括：多个电力凸块，包括多个第一电力凸块和多个第二电力凸块；第一金属线路，设置在多个第一电力凸块下方并电连接到多个第一电力凸块；第二金属线路，与第一金属线路水平分开，设置在多个第二电力凸块下方，并电连接到多个第二电力凸块。多个第一电力凸块沿着在与集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与集成电路芯片的不同于第一对角线方向的第二对角线方向平行的第二方向上延伸的第二线设置，多个第二电力凸块沿与第一线间隔开并在第一方向上延伸的第三线和沿与第二线间隔开并在第二方向上延伸的第四线设置。

Description

集成电路芯片和包括其的半导体封装件
相关申请的交叉引用
本申请要求于2020年6月30日提交的韩国专利申请No.10-2020-0079970的优先权，其公开内容通过引用全部合并于本文中。
技术领域
本发明涉及集成电路芯片和包括该集成电路芯片的半导体封装件。
背景技术
通常，为了驱动集成电路芯片，需要适当地供应电力并分配电力，并且根据集成电路芯片的尺寸和信号凸块的数目来确定用作集成电路芯片的电源的电力凸块的数目。
如果与芯片尺寸相比，信号凸块的数目不大，则尽管在电力供应和分配方面不存在重大问题，但是可布设在相同芯片尺寸中的电力凸块的数目会随着信号凸块数目增加的趋势而减少。数目减少的电力凸块可能导致电源完整性变差，例如违反IR压降。因此，需要针对电源完整性而优化的凸块布局和再分布(RDL)布线。
发明内容
本发明的各个方面提供了一种通过以鱼骨形的形式布设电力凸块来改善电源完整性的集成电路芯片。
本发明的各个方面还提供了一种通过以鱼骨形的形式布设电力凸块来改善电源完整性的半导体封装件。
然而，本发明的各个方面不限于本文阐述的方面。通过参考下面给出的本发明的详细说明，本发明的上述和其他方面对于本发明所属领域的普通技术人员而言将变得更加明显。
根据一个实施例，一种集成电路芯片，所述集成电路芯片包括在其上设置有标准单元的基板。所述集成电路芯片包括：多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块在所述集成电路芯片的一个表面的中心区域中设置成交错布置，并且以向所述标准单元供电的方式连接；第一金属线路，所述第一金属线路设置在所述多个第一电力凸块下方并电连接至所述多个第一电力凸块，从俯视图看所述第一金属线路的至少一部分与所述多个第一电力凸块交叠；以及第二金属线路，所述第二金属线路与所述第一金属线路水平地分离开，设置在所述多个第二电力凸块下方，并且电连接到所述多个第二电力凸块，从俯视图看所述第二金属线路的至少一部分与所述多个第二电力凸块交叠。所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线，以及所述多个第二电力凸块沿着与所述第一线间隔开并在所述第一方向上延伸的第三线以及沿着与所述第二线间隔开并在所述第二方向上延伸的第四线设置。
根据可以与上述实施例相同或不同的实施例，一种集成电路芯片，所述集成电路芯片包括在其上设置有标准单元的基板。所述集成电路芯片包括：多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块以交错布置设置在所述集成电路芯片的一个表面的中心区域中，并且以向所述标准单元提供电力的方式连接。所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线。所述多个第二电力凸块沿着与所述第一线间隔开并在所述第一方向上延伸的第三线以及与所述第二线间隔开并在所述第二方向上延伸的第四线设置。所述多个第一电力凸块连接到所述集成电路芯片的集成电路，使得当从所述集成电路芯片的外部接收到第一电压时，所述第一电压通过多个第一电力凸块施加到所述集成电路，所述多个第二电力凸块连接到所述集成电路芯片的集成电路，使得当从所述集成电路芯片的外部接收到不同于所述第一电压的第二电压时，所述第二电压通过所述多个第二电力凸块施加到所述集成电路。
根据可以与上述实施例相同或不同的实施例，一种半导体封装件，所述半导体封装件包括：封装基板，包括其上设置有多个外部连接端子的第一表面，以及与所述第一表面相对的第二表面；和集成电路芯片，所述集成电路芯片包括面对所述封装基板的所述第二表面的连接表面，并且包括多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块以交错布置设置在所述连接表面上。所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线。所述多个第二电力凸块沿着不同于所述第一线并且在所述第一方向上延伸的第三线以及沿着不同于第二线并且在所述第二方向上延伸的第四线设置。从俯视图看，所述多个外部连接端子中的至少第一外部连接端子与所述多个第一电力凸块中的一组电力凸块交叠，并且不与所述多个第二电力凸块中的任何电力凸块交叠。
附图说明
通过参考附图详细描述本发明的示例性实施例，本发明的上述和其他方面以及特征将变得更加明显，其中：
图1是用于说明根据本发明的一些实施例的集成电路芯片的俯视图；
图2是沿图1的线A-A'截取的截面图；
图3是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图；
图4是用于说明包括图3的集成电路芯片的半导体封装件的俯视图；
图5是沿图4的线B-B'截取的截面图；
图6是图4的区域R被放大的放大图；
图7是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图；
图8是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图；
图9是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图；
图10是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图；以及
图11是用于说明根据本发明一些其他实施例的集成电路芯片的俯视图。
具体实施方式
在下文中，将参照附图说明根据本发明的技术思想的实施例。在图1至图11的说明中，相同的附图标记用于基本上相同的组件，并且将不提供这些组件的重复说明。同样，贯穿本发明的若干图，相似的附图标记用于相似的组件。
图1是用于说明根据本发明的一些实施例的集成电路芯片的俯视图。图2是沿图1的线A-A'截取的截面图。图1是示出布设在集成电路芯片的一侧(例如，一个表面)上的电力凸块/信号凸块以及布设在这些凸块下方并与其电连接的最上金属线路的图示。
参照图1和图2，集成电路芯片100_1可以包括彼此相对的前侧100a(例如，前表面或前面)和后侧100b(例如，后表面或后面)，并且可以包括基板101、标准单元102、第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115、边缘电力凸块119、第一至第五最上金属线路121至125、电力布线线路主体131、信号布线线路主体132和钝化层150。
集成电路芯片100_1的前侧100a可以包括基板101的一侧，并且可以是集成电路芯片100_1的暴露侧。与前侧100a相对的后侧100b可以包括钝化层150的一侧。第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115以及边缘电力凸块119布设在后侧100b上。后侧100b可以是连接侧(例如，连接表面)，其面对集成电路芯片100_1并且在形成封装体时电连接在集成电路芯片100_1与封装基板之间。在下面将结合对第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115以及边缘电力凸块119的布局的说明，来提供对后侧100b上的区域的具体说明。
基板101可以是体硅或SOI(绝缘体上硅)。或者，基板101可以是硅基板，或者可以包括但不限于其他材料，例如硅锗、SGOI(绝缘体上硅锗)、锑化铟、铅碲化合物、砷化铟、磷化铟、砷化镓或锑化镓。
标准单元102可以布设在基板101上。标准单元102可以是例如但不限于反相器、多路复用器(MUX)、缓冲器、触发器、锁存器和逻辑运算块(例如，AND、OR、XOR和NAND)。
标准单元102可以包括具有10nm、7nm、5nm或更小的沟道长度的一个或更多个晶体管103。然而，沟道长度的前述示例不限制本发明的技术思想。每个晶体管103可以从电力布线线路主体131和信号布线线路主体132中的每个接收电力和信号。
从俯视图来看，第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115以及边缘电力凸块119都可以具有八边形形状，但是形状不限于此，它们可以具有诸如五边形或圆形的形状。
第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115以及边缘电力凸块119可以均包括下凸块金属、柱和焊料。在某些实施例中，第一VDD电力凸块111和第二VDD电力凸块113、信号凸块115以及边缘电力凸块119均包括相同和对应的配置，并且可以用对第一VDD电力凸块111的说明来代替其说明。
第一VDD电力凸块111可以包括第一下凸块金属111_1、第一柱111_2和第一焊料111_3。第一下凸块金属111_1可以包括钛(Ti)、镍(Ni)等。然而，第一下凸块金属111_1不限于上述材料的示例，第一下凸块金属111_1布设在被钝化层150包围的连接焊盘151上，并且对集成电路芯片100_1与第一柱111_2之间的连接进行介导。连接焊盘151可以形成为具有与钝化层150的外表面共面的表面。第一下凸块金属111_1可以具有与连接焊盘151的与钝化层150的外表面共面的表面接触的第一表面和与第一表面相对的第二表面。将理解的是，当元件被称为“连接”或“耦合”到另一元件或“在”另一元件“上”时，其可以直接连接或耦合到另一元件或直接在另一元件上，或者可以存在中间元件。相反，当元件被称为“直接连接”或“直接耦合”到另一元件，或被称为“接触”另一元件或“与”另一元件“接触”时，在接触点处不存在中间元件。
第一柱111_2可以布设在第一下凸块金属111_1的上侧(例如，第二表面)上。因此，集成电路芯片100_1可以通过第一柱111_2电连接到封装基板的焊盘、中介层(interposerlayer)的焊盘或另一芯片的焊盘。
尽管第一柱111_2可以包括锡(Sn)、锡合金(Sn-Bi、Sn-Ag、Sn-Cu、Sn-Ag和Sn-Ag-Cu)、铟(In)、铅(Pb)、锌(Zn)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)、锑(Sb)、铋(Bi)及其组合中的至少一种，但本发明的技术思想不限于此。第一柱111_2可以具有平坦的顶表面和底表面，其中，底表面接触第一下凸块金属111_1的第二表面，顶表面与底表面相对并且接触第一焊料111_3。
由于第一VDD电力凸块111包括第一焊料111_3，所以即使在连接至封装基板时在封装基板的接触面上未形成焊料，也可以将第一柱111_2连接至封装基板的接触面。
根据一些实施例的第一VDD电力凸块111的凸块直径d_bump在44μm至96μm的范围内，并且其同样适用于第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115以及边缘电力凸块119。
第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114可以连接到集成电路芯片100_1内的通过从集成电路芯片100_1的外部接收电力(例如，VDD和VSS)而运行的集成电路的组件。例如，这些组件可以接收从集成电路芯片100_1的外部施加并通过第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114传输的恒定电源电压。因此，第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114连接成向集成电路芯片100_1(例如，向集成电路芯片100_1中的一个或更多个标准单元)提供电力。
第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114布设在集成电路芯片100_1的后侧100b的中心区域CR上。信号凸块115和边缘电力凸块119可以布设在集成电路芯片100_1的后侧100b的除了中心区域CR之外的边缘区域ER中。布设在边缘区域ER上的边缘电力凸块119的数目可以小于布设在边缘区域ER上的信号凸块115的数目。边缘区域ER包围中心区域CR并且包括与集成电路芯片100_1的边缘相邻的凸块。
信号凸块115可以连接到集成电路芯片100_1内的通过从集成电路芯片100_1的外部接收诸如数据、命令和/或地址信号之类的信号而运行的集成电路的组件。例如，这些组件可以接收从集成电路芯片100_1的外部施加的并且通过信号凸块传输的具有交替的高电压和低电压的波形形状的信号。
根据一些实施例的第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114可以以交错布置来布设并且可以以交错形式布设在中心区域CR上。如本文中所使用的，术语“交错布置”用于表示形成第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114的组件之中的彼此最靠近的任何两个组件未布设在沿着第一方向D1或第二方向D2的直线上，而是一个组件相对于另一组件对角地偏移，其中集成电路芯片100_1的一个侧壁在第一方向D1上延伸，集成电路芯片100_1的与所述一个侧壁接触的另一侧壁在第二方向D2上延伸。例如，彼此最靠近的第一VDD电力凸块111和第一VSS电力凸块112未布设在沿着第一方向D1的直线上，而是可以沿着第一对角线方向D4或第二对角线方向D5布设，第一对角线方向D4和第二对角线方向D5是相对于第一方向D1和第二方向D2的对角线方向。根据一些实施例的第一对角线方向D4或第二对角线方向D5的角度可以分别为基于第一方向D1的45°或135°。换句话说，在中心区域CR中，可以将电力凸块布置在沿D1方向延伸的行中，这些行可以在D2方向上彼此相邻。对于两个直接相邻的行，在这两个直接相邻的行之中没有电力凸块与任何其他电力凸块在D2方向上对齐。而是，对于两个相邻的行，电力凸块可以形成Z字形，并且这两行可以具有沿着D1方向交替布置的电力凸块。
凸块节距p_bump是根据一些实施例的彼此相邻的第一VDD电力凸块111与第二VDD电力凸块113之间、第一VSS电力凸块112与第二VSS电力凸块114之间以及信号凸块115与边缘电力凸块119之间的距离，凸块节距p_bump的值可以在90μm至180μm的范围内。
第一VDD电力凸块111可以包括：第一线组L111_1，其被布设为在集成电路芯片100_1的第一对角线方向D4上延伸；第二线组L111_2，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸；和第三线组L111_3，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸。
第二线组L111_2和第三线组L111_3在第二对角线方向D5上彼此平行地延伸，并且在第一线组L111_1中包括的第一VDD电力凸块111的至少一种配置可以布设在第二线组L111_2与第三线组L111_3之间。因此，第一VDD电力凸块111的至少一部分可以包括以鱼骨(fishbone)的形式布设的包括第一线组L111_1至第三线组L111_3的第一鱼骨组FB_111。组FB_111也可以被描述为形成足球上的格子的平面图形状的足球格子组。
第一VSS电力凸块112可以包括：第四线组L112_1，其被布设为在集成电路芯片100_1的第一对角线方向D4上延伸；第五线组L112_2，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸；和第六线组L112_3，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸。诸如“第一”、“第二”、“第三”等的序号可以简单地用作某些元件、步骤等的标签，以将这些元件、步骤彼此区分开。在说明书中未使用“第一”、“第二”等进行描述的术语在权利要求中仍可以被称为“第一”或“第二”。此外，引用特定序号(例如，特定权利要求中的“第一”)的术语可以在其他地方用不同的序号(例如，说明书或另一权利要求中的“第二”)描述。
第五线组L112_2和第六线组L112_3在第二对角线方向D5上彼此平行地延伸，并且在第四线组L112_1中包括的第一VSS电力凸块112的至少一种配置可以布设在第五线组L112_2与第六线组L112_3之间。因此，第一VSS电力凸块112的至少一部分可以包括以鱼骨的形式布设的包括第四线组L112_1至第六线组L112_3的第一VSS鱼骨组FB_112。第二对角线方向D5可以垂直于第一对角线方向D4，但是实施例不限于此，并且第一对角线方向D4可以与第二对角线方向D5交叉，从而以除了90°以外的角度形成鱼骨形状或足球格子形状。
第二VDD电力凸块113和第二VSS电力凸块114可以布设在中心区域CR中，并且与第一VDD电力凸块111和第一VSS电力凸块112一样，第二VDD电力凸块113的至少一部分和第二VSS电力凸块114的至少一部分均可以包括以鱼骨或足球格子的形式布设的第二VDD鱼骨组和第二VSS鱼骨组。如图2所示，在至少一个实施例中，相邻的鱼骨组在鱼骨组的纵向延伸方向上(例如，在方向D4上)彼此交叠。被描述为在特定方向上“纵向”延伸的物体、层或物体或层的一部分具有在特定方向上的长度和垂直于该方向的宽度，其中长度大于宽度。第一线组L111_1和第四线组L112_1可以均包括在诸如D4方向的对角线方向(相对于集成电路芯片100_1的边缘)上延伸的一行电力凸块。这两个组可以称为电力凸块的脊骨或脊骨组。第二线组L111_2、第三线组L111_3、第五线组L112_2和第六线组L112_3均与相应的脊骨组交叉，并且可以均被称为肋骨组。
第一最上金属线路121在中心区域CR内布设在第一VDD电力凸块111下方，并且可以电连接到一个金属体形式的多个第一VDD电力凸块111。例如，与第一VDD电力凸块111组合的第一最上金属线路121可以被认为是单个导电结构或一个金属体。此外，第一最上金属线路121可以具有单个连续金属板的形式。
如在下面将说明的，第一最上金属线路121可以布设在第五_1最上金属线路125_1和第五_2最上金属线路125_2之间，并且可以从中心区域CR延伸到边缘区域ER。此外，第一最上金属线路121可以布设在边缘电力凸块119下方，并且可以电连接到边缘电力凸块119。
第二最上金属线路122可以在中心区域CR内布设在第一VSS电力凸块112下方，并且可以电连接到一个金属体形式的多个第一VSS电力凸块112。例如，与第一VSS电力凸块112组合的第二最上金属线路122可以被认为是单个导电结构或一个金属体。此外，第二最上金属线路122可以具有单个连续金属板的形式。
如下面将说明的，第二最上金属线路122布设在第五_3最上金属线路125_3和第五_4最上金属线路125_4之间，并且可以从中心区域CR延伸到边缘区域ER。尽管未示出，但是第二最上金属线路122可以在边缘区域ER和中心区域CR内布设在电力凸块下方，并且可以电连接至电力凸块。
第三最上金属线路123在中心区域CR内布设在第二VDD电力凸块113下方，并且可以电连接到一个金属体形式的多个第二VDD电力凸块113。例如，与第二VDD电力凸块113组合的第三最上金属线路123可以被认为是单个导电结构或一个金属体。此外，第三最上金属线路123可以具有单个连续金属板的形式。第三最上金属线路123布设在第五最上金属线路125之间，并且可以远离中心区域CR延伸到边缘区域ER。
第四最上金属线路124在中心区域CR内布设在第二VSS电力凸块114下方，并且可以电连接到一个金属体形式的多个第二VSS电力凸块114。例如，与第二VSS电力凸块114结合的第四最上金属线路124可以被认为是单个导电结构或一个金属体。此外，第四最上金属线路124可以具有单个连续金属板的形式。第四最上金属线路124可以布设在第五最上金属线路125之间并且远离中心区域CR延伸到边缘区域ER。
第五最上金属线路125包括第五_1最上金属线路125_1至第五_4最上金属线路125_4，第五_1最上金属线路125_1至第五_4最上金属线路125_4布设在信号凸块115中包括的第一信号凸块115_1至第四信号凸块115_4中的每个信号凸块下方，电连接至信号凸块115，并且可以从信号凸块115向I/O(输入/输出)端子(未示出)延伸。I/O端子(未示出)的形式根据包括集成电路芯片100_1的封装形式(例如，扇入(Fan-in)和扇出(Fan-out))而变化，并且I/O端子的形式不限制本发明的技术思想。
根据一些实施例的第一最上金属线路121至第五最上金属线路125可以基于基板101布设在相同的高度处并且可以彼此分开。例如，它们可以都处于距基板(例如，距基板的表面)相同竖直距离的竖直水平高度处，并且可以以位于它们之间的间隙彼此水平地间隔开，间隙避免不同的最上金属线路121至125之间的电连接。
电力布线线路主体131包括多个电力布线线路层131_L和多个电力布线线路通路131_VIA。沿着第三方向D3堆叠的电力布线线路层131_L的层数可以根据一些实施例而变化，并且层数不限制本发明的技术思想。
电力布线线路主体131布设在标准单元102与第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114中的每个电力凸块之间。根据一个实施例，电力布线线路主体131可以沿着标准单元102与第一VDD电力凸块111和第二VDD电力凸块113以及第一VSS电力凸块112和第二VSS电力凸块114中的每个电力凸块之间的最短路线布设。此外，电力布线线路主体131可以布设为在信号布线线路主体132的信号传输中不受噪声、短路等干扰。
信号布线线路主体132包括多个信号布线线路层132_L和多个信号布线线路通路132_VIA。沿第三方向D3堆叠的布线线路层132_L的层数可以根据一些实施例而变化，并且层数不限制本发明的技术思想。
信号布线线路主体132布设在每个信号凸块115与标准单元102之间，并且根据一个实施例，信号布线线路主体132可以沿着每个信号凸块115与标准单元102之间的最短路线布设。
钝化层150布设在第一最上金属线路121至第五最上金属线路125上，并且钝化层150的一侧可以被包括在集成电路芯片100_1的后侧100b上，并且可以形成集成电路芯片100_1的后表面。
连接焊盘151可以形成在钝化层150中，并且钝化层150可以包括例如氧化物膜或氮化物膜，或可以由例如氧化物膜或氮化物膜形成，但是不限于此。
第一最上金属线路121至第五最上金属线路125以及包括第一VDD电力凸块111和第二VDD电力凸块113、第一VSS电力凸块112和第二VSS电力凸块114、信号凸块115和边缘电力凸块119的凸块可以通过布设在钝化层150中的连接焊盘151电连接。
第一VDD电力凸块111用于将正工作电压VDD施加到可以包括标准单元102的一个或更多个晶体管103的集成电路，并且第一VSS电力凸块112用于将接地(电接地)工作电压VSS施加到可以包括标准单元102的一个或更多个晶体管103的集成电路。因此，第一VDD电力凸块111和第一VSS电力凸块112可以通过第一最上金属线路121和第二最上金属线路122以及电力布线线路主体131向标准单元102供电。
此外，边缘电力凸块119布设在第一最上金属线路121上，并且要施加到第一VDD电力凸块111的正工作电压VDD也可以施加到边缘电力凸块119。可以将相同的正工作电压VDD施加到布设在第一最上金属线路121上的电力凸块。可以将相同的接地工作电压VSS施加到布设在第二最上金属线路122上的电力凸块。
根据一个实施例，可以将不同的正工作电压VDD施加到第一VDD电力凸块111和第二VDD电力凸块113。类似地，可以将不同的接地工作电压VSS施加到第一VSS电力凸块112和第二VSS电力凸块114。
图3是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图3说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图1和图2中所示的集成电路芯片100_1的区别之处。
参照图3，根据一些实施例的第一VDD电力凸块116和第二VDD电力凸块118以及第一VSS电力凸块117可以以交错布置的形式布设并且可以以交错形式布设在中心区域CR上。
第一VDD电力凸块116可以包括：第一线组L116_1，其被布设为在集成电路芯片100_2的第一对角线方向D4上延伸；第二线组L116_2，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸；和第三线组L116_3，其被布设为在集成电路芯片100_1的第二对角线方向D5上延伸。
第一线组L116_1包括第一_a线组L116_1a(也称为第一线子组)和第一_b线组L116_1b(也称为第一线附加子组)，并且第一_a线组L116_1a和第一_b线组L116_1b在第一对角线方向D4上彼此平行延伸并且彼此分开。
第二线组L116_2和第三线组L116_3在第二对角线方向D5上彼此平行延伸，并且第一线组L116_1中包括的第一VDD电力凸块116的至少一个配置可以包括布设在第二线组L116_2与第三线组L116_3之间的第一VDD电力凸块116。因此，至少一些第一VDD电力凸块116可以包括以鱼骨形式布设的包括第一线组L116_1至第三线组L116_3的第一VDD鱼骨组FB_116。
第一VSS电力凸块117可以包括被布设为在集成电路芯片100_2的第一对角线方向D4上延伸的第四线组L117_1、被布设为在集成电路芯片100_1的第二对角线方向D5上延伸的第五线组L117_2和被布设为在集成电路芯片100_1的第二对角线方向D5上延伸的第六线组L117_3。
第四线组L117_1包括第四_a线组L117_1a(也被描述为第四线子组)和第四_b线组L117_1b(也被描述为第四线附加子组)，并且第四_a线组L117_1a和第四_b线组L117_1b在第一对角线方向D4上彼此平行延伸并且彼此分开。
第五线组L117_2和第六线组L117_3在第二对角线方向D5上彼此平行延伸，并且第四线组L117_1中包括的第一VSS电力凸块117的至少一个配置可以包括布设在第五线组L117_2与第六线组L117_3之间的第一VSS电力凸块117。因此，第一VSS电力凸块117的至少一部分可以包括以鱼骨形式形成的包括第四线组L117_1至第六线组L117_3的第一VSS鱼骨组FB_117。
图4是用于说明包括图3的集成电路芯片的半导体封装件的俯视图。图5是沿图4的线B-B'截取的截面图。图6是图4的区域R被放大的放大图。
图4是示出从平面的角度来看布设在集成电路芯片100_2的后侧上的电力凸块和信号凸块以及布设在封装基板201的第一侧201a上的VDD外部连接端子211和VSS外部连接端子221的俯视图。尽管在图4中仅标记并在下面详细描述了一个VDD外部连接端子211和一个VSS外部连接端子221，但是可以看出，每种类型的外部连接端子均有多个。这些外部连接端子用于将半导体封装件200连接到外部电源，以便向半导体封装件200施加电压。
参照图3至图6，半导体封装件200可以包括封装基板201和集成电路芯片100_2。尽管未示出，但是封装件还可包括覆盖封装基板201的顶表面以及集成电路芯片100_2的至少侧表面的模制层或包封层。模制层也可以覆盖集成电路芯片100_2的顶表面。
封装基板201包括彼此相对的第一侧201a(或第一表面)和第二侧201b(或第二表面)，并且可以包括VDD外部连接端子211、VSS外部连接端子221和再分布结构202。
在根据一些实施例的半导体封装件200中，VDD外部连接端子211和VSS外部连接端子221可以包括外部连接焊盘和焊料球，并且VDD外部连接端子211和VSS外部连接端子221的配置可以彼此相同或对应。因此，可以通过对VDD外部连接端子211的说明来代替对VSS外部连接端子221的说明。
VDD外部连接端子211可以包括VDD焊料球211_1和VDD外部连接焊盘211_2，并且VDD外部连接焊盘211_2可以包括诸如锡(Sn)-铝(Al)-铜(Cu)的材料。尽管在附图中将VDD外部连接端子211显示为包括VDD焊料球211_1和VDD外部连接焊盘211_2的多个组件(例如，两个组件)，但是根据不同实施例，VDD外部连接端子211可以为单个集成组件(例如，其中没有明显的界面)或两个以上组件。
VDD外部连接端子211和VSS外部连接端子221用于将半导体封装件200物理地和/或电气地连接至诸如电子设备的主板的外部装置。
在根据一些实施例的半导体封装件200中，VDD外部连接端子211和VSS外部连接端子221可以具有如图4所示的圆形形状，并且可以具有诸如多边形的形状，但不限于此。
考虑到VDD外部连接端子211和VSS外部连接端子221的球直径d_ball在0.2mm至0.6mm的范围内，在半导体封装件200中，如图2中描述的凸块直径d_bump在44μm至96μm的范围内，并且凸块节距p_bump在90μm至180μm的范围内，从平面的角度来看，VDD外部连接端子211和VSS外部连接端子221可以在三个到五个的范围内与电力凸块交叠。
VDD外部连接端子211和VSS外部连接端子221布设在第一侧201a上，并且在根据一些实施例的半导体封装件200中，VDD外部连接端子211和VSS外部连接端子221可以以交错布置布设，也可以以交错形式布设。
在根据一些实施例的半导体封装件200中，从俯视图看，VDD外部连接端子211被布设为沿着第一VDD电力凸块116的第一线组L116_1在第一对角线方向D4上延伸，并且可以与第一线组L116_1交叠。从俯视图看，VSS外部连接端子221被布设为沿着VSS电力凸块117的第四线组L117_1在第一对角线方向D4上延伸，并且可以与第四线组L117_1交叠。
从俯视图看，每个VDD外部连接端子211可以与第一线组L116_1中包括的三个到五个第一VDD电力凸块116交叠，并且不与VSS电力凸块117交叠。根据一个实施例，与一个VDD外部连接端子211交叠的第一VDD电力凸块116可以以菱形布设，即，可以布设四个第一VDD电力凸块116。
从俯视图看，每个VSS外部连接端子221可以与第四线组L117_1中包括的三个到五个第一VSS电力凸块117交叠，并且不与VSS电力凸块117交叠。根据一个实施例，与一个VSS外部连接端子221交叠的第一VSS电力凸块117可以以菱形布设，即，可以布设四个第一VSS电力凸块117。
根据一些实施例的根据半导体封装件200的再分布结构202包括多条再分布线202_L和再分布通路202_VIA。每组再分布线202_1和相邻的再分布通路202_VIA可以被包括在也包括绝缘层的再分布层中。在第三方向D3上堆叠的再分布层的数目可以根据一些实施例而变化，并且再分布层的数目不限制本发明的技术思想。
再分布结构202布设在外部连接端子(例如，VDD外部连接端子211和VSS外部连接端子221)与电力凸块(例如，第一VDD电力凸块116和第一VSS电力凸块117)之间。根据一个实施例，再分布结构202的将每组电力凸块连接到相应的外部连接端子的部分可以沿着电力凸块组与相应的外部连接端子之间的最短路线布设。因此，可以将连接在单个VDD外部连接端子211与第一组3-5个VDD电力凸块116之间的一组再分布线202_L和再分布通路202_VIA形成为具有最短路线(例如，在垂直方向上的直线)，以将每个电力凸块连接到外部连接端子。同样适用于VSS电力凸块117和各个外部连接端子。
因此，当根据一些实施例的半导体封装件200中的与单个VDD外部连接端子211交叠的第一VDD电力凸块116以菱形布设时，四个或更多个再分布结构202可以连接到单个VDD外部连接端子211以在俯视图中交叠。
图7是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图7说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图1和图2所示的集成电路芯片100_1的不同之处。
图7是示出电力凸块和布设在电力凸块下方并在集成电路芯片100_3的中心区域CR和与中心区域CR相邻的区域中电连接的最上金属线路的俯视图。参照图7，集成电路芯片100_3包括沿着中心区域CR的边缘部分布设的第一环形金属线路141。
在根据一些实施例的第一环形金属线路141内，第一最上金属线路121至第五最上金属线路125可以相对于基板101的表面以相同的高度布设。
第一环形金属线路141通过第一环形连接部分141_C连接到第一最上金属线路121和第三最上金属线路123，并且可以与第二最上金属线路122和第四最上金属线路124分开。
第一VDD电力凸块111和第二VDD电力凸块113可以通过第一最上金属线路121和第三最上金属线路123以及第一环形金属线路141电连接。根据实施例，可以将相同的正工作电压VDD施加到第一VDD电力凸块111和第二VDD电力凸块113。
图8是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图8说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图1和图2所示的集成电路芯片100_1的不同之处。
图8是示出电力凸块和布设在电力凸块下方并在集成电路芯片100_4的中心区域CR和与中心区域CR相邻的区域中电连接的最上金属线路的俯视图。参照图8，集成电路芯片100_4包括沿着中心区域CR的边缘部分布设的第二环形金属线路142。
在根据一些实施例的第二环形金属线路142内，第一最上金属线路121至第五最上金属线路125可以相对于基板101的表面以相同的高度布设。
第二环形金属线路142通过第二环形连接部分142_C连接到第二最上金属线路122和第四最上金属线路124，并且可以与第一最上金属线路121和第三最上金属线路123分开。
第一VSS电力凸块112和第二VSS电力凸块114可以通过第二最上金属线路122和第四最上金属线路124以及第二环形金属线路142电连接。根据实施例，可以将相同的接地工作电压VSS施加到第一VSS电力凸块112和第二VSS电力凸块114。
图9是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图9说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图1和图2所示的集成电路芯片100_1的不同之处。
图9是示出电力凸块和布设在电力凸块下方并在集成电路芯片100_5的中心区域CR和与中心区域CR相邻的区域中电连接的最上金属线路的俯视图。参照图9，集成电路芯片100_5包括沿着中心区域CR的边缘部分布设的外部金属线路143。
根据一些实施例，在外部金属线路143的各个部分之间，第一最上金属线路121至第五最上金属线路125可以相对于基板101的表面以相同的高度布设。
外部金属线路143可以包括第一外部金属线路部分143_1和第二外部金属线路部分143_2。
第一外部金属线路部分143_1可以通过第一外部连接部分143_1C连接到第一最上金属线路121和第三最上金属线路123，第二外部金属线路部分143_2可以通过第二外部连接部分143_2C连接到第二最上金属线路122和第四最上金属线路124。
第一VDD电力凸块111和第二VDD电力凸块113可以通过第一最上金属线路121和第三最上金属线路123以及第一外部金属线路部分143_1电连接。根据该实施例，可以将相同的正工作电压VDD施加到第一VDD电力凸块111和第二VDD电力凸块113。
第一VSS电力凸块112和第二VSS电力凸块114可以通过第二最上金属线路122和第四最上金属线路124以及第二外部金属线路部分143_2电连接。根据实施例，可以将相同的接地工作电压VSS施加到第一VSS电力凸块112和第二VSS电力凸块114。
图10是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图10说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图7所示的集成电路芯片100_3的不同之处。
图10是示出电力凸块和布设在电力凸块下方并在集成电路芯片100_6的中心区域CR和与中心区域CR相邻的区域中电连接的最上金属线路的俯视图。
第一VDD电力凸块161和第二VDD电力凸块163以及第一VSS电力凸块162和第二VSS电力凸块164可以以交错布置布设在集成电路芯片100_6的中心区域CR上，并且可以以交错形式布设。
多个第一VDD电力凸块161和多个第二VDD电力凸块163包括在沿第一对角线方向D4平行延伸的同时布设的部分。例如，在多个第一VDD电力凸块161和多个第二VDD电力凸块163中仅包括被布设为在一个方向上对角地延伸而不是在多个方向上对角地延伸的部分。
第一VSS电力凸块162可以布设在第一VDD电力凸块161与第二VDD电力凸块163之间。例如，一组第一VSS电力凸块162可以在一组第一VDD电力凸块161与一组第二VDD电力凸块163之间。
多个第一VSS电力凸块162和多个第二VSS电力凸块164包括在沿第一对角线方向D4平行延伸的同时布设的部分。例如，在多个第一VDD电力凸块161和多个第二VDD电力凸块163中仅包括沿一个方向对角地延伸而不是沿多个方向对角地延伸的部分。
第二VDD电力凸块163可以布设在多个第一VSS电力凸块162与多个第二VSS电力凸块164之间。例如，一组第二VDD电力凸块163可以在一组第一VSS电力凸块162与一组第二VSS电力凸块164之间。
图11是用于说明根据本发明的一些其他实施例的集成电路芯片的俯视图。
在下文中，将参照图11说明根据本发明的一些其他实施例的集成电路芯片。将主要说明与图8所示的集成电路芯片100_4的区别之处。
图11是示出电力凸块和布设在电力凸块下方并在集成电路芯片100_7的中心区域CR和与中心区域CR相邻的区域中电连接的最上金属线路的俯视图。
第一VDD电力凸块161和第二VDD电力凸块163以及第一VSS电力凸块162和第二VSS电力凸块164可以以交错布置布设在集成电路芯片100_7的中心区域CR上，并且可以以交错形式布设。
多个第一VDD电力凸块161和多个第二VDD电力凸块163包括在沿第一对角线方向D4平行延伸的同时布设的部分。例如，在多个第一VDD电力凸块161和多个第二VDD电力凸块163中仅包括被布设为在一个方向上对角地延伸而不是在多个方向上对角地延伸的部分。
第一VSS电力凸块162可以布设在第一VDD电力凸块161与第二VDD电力凸块163之间。
多个第一VSS电力凸块162和多个第二VSS电力凸块164包括在沿第一对角线方向D4平行延伸的同时布设的部分。例如，在多个第一VSS电力凸块162和多个第二VSS电力凸块164中仅包括被布设为在一个方向上对角地延伸而不是在多个方向上对角地延伸的部分。
第二VDD电力凸块163可以布设在多个第一VSS电力凸块162与多个第二VSS电力凸块164之间。
在根据一些实施例的集成电路芯片100_1至100_5中，通过鱼骨形式的电力凸块111和112的布置来增加连接到布设在电力凸块下方的最上金属线路121和122的电力凸块的数目。因此，与在VDD电力凸块111的情况下的VDD压降相比，在VSS电力凸块112的情况下，可以改善VSS反弹(bounce)并改善电源完整性。
在根据一些实施例的集成电路芯片100_1至100_5中，通过鱼骨或足球格子形式的电力凸块111和112的布置来增加在位于电力凸块111和112下方的最上金属线路121和122与标准单元102之间平行布设的电力布线线路主体131的数目。因此，可以改善IR压降并改善功率密度。
在根据一些实施例的集成电路芯片100_3至100_7中，环形金属线路141至143在集成电路芯片的下侧沿着中心区域的边缘部分布设，分开的最上金属线路(121和123、122和124、171和173、172和174)相连接，并且在最上金属线路121至124和171至174与标准单元102之间平行布设的电力布线线路主体131的数目增加。因此，可以改善IR压降并改善功率密度。
在根据一些实施例的包括集成电路芯片100_2的半导体封装件200中，通过鱼骨形或足球格子形式的电力凸块的布置，在施加与布设在封装基板上的外部连接端子211和221相同的工作电压时，交叠的电力凸块116和117的数目增加，以及在最上金属线路126和127与外部连接端子211和221之间平行连接的再分布结构202的数目增加。因此，可以改善IR压降并改善电源完整性。
然而，实施例的效果不限于本文阐述的效果。通过参照权利要求，实施例的上述和其他效果对于本公开所属领域的普通技术人员而言将变得更加明显。

Claims (20)

1.一种集成电路芯片，所述集成电路芯片包括在其上设置有标准单元的基板，所述集成电路芯片包括：
多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块设置成在所述集成电路芯片的一个表面的中心区域中交错布置，并且连接成向所述标准单元供电；
第一金属线路，所述第一金属线路设置在所述多个第一电力凸块下方并电连接到所述多个第一电力凸块，从俯视图看，所述第一金属线路的至少一部分与所述多个第一电力凸块交叠；以及
第二金属线路，所述第二金属线路与所述第一金属线路水平地分开，设置在所述多个第二电力凸块下方，并且电连接到所述多个第二电力凸块，从俯视图看，所述第二金属线路的至少一部分与所述多个第二电力凸块交叠，
其中，所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线，以及
其中，所述多个第二电力凸块沿着与所述第一线间隔开并在所述第一方向上延伸的第三线以及沿着与所述第二线间隔开并在所述第二方向上延伸的第四线设置。
2.根据权利要求1所述的集成电路芯片，其中，所述多个第一电力凸块连接到所述集成电路芯片内的通过从所述多个第一电力凸块接收VDD电压而工作的集成电路，并且所述多个第二电力凸块连接到所述集成电路芯片内的通过从所述多个第二电力凸块接收VSS电压而工作的集成电路。
3.根据权利要求1所述的集成电路芯片，其中，所述多个第一电力凸块包括沿着所述第一线设置的第一线组。
4.根据权利要求3所述的集成电路芯片，其中，所述多个第一电力凸块包括与所述第一线组间隔开并且沿着与所述第一线平行的线设置的附加线组。
5.根据权利要求3所述的集成电路芯片，其中，所述多个第一电力凸块包括沿着所述第二线布置的第二线组和沿着第五线布置的第三线组，所述第五线在所述第一方向上与所述第二线间隔开并沿着所述第二方向延伸，并且
所述多个第二电力凸块包括沿着所述第四线布置的第四线组和沿着第六线布置的第五线组，所述第六线在所述第一方向上与所述第四线间隔开并沿着所述第二方向延伸。
6.根据权利要求1所述的集成电路芯片，所述集成电路芯片还包括：
环形金属线路，所述环形金属线路形成为在俯视图中包围所述中心区域，并且设置成与所述集成电路芯片的所述一个表面相邻；
多个第三电力凸块，所述多个第三电力凸块设置成在所述集成电路芯片的所述一个表面的所述中心区域中与所述多个第一电力凸块和所述多个第二电力凸块一起交错布置；以及
第三金属线路，所述第三金属线路与所述第二金属线路分开，设置成从俯视图看与所述多个第三电力凸块交叠，并且电连接到所述多个第三电力凸块，
其中，所述第一金属线路和所述第三金属线路通过所述环形金属线路彼此连接，并且所述第一电力凸块和所述第三电力凸块彼此电连接。
7.根据权利要求6所述的集成电路芯片，其中，所述第一金属线路、所述第二金属线路和所述第三金属线路以及所述环形金属线路相对于所述基板的表面设置在相同的高度处。
8.根据权利要求1所述的集成电路芯片，所述集成电路芯片还包括：
第一信号凸块和第二信号凸块，所述第一信号凸块和第二信号凸块在除所述中心区域以外的边缘区域中设置在所述集成电路芯片的所述一个表面上，并向所述标准单元提供工作信号；以及
第三金属线路和第四金属线路，所述第三金属线路和第四金属线路分别设置在所述第一信号凸块和所述第二信号凸块下方并分别电连接到所述第一信号凸块和所述第二信号凸块，并且形成为与所述集成电路芯片的所述边缘区域相邻，
其中，所述第一金属线路朝着所述第三金属线路与所述第四金属线路之间的所述边缘区域延伸。
9.根据权利要求8所述的集成电路芯片，其中，所述第一金属线路、所述第三金属线路和所述第四金属线路相对于所述基板的表面设置在相同的高度处，并且
所述第一金属线路、所述第三金属线路和所述第四金属线路彼此水平地分开。
10.一种集成电路芯片，所述集成电路芯片包括其上设置有标准单元的基板，所述集成电路芯片包括：
多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块以交错布置设置在所述集成电路芯片的一个表面的中心区域中，并且连接成向所述标准单元提供电力，
其中，所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线，
其中，所述多个第二电力凸块沿着与所述第一线间隔开并在所述第一方向上延伸的第三线以及与所述第二线间隔开并在所述第二方向上延伸的第四线设置，并且
其中，所述多个第一电力凸块连接到所述集成电路芯片的集成电路，使得当从所述集成电路芯片的外部接收到第一电压时，所述第一电压通过多个第一电力凸块施加到所述集成电路，并且所述多个第二电力凸块连接到所述集成电路芯片的所述集成电路，使得当从所述集成电路芯片的外部接收到不同于所述第一电压的第二电压时，所述第二电压通过所述多个第二电力凸块施加到所述集成电路。
11.根据权利要求10所述的集成电路芯片，所述集成电路芯片还包括：
第一金属线路，所述第一金属线路设置在所述多个第一电力凸块下方并电连接到所述多个第一电力凸块，从俯视图看，所述第一金属线路的至少一部分与所述多个第一电力凸块中的每个电力凸块交叠；以及
第二金属线路，所述第二金属线路与所述第一金属线路水平地分开，设置在所述多个第二电力凸块下方，并电连接到所述多个第二电力凸块，从俯视图看，所述第二金属线路的至少一部分与所述多个第二电力凸块中的每个电力凸块交叠。
12.根据权利要求11所述的集成电路芯片，其中，所述第一金属线路和所述第二金属线路相对于所述基板的表面设置在相同的高度处。
13.根据权利要求10所述的集成电路芯片，其中，所述多个第一电力凸块连接到所述集成电路芯片的通过接收作为所述第一电压的VDD电压而工作的电路组件，并且
所述多个第二电力凸块连接到所述集成电路芯片的通过接收作为所述第二电压的VSS电压而工作的电路组件。
14.根据权利要求10所述的集成电路芯片，所述集成电路芯片还包括：
环形金属线路，所述环形金属线路沿着所述中心区域的边缘部分形成并与所述集成电路芯片的所述一个表面相邻；和
多个第三电力凸块，所述多个第三电力凸块与所述多个第一电力凸块和所述多个第二电力凸块一起以交错布置设置在所述集成电路芯片的所述一个表面的中心区域中，
其中，所述多个第一电力凸块和所述多个第三电力凸块通过所述环形金属线路电连接，以及
所述多个第三电力凸块连接到所述集成电路芯片的通过接收所述第一电压而工作的电路组件。
15.一种半导体封装件，所述半导体封装件包括：
封装基板，所述封装基板包括其上设置有多个外部连接端子的第一表面以及与所述第一表面相对的第二表面；和
集成电路芯片，所述集成电路芯片包括面对所述封装基板的所述第二表面的连接表面，并且包括多个电力凸块，所述多个电力凸块包括多个第一电力凸块和多个第二电力凸块，所述多个电力凸块以交错布置设置在所述连接表面上，
其中，所述多个第一电力凸块沿着在与所述集成电路芯片的第一对角线方向平行的第一方向上延伸的第一线和在与所述集成电路芯片的第二对角线方向平行的第二方向上延伸的第二线设置，所述第二对角线方向不同于所述第一对角线方向，所述第一对角线方向和所述第二对角线方向是相对于所述集成电路芯片的边缘的对角线，
其中，所述多个第二电力凸块沿着不同于所述第一线并且在所述第一方向上延伸的第三线以及沿着不同于第二线并且在所述第二方向上延伸的第四线设置，以及
其中，从俯视图看，所述多个外部连接端子中的至少第一外部连接端子与所述多个第一电力凸块中的一组电力凸块交叠，并且不与所述多个第二电力凸块中的任何电力凸块交叠。
16.根据权利要求15所述的半导体封装件，其中，所述多个第一电力凸块包括：沿着所述第一线布置的第一线组；以及与所述第一线组间隔开并且平行于所述第一线布置的第一线附加组。
17.根据权利要求16所述的半导体封装件，其中，所述多个第一电力凸块中的在俯视图中与所述第一外部连接端子交叠的所述一组电力凸块包括以菱形形状布置的电力凸块。
18.根据权利要求16所述的半导体封装件，其中，在俯视图中，所述第一外部连接端子与所述多个第一电力凸块中的所述一组电力凸块交叠，其中，所述多个第一电力凸块中的所述一组电力凸块包括三个至五个电力凸块。
19.根据权利要求15所述的半导体封装件，其中，所述多个第一电力凸块连接到所述集成电路芯片的通过接收VDD电压而工作的电路组件，并且所述多个第二电力凸块连接到所述集成电路芯片的通过接收VSS电压而工作的电路组件。
20.根据权利要求15所述的半导体封装件，其中，所述多个第一电力凸块连接到所述集成电路芯片的通过接收VSS电压而工作的电路组件，并且所述多个第二电力凸块连接到所述集成电路芯片的通过接收VDD电压而工作的电路组件。
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