CN113823992B - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- CN113823992B CN113823992B CN202111071850.7A CN202111071850A CN113823992B CN 113823992 B CN113823992 B CN 113823992B CN 202111071850 A CN202111071850 A CN 202111071850A CN 113823992 B CN113823992 B CN 113823992B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
Abstract
The invention discloses a semiconductor device manufacturing method, which comprises at least one etching process, wherein the etching process is used for transferring a pattern to an etching target layer formed by a first III-V group semiconductor material by taking a patterned photoresist as a mask and removing the photoresist; the etching process comprises the following steps: forming an isolation layer made of a second III-V semiconductor material on the etching target layer, wherein the second III-V semiconductor material and the first III-V semiconductor material have corrosion selectivity and are in lattice matching; coating photoresist on the isolation layer and patterning the photoresist; taking the patterned photoresist as a mask, and transferring the pattern to the isolation layer and the etching target layer in an etching way; removing at least part of the photoresist; and removing the isolation layer and the residual photoresist on the isolation layer by a selective wet etching process. The invention also discloses a semiconductor device. The invention can realize the complete removal of the photoresist in the etching process, and hardly causes damage to the surface of the etching target layer.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device based on III-V compounds.
Background
Group III-V compounds are compounds of B, al, ga, in of group III of the periodic Table of the elements and N, P, as, sb of group V, and so-called group III-V semiconductors are binary compounds of the above-mentioned group III and group V elements, and have a compositional chemical ratio of 1:1. the III-V group compound semiconductor material has been applied to photoelectronic devices, photoelectric integration, ultra-high-speed microelectronic devices, ultra-high-frequency microwave devices and circuits, and has wide prospects. The group III-V semiconductors currently used in the industry are mainly gallium arsenide (GaAs), indium phosphide (InP) and gallium nitride.
Due to the characteristics of the materials, compared with the traditional Si and Ge semiconductors, the manufacturing process of the semiconductor device based on the III-V group compounds has many differences, for example, the semiconductor device manufactured by using the Si group materials has a mature COMS process, and can be manufactured according to a uniform flow only by designing a required device structure in advance; however, group III-V compound semiconductors are greatly different in terms of dry etching gases and wet etching liquids due to the difference in materials. Common etching gases for gallium arsenide materials, for example, are chlorine, argon, boron trichloride. The common etching gases for the InP material are chlorine, methane and argon, which also include the removal of photoresist in the etching process. In the manufacturing process of semiconductor devices, at least one etching process is often required to etch and form a required pattern on a semiconductor substrate or a layer structure; this process usually uses a patterned photoresist as a mask to etch a substrate or a layer structure according to the design on the mask, and after the etching is finished, the photoresist needs to be stripped from the surface of the wafer for the next process. The existing photoresist removing methods mainly comprise the following types: the first kind of direct photoresist stripping method. That is, when removing the photoresist, an organic solvent (such as acetone) or a special photoresist removing solution is used to remove the photoresist, and this method has two disadvantages, one is that the photoresist removing time is relatively long and water bath heating is required, and the other is that the photoresist removing is often not clean enough, which is the biggest disadvantage of this method. The second type is plasma pre-bombardment. In this method, before dry etching using the photoresist as a mask, plasma bombardment (mainly oxygen ionized plasma) is performed on the photoresist, so that the photoresist and the etching material are not bonded so tightly. Thereby being easier to remove when the photoresist is later removed using an organic solvent. The main disadvantage of this method is that the photoresist cannot be removed cleanly, and only a certain improvement effect can be achieved. The third type is an oxygen glow method. Such methods first use an organic solvent to remove the photoresist. There will be some photoresist residue on the surface of the etched material. The surface of the etched material is then bombarded with O2 in ICP to remove the photoresist. This method can cause damage to the surface of the etched material in the first place, and for some materials that are easily oxidized, can oxidize the etched material, thereby affecting the performance of the device.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the existing photoresist removing process and provide a semiconductor device manufacturing method, which can realize the complete removal of the photoresist in the etching process and hardly cause damage to the surface of an etching target layer.
The invention specifically adopts the following technical scheme to solve the technical problems:
a semiconductor device manufacturing method comprises at least one etching process for transferring a pattern to an etching target layer made of a first III-V semiconductor material by using a patterned photoresist as a mask and removing the photoresist; the etching process comprises the following steps:
forming an isolation layer made of a second III-V semiconductor material on the etching target layer, wherein the second III-V semiconductor material and the first III-V semiconductor material have corrosion selectivity and are in lattice matching;
coating photoresist on the isolation layer and patterning the photoresist;
taking the patterned photoresist as a mask, and transferring the pattern to the isolation layer and the etching target layer in an etching way;
removing at least part of the photoresist;
and removing the isolation layer and the residual photoresist on the isolation layer by a selective wet etching process.
Preferably, the isolation layer is formed on the etch target layer using an epitaxial growth method.
Preferably, the thickness of the isolation layer is 50nm to 150nm.
In one preferred embodiment of the present invention, the first III-V semiconductor material is Al x Ga 1-x As, the second III-V semiconductor material is Al y Ga 1-y As, wherein x is in the range of 0-0.4, and y is in the range of 0.7-1.
Preferably, the selective etching solution used in the selective wet etching process is an HF solution system.
Further preferably, the selective etching solution is a diluted HF solution with a dilution ratio of HF to H 2 O=1：20。
As another preferred embodiment of the present invention, the first III-V semiconductor material is Al x Ga 1-x As, the second III-V semiconductor material is Al y Ga 1-y As, wherein the value range of x is 0.8-1,y and 0-0.2.
Preferably, the selective etching solution used in the selective wet etching process is a mixture of a 50% citric acid solution and a 30% hydrogen peroxide solution in a volume ratio of 1: 1-3: 1.
Further preferably, the selective etching solution is formed by mixing a 50% citric acid solution and a 30% hydrogen peroxide solution according to a volume ratio of 1: 2.
In yet another preferred embodiment of the present invention, the first III-V semiconductor material is InGaAs and the second III-V semiconductor material is InP.
Preferably, the selective etching solution used in the selective wet etching process is: h 3 PO 4 HCl = 3:1-10, or HCl: H 2 O = 5:1-3:1, or HCl: H 3 PO 4 :H 2 O = 3.
Further preferably, the selective etching solution is HCl H 2 O = 3:1.
In still another preferred embodiment of the present invention, the first III-V semiconductor material is InGaAsP, and the second III-V semiconductor material is InP.
Preferably, the selective etching solution used in the selective wet etching process is: HCl is CH 3 Acid solution of COOH =1:1, or HCl: H 2 1 to 1, or H =2 3 PO 4 HBr = 1:1.
Further preferably, the selective etching solution is HCl H 2 O = 1:1.
Based on the technical scheme, the method can also obtain the following steps:
a semiconductor device manufactured using the method of any preceding claim.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the extremely strong selective wet etching characteristic of the III-V semiconductor material system, the isolation layer which has etching selectivity with the etching target layer and is in lattice matching with the etching target layer is arranged between the etching target layer and the photoresist, and then the isolation layer and the photoresist on the isolation layer are removed by utilizing the selective wet etching process after the etching is finished.
Drawings
FIG. 1 is a schematic diagram of a conventional photoresist stripping scheme in a VCSEL chip fabrication process;
FIG. 2 is a schematic diagram of a photoresist stripping scheme of the present invention.
Detailed Description
Aiming at the defects of the existing photoresist removing technology, the solution idea of the invention is that based on the extremely strong selective wet etching characteristic of a III-V semiconductor material system, an isolation layer which has etching selectivity with an etching target layer and is in lattice matching with the etching target layer is arranged between the etching target layer and a photoresist, and then the isolation layer and the photoresist on the isolation layer are removed by using a selective wet etching process after etching is finished, so that the photoresist can be removed in percentage, and the surface of the etching target layer is hardly damaged.
The manufacturing method of the semiconductor device comprises at least one etching process, wherein the etching process is used for transferring a pattern to an etching target layer formed by a first III-V group semiconductor material by taking a patterned photoresist as a mask and removing the photoresist; the etching process comprises the following steps:
forming an isolation layer made of a second III-V semiconductor material on the etching target layer, wherein the second III-V semiconductor material and the first III-V semiconductor material have corrosion selectivity and are in lattice matching;
coating photoresist on the isolation layer and patterning the photoresist;
taking the patterned photoresist as a mask, and transferring the pattern to the isolation layer and the etching target layer in an etching way;
removing at least part of the photoresist;
and removing the isolation layer and the residual photoresist on the isolation layer by a selective wet etching process.
For the public understanding, the technical scheme of the invention is explained in detail by a group of specific embodiments and the accompanying drawings:
example 1:
the semiconductor device in this embodiment is a Vertical-Cavity Surface-Emitting Laser (VCSEL for short). Al used in VCSEL chip x Ga 1-x The DBR layer of As material and GaAs substrate (x value range is 0-0.4), need to etch the smooth, steep, flat step of bottom of sidewall. In order to make the required pattern of the device, photoresist is coated on the epitaxial wafer for photoetching, so that a photoresist mask is formed, as shown in FIG. 1; then, the Al is etched by using the photoresist as a mask x Ga 1-x As and GaAs materials. Due to the long etching time, carbonization of the photoresist is easily caused during the dry etching process. The prior art is the use of oxygen (O) 2 ) Plasma bombardment is performed, and acetone is used for removing the photoresist, and the methods easily cause the residue of the photoresist, generate dirty spots on the surface of a wafer, or damage the surface of a material, thereby affecting the performance of a device.
To solve this problem, the following etching process is adopted in this embodiment:
step 1, manufacturing an isolation layer:
in the process of manufacturing VCSEL chip, al is firstly used x Ga 1-x The As (x ranges from 0 to 0.4) layer generates thinner Al y Ga 1-y The As layer (y ranges from 0.7 to 1) is used As an isolation layer for removing the subsequent photoresist. Al (Al) y Ga 1-y As layer and Al x Ga 1-x As has extremely strong selective corrosion characteristics, and the twoThe lattice matching does not cause adverse effects such as cracking between wafer layers due to stress. The thickness of the isolation layer is preferably 50nm to 150nm, in this embodiment 100nm to 150nm. The formation of the isolation layer can adopt the existing physical vapor deposition method or chemical vapor deposition method, and also can adopt molecular beam epitaxial growth; preferably, the epitaxial growth mode is adopted, and the isolation layer can be obtained by epitaxial growth together with the etching target layer or by secondary epitaxial growth before etching.
Step 2, manufacturing a photoresist mask:
as shown in FIG. 2, in the case of Al having formed the barrier layer x Ga 1-x A photoresist is coated on the As layer and a photoresist mask is made by photolithography.
Step 3, etching the pattern:
etching Al by ICP etcher y Ga 1-y As layer and Al x Ga 1-x As material. Al (aluminum) x Ga 1-x The etch parameters of As need not be changed. This is because: in etching Al x Ga 1-x When As material is used, the used gases are chlorine, boron trichloride and argon, al y Ga 1- y The dry etching property of the As layer is basically the same As that of the materials, and the influence on the original etching process is basically negligible due to the extremely thin thickness.
And 4, removing at least part of the photoresist:
the main purpose of this step is to expose as much of the surface of the isolation layer as possible to accelerate the speed of the subsequent selective wet etching, and it is not necessary to pay attention to the quality of the photoresist removal and whether the surface of the isolation layer will be damaged, so that various existing wet or dry photoresist removal methods can be flexibly adopted according to the actual situation, and the method with the most convenient operation and the lowest implementation cost is preferably selected. In this example, the photoresist is cleaned with an organic solvent such as acetone.
And 5, removing the isolation layer by selective wet etching:
due to the long dry etching process, part of the photoresist is carbonized and difficult to remove, and some non-volatile auxiliary substancesThe product covers the surface of the photoresist, which is difficult to solve by the existing photoresist stripping scheme. The invention removes the isolation layer by a selective wet etching process, in particular to only Al of the isolation layer by selective etching liquid y Ga 1-y As is etched away without etching Al of the target layer x Ga 1-x As has an effect. The selective etching solution used in the selective wet etching process is an HF solution system, including but not limited to: BOE solution, buffered HF (HF: NH) 4 F:H 2 O =3, 6), diluted HF solution (volume ratio to water 1:5-1:30 all), HF (48 w t%)/CrO 3 (33 w t%) (volume ratio is 0.01-0.138) mixing the solution. Wherein, BOE solution and buffered HF (HF: NH) 4 F:H 2 O =3: 5~1: the 15 diluted HF concentration is higher and the corrosion rate is too fast, while HF (48 w t%)/CrO 3 (33 w t%) (the volume ratio is 0.01-0.138), the mixed solution contains chromium, so that the chromium-containing mixed solution has high toxicity and is easy to cause damage to a human body; therefore, 1: the HF solution diluted by 20 has moderate corrosion rate, easy preparation and high selective corrosion.
And (3) carrying out the steps of 1: wet release is carried out for 90s in 20 diluted HF solution, the HF solution is properly stirred, then the corrosive liquid is cleaned by deionized water, then a cotton ball is dipped in acetone to slightly wipe the surface of the epitaxial wafer, the cotton ball is dipped in isopropanol to slightly wipe the surface of the epitaxial wafer, the operation is repeated for a plurality of times, and finally the deionized water is used for cleaning. At this time, the isolation layer is completely removed, and the residual photoresist attached to the isolation layer is also completely removed. The RMS of the final processed etch target layer was 0.2nm, which is substantially the same level as the surface smoothness of the epitaxial growth.
Example 2:
the semiconductor device in this embodiment is a brillouin laser. In a Brillouin laser, al is added to an etching target layer x Ga 1-x As (x ranges from 0.8 to 1), the waveguide width, the etching depth, the side wall smoothness and the surface cleanliness are very high requirements. In order to manufacture the device, photoresist is coated on the epitaxial wafer for photoetching so as to form a photoresist maskFilm, and etching Al with the photoresist as mask x Ga 1-x As (x ranges from 0.8 to 1) to form a waveguide. Al (aluminum) x Ga 1-x As (x ranges from 0.8 to 1) material is easily oxidized if oxygen (O) is used 2 ) Plasma bombardment readily oxidizes the waveguide layer material, greatly increasing the transmission loss of the device and significantly affecting the laser emission spectrum.
The embodiment specifically adopts the following etching process:
step 1, manufacturing an isolation layer:
this example shows etching of the target layer Al x Ga 1-x The isolating layer material selected from As (x ranges from 0.8 to 1) is Al y Ga 1-y As (y ranges from 0 to 0.2). The two materials have extremely strong selective corrosion characteristics, and the two materials are in lattice matching, so that adverse effects of layer-to-layer fracture caused by stress can be avoided. The thickness of the isolation layer is preferably 50nm to 150nm, in this embodiment 100nm to 150nm. The isolation layer can be formed by the existing physical vapor deposition method or chemical vapor deposition method, or by molecular beam epitaxy, preferably by epitaxial growth.
Step 2, manufacturing a photoresist mask:
al in the formed isolation layer x Ga 1-x A photoresist is coated on the As layer and a photoresist mask is made by photolithography.
Step 3, etching patterns:
etching Al by ICP etcher y Ga 1-y As layer and Al x Ga 1-x An As material. Al (Al) x Ga 1-x The etch parameters of As need not be changed. This is because: in etching Al x Ga 1-x When As material is used, the used gases are chlorine, boron trichloride and argon, al y Ga 1- y The dry etching property of the As layer is basically the same As that of the materials, and the influence on the original etching process is basically negligible due to the extremely thin thickness.
And 4, removing at least part of the photoresist:
the main purpose of this step is to expose as much of the surface of the isolation layer as possible to accelerate the speed of the subsequent selective wet etching, and it is not necessary to pay attention to the quality of the photoresist removal and whether the surface of the isolation layer will be damaged, so that various existing wet or dry photoresist removal methods can be flexibly adopted according to the actual situation, and the method with the most convenient operation and the lowest implementation cost is preferably selected. In this example, the photoresist was cleaned with an organic solvent such as acetone.
And 5, removing the isolation layer by selective wet etching:
the selective etching solution selected in this example is: 50 Mixing a% citric acid solution and a 30% hydrogen peroxide solution according to a volume ratio of 1:1 to 3:1 (the 50% citric acid solution is prepared by citric acid monohydrate crystals and deionized water according to a mass ratio of 1:1); the preferred proportion of the corrosive liquid is 1:2, the selective corrosivity of the corrosive liquid is the highest, and the highest selective ratio can reach 116.
And (4) carrying out wet release on the epitaxial wafer subjected to the photoresist removal in the step (4) in a selective corrosive liquid for 90s, properly stirring, cleaning the corrosive liquid by using deionized water, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with acetone, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with isopropanol, circulating for a plurality of times in such a way, and finally cleaning by using deionized water. At this time, the isolation layer is completely removed, and the residual photoresist attached to the isolation layer is also completely removed. The RMS of the final processed etch target layer was 0.2nm, which was substantially the same level as the surface smoothness of the epitaxially grown layer.
Example 3:
the semiconductor device in this embodiment is a 1.1 micron band laser. The light emission peak of the active layer InGaAs material is located in this band. In order to improve the light emission efficiency and lower the threshold, the active layer sometimes needs to be specially designed. In lasers, the smooth, steep sidewalls act as resonator mirrors, so the epitaxial wafer is dry etched. In order to form the required pattern of the device, photoresist is coated on the epitaxial wafer for photoetching, so that a photoresist mask is formed, and then the InGaAs layer is etched by taking the photoresist as the mask. Since the laser needs to have a smooth and clean sidewall, the residual photoresist can cause laser leakage, which results in an increase of laser threshold and a decrease of light emitting efficiency or even failure to generate laser.
The following etching process is specifically adopted in this embodiment:
step 1, manufacturing an isolation layer:
in this embodiment, the isolation layer material selected for the InGaAs etching target layer is InP. The two materials have extremely strong selective corrosion characteristics, and the two materials are in lattice matching, so that adverse effects of layer-to-layer fracture caused by stress are avoided. The thickness of the isolation layer is preferably 50nm to 150nm, in this embodiment 100nm to 150nm. The isolation layer can be formed by the existing physical vapor deposition method or chemical vapor deposition method, or by molecular beam epitaxy, preferably by epitaxial growth.
Step 2, manufacturing a photoresist mask:
a photoresist is coated on the InGaAs layer where the isolation layer is formed, and a photoresist mask is made by photolithography.
Step 3, etching patterns:
and etching the InGaAs layer and the InP layer by using an ICP etching machine. The etch parameters of the InGaAs need not be changed. This is because: when the InGaAs material is etched, the used gases are chlorine, methane and argon, the dry etching property of the InP layer is basically the same as that of the material, and the influence on the original etching process is basically negligible due to the extremely thin thickness.
And 4, removing at least part of the photoresist:
the main purpose of this step is to expose as much of the surface of the isolation layer as possible to accelerate the speed of the subsequent selective wet etching, and it is not necessary to pay attention to the quality of the photoresist removal and whether the surface of the isolation layer will be damaged, so that various existing wet or dry photoresist removal methods can be flexibly adopted according to actual situations, and the method with the most convenient operation and the lowest implementation cost is preferably selected. In this example, the photoresist was cleaned with an organic solvent such as acetone.
And 5, removing the isolation layer by selective wet etching:
the selective etching solution selected in this example is: h 3 PO 4 HCl = 3:1-10, or HCl: H 2 O = 5:1-3:1, or HCl H 3 PO 4 :H 2 O = 3. Preferred is HCl H 2 The acidic solution of O =3:1 has high selectivity to InGaAs/InP, only relates to one acid and has simple proportioning.
And (4) carrying out wet release on the epitaxial wafer subjected to the photoresist removal in the step (4) in a selective corrosive liquid for 90s, properly stirring, cleaning the corrosive liquid by using deionized water, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with acetone, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with isopropanol, circulating for a plurality of times in such a way, and finally cleaning by using deionized water. At this time, the isolation layer is completely removed, and the residual photoresist attached to the isolation layer is also completely removed. The final processed etching target layer has substantially the same surface smoothness level as that of the epitaxially grown etching target layer.
Example 4:
the semiconductor device in this embodiment is a 1.7 micron band laser. The light emission peak of the active layer InGaAsP material is located in the wave band. In order to improve the light emission efficiency and lower the threshold, the active layer sometimes needs to be specially designed. In lasers, the smooth, steep sidewalls act as resonator mirrors, so the epitaxial wafer is dry etched. In order to form the required pattern of the device, photoresist is coated on the epitaxial wafer for photoetching, so that a photoresist mask is formed. The InGaAsP then needs to be etched using the photoresist as a mask. Since the laser needs to have a smooth and clean sidewall, the residual photoresist can cause laser leakage, which results in an increase of laser threshold and a decrease of light emitting efficiency or even failure to generate laser.
The embodiment specifically adopts the following etching process:
step 1, manufacturing an isolation layer:
in this embodiment, the material of the isolation layer selected for the InGaAsP etching target layer is InP. The two materials have extremely strong selective corrosion characteristics, and the two materials are in lattice matching, so that adverse effects of layer-to-layer fracture caused by stress are avoided. The thickness of the isolation layer is preferably 50nm to 150nm, in this embodiment 100nm to 150nm. The isolation layer can be formed by the existing physical vapor deposition method or chemical vapor deposition method, or by molecular beam epitaxy, preferably by epitaxial growth.
Step 2, manufacturing a photoresist mask:
a photoresist is coated on the InGaAsP layer where the isolation layer is formed, and a photoresist mask is made by photolithography.
Step 3, etching the pattern:
and etching the InGaAsP layer and the InP layer by using an ICP etching machine. The etch parameters of the InGaAsP need not be changed. This is because: when the InGaAsP material is etched, the used gases are chlorine, methane and argon, the dry etching property of the InP layer is basically the same as that of the material, and the influence on the original etching process is basically negligible due to the extremely thin thickness.
And 4, removing at least part of the photoresist:
the main purpose of this step is to expose as much of the surface of the isolation layer as possible to accelerate the speed of the subsequent selective wet etching, and it is not necessary to pay attention to the quality of the photoresist removal and whether the surface of the isolation layer will be damaged, so that various existing wet or dry photoresist removal methods can be flexibly adopted according to the actual situation, and the method with the most convenient operation and the lowest implementation cost is preferably selected. In this example, the photoresist was cleaned with an organic solvent such as acetone.
And 5, removing the isolation layer by selective wet etching:
the selective etching solution selected in this example is: HCl is CH 3 Acid solution of COOH =1:1, or HCl: H 2 1 to 1, or H =2 3 PO 4 HBr = 1:1; the preferred corrosive liquid is HCl H2O (1:1), which has high selective corrosivity and simple proportioning compared with H 3 PO 4 HBr (1:1) has low toxicity and high safety factor.
And (4) releasing the epitaxial wafer subjected to photoresist removal in the step (4) in a selective corrosive liquid for 90s in a wet manner, properly stirring, cleaning the corrosive liquid by using deionized water, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with acetone, slightly wiping the surface of the epitaxial wafer by using a cotton ball dipped with isopropanol, circulating for a plurality of times in the way, and finally cleaning by using deionized water. At this time, the isolation layer is completely removed, and the residual photoresist attached to the isolation layer is also completely removed. The final processed etch target layer has substantially the same level of surface smoothness as the epitaxially grown layer.
Claims (16)
1. A semiconductor device manufacturing method comprises at least one etching process for transferring a pattern to an etching target layer made of a first III-V semiconductor material by using a patterned photoresist as a mask and removing the photoresist; the method is characterized in that the etching process comprises the following steps:
forming an isolation layer made of a second III-V semiconductor material on the etching target layer, wherein the second III-V semiconductor material and the first III-V semiconductor material have corrosion selectivity and are in lattice matching;
coating photoresist on the isolation layer and patterning the photoresist;
taking the patterned photoresist as a mask, and etching and transferring the pattern to the isolation layer and the etching target layer;
removing at least part of the photoresist;
and removing the isolation layer and the residual photoresist on the isolation layer by a selective wet etching process.
2. The manufacturing method of a semiconductor device according to claim 1, wherein the isolation layer is formed on the etch target layer using epitaxial growth.
3. The manufacturing method of a semiconductor device according to claim 1, wherein a thickness of the spacer is 50nm to 150nm.
4. The manufacturing method of a semiconductor device according to claim 1,wherein the first III-V semiconductor material is Al x Ga 1-x As, the second III-V semiconductor material is Al y Ga 1-y As, wherein x is in the range of 0-0.4, and y is in the range of 0.7-1.
5. The manufacturing method of a semiconductor device according to claim 4, wherein the selective etching liquid used in the selective wet etching process is an HF solution system.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the selective etching solution is a diluted HF solution having a dilution ratio of HF to H 2 O=1：20。
7. The method for manufacturing a semiconductor device according to claim 1, wherein the first III-V semiconductor material is Al x Ga 1-x As, the second III-V semiconductor material is Al y Ga 1-y As, wherein the value range of x is 0.8-1,y and 0-0.2.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the selective wet etching process uses a selective etching solution in which a 50% citric acid solution and a 30% hydrogen peroxide solution are mixed in a volume ratio of 1:1 to 3: 1.
9. The manufacturing method of a semiconductor device according to claim 8, wherein the selective etching solution is a mixture of a 50% citric acid solution and a 30% hydrogen peroxide solution in a volume ratio of 1: 2.
10. The method of fabricating a semiconductor device according to claim 1, wherein the first III-V semiconductor material is InGaAs and the second III-V semiconductor material is InP.
11. Method for manufacturing a semiconductor device according to claim 10The selective wet etching process is characterized in that the selective etching solution used in the selective wet etching process is as follows: h 3 PO 4 HCl = 3:1-10, or HCl: H 2 O = 5:1-3:1, or HCl: H 3 PO 4 :H 2 O = 3.
12. The method for manufacturing a semiconductor device according to claim 11, wherein the selective etching solution is HCl H 2 O = 3:1.
13. A method of fabricating a semiconductor device according to claim 1, wherein the first III-V semiconductor material is InGaAsP and the second III-V semiconductor material is InP.
14. The manufacturing method of a semiconductor device according to claim 13, wherein the selective etching solution used in the selective wet etching process is: HCl is CH 3 Acid solution of COOH =1:1, or HCl: H 2 1 to 1, or H =2 3 PO 4 HBr = 1:1.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the selective etching solution is HCl H 2 O = 1:1.
16. A semiconductor device manufactured by the method according to any one of claims 1 to 15.
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| EP0450255B1 (en) * | 1990-04-06 | 1994-07-06 | International Business Machines Corporation | Process for forming the ridge structure of a self-aligned semiconductor laser |
| US6551936B2 (en) * | 2000-12-29 | 2003-04-22 | Bookham Technology Plc | Method of etching patterns into epitaxial material |
| US7867913B2 (en) * | 2007-09-28 | 2011-01-11 | Hynix Semiconductor Inc. | Method for fabricating fine pattern in semiconductor device |
| KR20120095411A (en) * | 2009-11-09 | 2012-08-28 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | Etching process for semiconductors |
| TWI403235B (en) * | 2010-07-14 | 2013-07-21 | Taiwan Memory Company | Manufacturing method for a buried circuit structure |
| CN104701145B (en) * | 2013-12-10 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| US9293523B2 (en) * | 2014-06-24 | 2016-03-22 | Applied Materials, Inc. | Method of forming III-V channel |
| CN104282548A (en) * | 2014-09-12 | 2015-01-14 | 电子科技大学 | Etching method for III-V-group compound semiconductor materials |
| CN105668540B (en) * | 2014-11-19 | 2017-11-14 | 清华大学 | A kind of preparation method of nano-wire array |
| CN106257624A (en) * | 2016-08-29 | 2016-12-28 | 北京代尔夫特电子科技有限公司 | A kind of caustic solution of compound semiconductor |
| US9941168B1 (en) * | 2016-09-21 | 2018-04-10 | Korea Institute Of Science And Technology | Method for manufacturing semiconductor device by epitaxial lift-off using plane dependency of III-V compound |
| CN108383078B (en) * | 2018-02-28 | 2019-04-30 | 清华大学 | The preparation method of silicon needle array |
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