JP2007324575A - Etching method of group iii-v nitride semiconductor layer, and manufacturing method of semiconductor device employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel etching method of a group III-V nitride semiconductor layer. <P>SOLUTION: The manufacturing method of the group III-V nitride semiconductor layer has a process of forming a metal fluoride layer containing a bivalent or trivalent metal element as at least one part of an etching mask on a group III-V nitride semiconductor layer; a process of patterning the metal fluoride layer by wet etching; and a process of dry etching the group III-V nitride semiconductor layer using the patterned metal fluoride layer as a mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor etching method and a semiconductor device manufacturing method using the same. In particular, the present invention relates to an electronic device using a GaN-based material such as a light emitting diode (LED), and an etching method suitably used for manufacturing a light emitting device.

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue or ultraviolet LEDs with the illumination application in mind.

  Here, in order to increase the output of the element, that is, to improve the total radiant flux, it is indispensable to increase the size of the element and to ensure the resistance against large input power. In addition, an element that is sufficiently large compared to a normal LED as a point light source exhibits light emission characteristics as a surface light source, and is particularly suitable for illumination applications.

  However, in an element in which the area of a normal small LED is simply increased in a similar manner, the uniformity of the light emission intensity of the entire element cannot generally be obtained. Therefore, it has been proposed to integrate LEDs on the same substrate. For example, JP-A-11-150303 (Patent Document 1) discloses an integrated light-emitting component in which individual LEDs are connected in series as a light-emitting component suitable as a surface light source. Japanese Laid-Open Patent Publication No. 2002-26384 (Patent Document 2) discloses an LED integration method for the purpose of providing an integrated nitride semiconductor light emitting device having a large area and good light emission efficiency. For integration, it is necessary to electrically isolate a pair of pn junctions that are a single light-emitting unit from other light-emitting units, and a technique for forming an effective “groove” in a nitride semiconductor layer is very important. Is important to.

In Japanese Patent Application Laid-Open No. 11-150303 (Patent Document 1), in order to completely electrically separate a pair of pn junctions that are a single light emitting unit between the units, Ni is used until the insulating substrate is exposed. It describes that a GaN layer is etched using a mask (see Patent Document 1, paragraph 0027). Also in Japanese Patent Application Laid-Open No. 2002-26384 (Patent Document 2), in order to separate a pair of pn junction portions which are a single light emitting unit from other light emitting units, an RIE (reactive ion etching) method is used. The SiO ₂ is used as a mask to etch the GaN-based material until it reaches the sapphire substrate, thereby forming separation grooves between the units (see Patent Document 2, FIG. 2, FIG. 3, and paragraph 0038).

However, a metal mask such as Ni used in Patent Document 1, an oxide such as SiO ₂ used in Patent Document 2, and a known nitride mask such as SiN are used as etching masks for GaN-based materials. The etching resistance is insufficient, the selectivity cannot be obtained, and there is a problem in the etching shape control. In addition, as a real problem, in order to etch a thick GaN-based epitaxial layer exceeding several μm with an oxide mask such as SiO ₂ , an extremely thick SiO ₂ mask is required, and there is a problem in productivity. .

  Incidentally, fluoride masks have been proposed in addition to the metal mask, oxide mask and nitride mask.

For example, Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B) Vol. 8, p. 28, 1990 (Non-patent Document 1), a SrF ₂ mask and an AlF were formed by lift-off using a PMMA resist as a mask for forming a separation groove of a GaN-based material, etching an AlGaAs-based material, and performing re-growth. It is described that _three masks are formed and that an AlSrF mask is formed by MBE at room temperature.

Similarly, Japanese Patent Application Laid-Open No. 6-310471 (Patent Document 3) describes that SrF ₂ and AlF ₃ produced by a lift-off method can be used for fine etching of GaAs, InGaAs, and InGaAsP-based materials. ing. Although this document does not describe the conditions for forming an etching mask, the mask patterning method is based on the lift-off method using a resist that can be exposed to electron beams. It is estimated that the film is formed at a temperature of about 100 ° C.

Further, Japanese Patent Laid-Open No. 5-36648 (Patent Document 4) also discloses a technique of etching a GaAs-based material using a metal mask or SrF ₂ mask patterned by a lift-off method. Even in this document, there is no description of the film forming conditions of the SrF ₂ mask, but since the mask patterning is based on the lift-off method, the mask film forming temperature is from room temperature to about 100 ° C. It is estimated that

As described above, metal fluorides have been used as etching masks for III-V group compound semiconductors such as GaAs, but this is used for III-V group nitride semiconductors such as GaN and the metal fluoride layer A method for performing patterning by a method other than the lift-off method has not been known. Further, in the conventional technique using the lift-off method for patterning metal fluoride, there is a problem that the film quality of metal fluoride is limited and the degree of freedom of process conditions is low.
Japanese Patent Laid-Open No. 11-150303 JP 2002-26384 A JP-A-6-310471 JP-A-5-36648 Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B) Vol. 8, p. 28, 1990

  The present invention has been made in view of conventional problems, and an object thereof is to provide a novel etching method for a group III-V nitride semiconductor layer. Further, in the present invention, the degree of freedom of the formation conditions of the etching mask formed when the III-V nitride semiconductor layer is etched is large, and the III-V nitride semiconductor layer etching process is relatively easy. An object is to provide a method for etching a group V nitride semiconductor layer.

  Furthermore, one embodiment of the present invention provides an etching method capable of easily forming a fine structure such as a fine groove (for example, a narrow and deep groove) in a group III-V nitride semiconductor layer that is difficult to etch. The purpose is to do.

  It is a further object of the present invention to provide a method for manufacturing a semiconductor light emitting device having the etching method as one step.

  The present invention relates to the following matters.

1. Forming a metal fluoride layer on at least a part of the etching mask on the III-V nitride semiconductor layer;
Patterning the metal fluoride layer by etching;
And etching the group III-V nitride semiconductor layer using the patterned metal fluoride layer as a mask. A method for etching a group III-V nitride semiconductor layer, comprising:
2. The metal fluoride layer contains a divalent or trivalent metal element;
The patterning process of the metal fluoride layer is performed by wet etching,
2. The method according to 1 above, wherein the step of etching the III-V nitride semiconductor layer is performed by dry etching.
3. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, the method of the second aspect, characterized in that it is selected from CaF ₂ and combinations thereof.
4). 4. The method according to 2 or 3 above, wherein the forming step of the metal fluoride layer is performed by a vacuum deposition method.
5). 5. The method according to any one of the above items 2 to 4, wherein the dry etching is plasma-excited dry etching using a gas species containing at least chlorine atoms.
6). 6. The method according to 5 above, wherein the gas species containing a chlorine atom is selected from the group consisting of Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations of two or more thereof.
7). 7. The method according to 5 or 6 above, wherein plasma excitation during the dry etching is performed by inductively coupled excitation.
8). 8. The method according to any one of 2 to 7 above, wherein the metal fluoride layer is formed at a temperature of 150 ° C. to 480 ° C.
9. A patterning step of the metal fluoride layer,
Forming a patterned photoresist film on the metal fluoride layer by photolithography; and
The sub-process of wet-etching the metal fluoride layer using an etchant containing an acid or alkali using the patterned photoresist film as a mask. Method.
10. 10. The method according to 9 above, wherein the etchant contains hydrochloric acid or hydrofluoric acid.
11. 11. The method according to any one of 2 to 10, further comprising a step of removing the metal fluoride layer with an etchant containing an acid or an alkali after the step of etching the group III-V nitride semiconductor layer.
12 The etching mask formed on the group III-V nitride semiconductor is resistant to an etchant used in the metal fluoride layer and the metal fluoride layer and a layer other than the metal fluoride. 12. The method according to any one of 2 to 11 above, wherein the method has a multilayer structure portion with a second mask layer, and the metal fluoride layer becomes an etching resistant layer at the time of dry etching.
13. 13. The method according to claim 12, wherein the second mask layer is an oxide or nitride layer.
14 14. The method according to claim 12 or 13, wherein the second mask layer is selected from silicon nitride, silicon oxide, and combinations thereof.
15. 15. The method according to any one of 12 to 14, wherein the second mask layer is smaller than the metal fluoride layer.
16. 16. The method according to any one of 12 to 15, wherein the second mask layer covers a metal layer.
17. 17. The method according to any one of 1 to 16, wherein the III-V nitride semiconductor layer is formed with irregularities before the etching mask is formed.
18. A III-V nitride semiconductor layer;
A semiconductor multilayer structure having an etching mask layer including a metal fluoride layer formed at a temperature of 150 ° C. to 480 ° C.
19. 19. The semiconductor laminated structure according to claim 18, wherein the etching mask layer is composed of only the metal fluoride layer.
20. 19. The semiconductor multilayer structure according to claim 18, wherein the etching mask layer has a multilayer structure portion of the metal fluoride layer and an oxide or nitride layer formed in contact with the metal fluoride layer and below the metal fluoride layer.
21. 21. The semiconductor multilayer structure according to any one of 18 to 20, wherein the etching mask layer is patterned.
22. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, the semiconductor multilayer structure according to any one of CaF ₂ and the 18 to 21 characterized in that it is selected from the group consisting of.
23. 18. A method for manufacturing a semiconductor device, comprising a step of forming a groove in a III-V nitride semiconductor layer by the etching method according to any one of 1 to 17 above.
24. 24. A semiconductor device formed by the manufacturing method according to the above item 23.

  ADVANTAGE OF THE INVENTION According to this invention, the novel etching method of a III-V nitride semiconductor layer can be provided. The present invention realizes a seemingly contradictory characteristic that wet etching is relatively easy and dry etching resistance is good by making use of the characteristics of a metal fluoride layer containing a divalent or trivalent metal element. As a result of adopting this process, the degree of freedom in forming the metal fluoride layer is great, and the film quality can be appropriately set according to each process condition such as dry etching and wet etching.

  In particular, according to one embodiment of the present invention, a film-quality layer having high dry etching resistance can be formed, so that the group III-V nitride semiconductor layer can be easily dry etched by a relatively simple process. . Therefore, the present invention is preferably used in a method for manufacturing a semiconductor device having a step of forming a fine structure such as a fine groove (for example, a narrow and deep groove) in a group III-V nitride semiconductor layer.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”. In addition, the expression “numerical value 1 to numerical value 2” is used to mean a numerical value 1 or more and 2 or less.

  Furthermore, in the present invention, “epitaxial growth” includes, in addition to the formation of an epitaxial layer in a so-called crystal growth apparatus, a subsequent activation process of carriers by heat treatment, charged particle treatment, plasma treatment, etc. of the epitaxial layer. And described as epitaxial growth.

[Description of Embodiment of the Present Invention]
As described above, the III-V nitride semiconductor layer etching method of the present invention is a metal containing a divalent or trivalent metal element on at least a part of an etching mask on the III-V nitride semiconductor layer. A step of forming a fluoride layer, a step of patterning the metal fluoride layer by wet etching, and a step of dry-etching the group III-V nitride semiconductor layer using the patterned metal fluoride layer as a mask; Have Hereinafter, the present invention will be described with reference to FIGS.

<III-V Group Nitride Semiconductor Layer>
The material of the group III-V nitride semiconductor layer to be etched is one in which the main component of group V atoms contained in the group III-V compound semiconductor is a nitrogen element. Of the group V atoms, preferably 90% (atomic%) or more are nitrogen atoms, more preferably 95% or more, particularly 98% or more, and most preferably 100% are nitrogen atoms. The higher the nitrogen atom content, the more difficult the etching of the III-V nitride semiconductor layer is. However, in the present invention, an etching mask with high etching resistance is used, so that etching with a high selectivity can be performed. The group III element preferably includes an element selected from In, Ga, Al, B, and combinations of two or more thereof. Specifically, III-V group nitride semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlN, InAlGaN, and InAlBGaN (hereinafter sometimes referred to as GaN-based semiconductors for simplicity) can be given. These may contain elements such as Si and Mg as dopants if necessary.

Further, the method for forming the III-V nitride semiconductor layer is not limited, and the method can be applied to a semiconductor layer formed by any method. Usually, the group III-V nitride semiconductor layer is formed on the substrate, but the substrate may be a group III-V nitride semiconductor layer, or a combination of the substrate and the semiconductor layer formed thereon may be used. It may be a group III-V nitride semiconductor layer. When the present invention is applied to the manufacture of a light emitting device, a III-V nitride semiconductor layer formed on a substrate by a thin film crystal growth technique such as epitaxial growth is preferable. Here, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), plasma assist MBE, PLD (Pulsed
Laser Deposition), PED (Pulsed Electron Deposition), VPE (Vapor Phase Epitaxy), LPE (Liquid
In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth equipment such as the (Phase Epitaxy) method, carrier treatment by subsequent heat treatment, plasma treatment, etc. It is described as thin film crystal growth including activation treatment.

  The III-V nitride semiconductor layer may have a multilayer structure, and when a III-V nitride semiconductor (GaN-based) light emitting device is manufactured using the present invention, thin film crystal growth (typically epitaxial growth). It is desirable to include a buffer layer, a first conductivity type cladding layer, a first conductivity type contact layer, an active layer structure, a second conductivity type cladding layer, a second conductivity type contact layer, and the like.

  In the following description, as shown in FIG. 1, a case where a group III-V nitride semiconductor layer 2 is formed on a substrate 1 will be described as a representative example. However, the layer itself does not exist and the substrate itself is subjected to dry etching. When the target group III-V nitride semiconductor layer is the substrate 1 and the layer 2 are both the group III-V nitride semiconductor layer subject to dry etching, the substrate 1 is not the group III-V nitride semiconductor layer. Although not provided, the present invention can also be applied to the case where the layer 2 is a group III-V nitride semiconductor layer and the substrate 1 and the layer 2 are etched together.

  When the III-V nitride semiconductor layer is formed on the substrate, the substrate is not particularly limited as long as the target semiconductor layer can be formed, and the semiconductor substrate, the ceramic substrate, the insulating substrate, and the conductive material are not limited. A substrate, a transparent substrate, an opaque substrate, and the like can be used. It is preferable to select appropriately considering the target semiconductor device, semiconductor manufacturing process, and the like.

For example, when a light emitting element structure is manufactured, it is desirable that the optical element is approximately transparent to the light emission wavelength of the element. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if absorption exists, the light output is not reduced by 50% or more due to absorption of the substrate. Further, an electrically insulating substrate is preferable for the production of the GaN-based light emitting device. This is because assuming that so-called flip chip mounting is used, even if a solder material or the like adheres to the periphery of the substrate, current injection into the semiconductor light emitting device is not affected. The specific material in this case is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ and MgO, for example, in order to epitaxially grow an InAlGaN-based light emitting material or InAlBGaN-based material thereon. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less It is desirable from the viewpoint of electrical resistance and crystallinity.

  The substrate used in the present invention is preferably not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during epitaxial growth. When the semiconductor layer formed on the off-substrate is an epitaxial layer, the off-substrate has an effect of promoting good crystal growth in the step flow mode. Therefore, the off-substrate is also effective in improving the morphology of the semiconductor layer. Widely used as. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of a GaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As the off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in the GaN-based material formed on sapphire, it is a light emitting point in the active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching or heat treatment in advance in order to produce a group III-V nitride semiconductor layer using a crystal growth technique such as MOCVD or MBE. In addition, it is possible to intentionally make the substrate uneven, thereby preventing the threading transition that occurs at the interface between the epitaxial layer and the substrate from being introduced into the vicinity of the light emitting element or the active layer of the light emitting unit described later. It is. In this case, an etching mask layer is formed on the uneven surface, but in the present invention, a good etching mask layer can be formed also in that case.

  The thickness of the substrate is selected in consideration of the target semiconductor device and the semiconductor process. However, in the initial stage of device fabrication, the thickness is set to, for example, about 250 to 700 μm, and the mechanical strength in the semiconductor device crystal growth and element fabrication process is high. It is usually preferred to ensure that it is secured. It is also preferable to make the III-V nitride semiconductor layer thin during the process by a polishing step in order to facilitate separation into each element after forming the group III-V nitride semiconductor layer by a method such as sputtering, vapor deposition, or epitaxial growth. In a specific embodiment, when a semiconductor element, in particular, a semiconductor light emitting device is finally obtained, it is desirable that the thickness is, for example, about 100 μm or less.

<Deposition of metal fluoride layer>
FIG. 2 shows a state where the etching mask layer 3 is formed on the III-V nitride semiconductor layer 2. The etching mask layer includes at least one metal fluoride layer containing a divalent or trivalent metal element. In order to be compatible with the process of the present invention, this metal fluoride layer has an appropriate (usually large) solubility to an etchant used in the patterning process of the metal fluoride layer, and is used for etching. Before the patterning mask is peeled off or damaged, the portion of the metal fluoride material exposed in the patterning mask opening needs to be etched away within a practical time range. At the same time, the metal fluoride layer needs to have practical etching resistance as compared with the group III-V nitride semiconductor in the dry etching process of the group III-V nitride semiconductor layer. Accordingly, the metal fluoride layer containing a divalent or trivalent metal element is not particularly limited as long as it has physical properties suitable for such a process, and the material and film formation are performed so as to have such physical properties. Conditions are chosen.

The material constituting the metal fluoride layer is a metal element fluoride selected from Group 2 (Group 2A), Group 3 (Group 3A), Group 12 (Group 2B) and Group 13 (Group 3B) of the long periodic table. Compounds are preferred. Specifically, SrF ₂ , CaF ₂ , MgF ₂ , BaF ₂ , AlF _{3 and the} like can be mentioned, and considering the balance between dry etching resistance and wet etching property, SrF ₂ , CaF ₂ and MgF ₂ are preferable. CaF ₂ and SrF ₂ are preferred, and SrF ₂ is most preferred.

There have been proposals for using a metal fluoride such as SrF ₂ as an etching mask. However, the divalent or trivalent metal fluoride described above is effective as an etching mask for a group III-V nitride semiconductor layer. Compatibility with the simple process of the invention has been newly found by the present invention.

  In particular, the metal fluoride layer containing these divalent or trivalent metal elements is preferably formed at a temperature of 150 ° C. or higher. Films formed at 150 ° C. or higher are particularly excellent in adhesion to the base, a dense film is formed, and after patterning by etching, the mask sidewalls are also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask. In the following description, film formation at a temperature of 150 ° C. or higher may be referred to as “high temperature film formation” for short.

  In the patterning by the conventional lift-off method, the photoresist cannot be exposed to a high temperature, so that the metal fluoride layer cannot be formed at a high temperature. However, in the present invention, since the patterning of the metal fluoride layer is performed by wet etching, the setting range of the film formation temperature of the metal fluoride layer is widened. There is also an advantage that high-temperature film formation with excellent linearity of the mask side wall can be adopted after a simple film is formed and simultaneously patterned by etching.

On the other hand, in terms of wet etching at the time of patterning the metal fluoride and removal of the metal fluoride layer, which may be performed after dry etching with a chlorine plasma of a group III-V nitride semiconductor layer described later, the metal fluoride is used. The chemical layer is preferably formed at a temperature of 480 ° C. or lower. In particular, as will be described later, when a mask such as SrF ₂ is exposed to plasma of chlorine or the like during dry etching of the semiconductor layer, the etching rate at the subsequent removal of the mask layer is reduced before exposure to plasma of chlorine or the like. It has a tendency to decrease in comparison. For this reason, the film formation of the metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate for an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride layer, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, in the metal fluoride layer after being exposed to the plasma during the dry etching of the III-V nitride semiconductor layer, the wet etching rate with respect to hydrochloric acid or the like at the time of removal has a property of being reduced to an excessively high temperature. In this case, it becomes difficult to remove the metal fluoride that is no longer necessary after etching the semiconductor layer.

  Furthermore, if metal fluoride film formation is performed at an excessively high temperature, an excessive thermal history is given to the substrate, the semiconductor layer, or the metal layer formed on the group III-V nitride semiconductor layer as described later. When manufacturing a III-V nitride semiconductor light emitting device, etc., the mask manufacturing process may adversely affect the device.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

  Under the etching conditions of the group III-V nitride semiconductor layer, the etching selectivity between the metal fluoride layer and the semiconductor layer is 40 or more, preferably 200 or more, more preferably 400 or more, and this is the group III-V nitride. A physical semiconductor is also possible.

  As a method for forming the metal fluoride layer, a normal film forming method such as a sputtering method, an electron beam evaporation method, or a vacuum evaporation method can be employed. However, an etching mask having a low selectivity may be obtained by a method such as sputtering or electron beam evaporation. This is probably because electrons, ions, and the like directly collide with the fluoride, and depending on the conditions, the fluoride is probably dissociated into metal and fluorine. Therefore, in these film forming methods, it is necessary to select film forming conditions appropriately, and there are cases where manufacturing conditions are limited. On the other hand, for example, the vacuum evaporation method by resistance heating is most desirable because there is no such problem. In addition, even if the evaporation method using an electron beam is not an electron beam directly applied to a fluoride material, if it is an indirect heating in which a crucible containing the material is heated by an electron beam, a resistance heating method is used. Also desirable. When a film is formed by these vapor deposition methods, a metal fluoride layer excellent in dry etching resistance can be easily formed on the group III-V nitride semiconductor layer.

Furthermore, the deposition rate of the metal fluoride layer such as SrF ₂ is preferably in the range of about 0.05 nm / sec to 3 nm / sec, and more preferably about 0.1 nm / sec to 1 nm / sec. A metal fluoride layer formed in this range is more desirable because it is a film having high adhesion to the base and ensuring resistance to plasma.

In the present invention, the etching mask layer may be a single layer film of a metal fluoride layer, a multilayer film thereof, or a multilayer structure with a second mask layer that is not a metal fluoride layer. In the present invention, it is only necessary that the metal fluoride layer is exposed on the surface during dry etching of the III-V nitride semiconductor layer so that the underlying structure can be protected from dry etching. Therefore, another layer may be formed on the group III-V nitride semiconductor layer side in order to protect the semiconductor or a component formed on the semiconductor or for other purposes. In one embodiment of the present invention, for example, as described later, when the metal fluoride layer is finally removed, the second metal layer formed on the surface of the semiconductor layer is not removed. The mask layer is preferably a multilayer film in which a film of SiN _x , SiO _x or the like is formed below the metal fluoride layer. In addition to the second mask layer formed below the metal fluoride layer, a third mask layer or the like may be provided above the metal fluoride layer. These can be appropriately selected according to the purpose.

<Patterning of metal fluoride layer>
In the present invention, the metal fluoride layer is patterned into a desired shape by wet etching.

  The patterning of the etching mask layer including the metal fluoride layer is preferably performed using another mask. For example, as shown in FIG. 3, a resist mask 4 made of a photoresist material is formed on the etching mask layer 3, and the resist mask layer 4 is patterned as shown in FIG. 4 by ordinary photolithography such as exposure and development. To do.

  In the present invention, as shown in FIG. 5, the pattern is transferred by wet etching the etching mask layer 3 including the metal fluoride layer using the patterned resist mask layer 4 as a mask.

As an etchant for wet etching, an acid or alkali is preferably contained, and an aqueous solution containing an acid such as hydrochloric acid, hydrofluoric acid, sulfuric acid, phosphoric acid or nitric acid is preferred. If necessary, an oxidizing agent such as hydrogen peroxide, ethylene glycol And the like containing a diluent (wetting agent, surfactant) and the like. The etchant is selected in consideration of the material of the metal fluoride layer, film formation conditions, and the like, but preferably contains at least hydrochloric acid or hydrofluoric acid. For example, when patterning SrF ₂ , hydrochloric acid is desirable, and CaF ₂ Hydrofluoric acid is desirable for patterning. Etching with alkali is also possible, and in any etching, light irradiation, heating, etc. may be used in combination.

  In this manner, after the patterning of the etching mask layer 3 is completed and the structure of FIG. 5 is formed, the resist mask layer 4 which is usually unnecessary is removed, and a group III-V nitride is formed as shown in FIG. A structure is obtained in which the patterned etching mask layer 3 is formed on the physical semiconductor layer.

<Etching of Group III-V Nitride Semiconductor Layer>
In the etching process of the group III-V nitride semiconductor layer, as shown in FIG. 7, the group III-V nitride semiconductor layer 2 is dry-etched using the etching mask layer 3 as a mask.

In the dry etching method, conditions such as the gas type, bias power, and degree of vacuum can be appropriately selected based on the material, crystallinity, and other properties of the layer 2. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. Chlorine-based plasma generated by these gas species has a large selectivity ratio between a group III-V nitride semiconductor material such as GaN and a metal fluoride material (particularly a material formed at high temperature) during dry etching. Therefore, the III-V nitride semiconductor layer can be etched with little etching of the metal fluoride material. As a result, the III-V nitride semiconductor layer having excellent shape controllability can be etched. During dry etching, the thickness of the metal fluoride layer is hardly reduced, but the characteristics of the film, particularly the resistance during wet etching, change, and the wet etching rate tends to decrease.

Here, the plasma generation method at the time of dry etching may be any of capacitively coupled plasma generation (CCP type), inductively coupled plasma generation (ICP type), plasma generation based on electron cyclotron resonance (ECR type), etc. Such a method can also be applied. However, in the present invention, it is desirable to generate chlorine-based plasma by inductively coupled plasma generation. This is because the plasma density can be increased as compared with other methods, which is advantageous when etching a group III-V nitride semiconductor material or the like. Here, the plasma density during dry etching is preferably 0.05 × 10 ¹¹ (cm ⁻³ ) to 10.0 × 10 ¹¹ (cm ⁻³ ), and more preferably 1 × 10 ¹¹ (cm ³ ). ⁻³ ) to 7.0 × 10 ¹¹ (cm ⁻³ ). And since the metal fluoride layer formed into a high temperature by this invention has high etching tolerance, even if it is the plasma of the high plasma density formed by the inductive coupling system, sufficient tolerance is shown.

For example, when a nitride such as SiN _x or SiO _x , an oxide, or a metal such as Ni is used as a mask, the selection ratio between the group III-V nitride semiconductor layer and the mask is about 5 to 20, but the present invention. With this metal fluoride mask, a selectivity of 100 or more can be realized even for the III-V nitride semiconductor layer. Therefore, according to the method of the present invention, the etching depth can be applied even if it exceeds 1 μm or more, preferably 2 μm or more, more preferably 3 μm or more, most preferably 5 μm or more, and even more than 10 μm. Furthermore, depending on the material and thickness of the metal fluoride mask and the material of the semiconductor layer, when a sufficiently thick SrF ₂ mask is formed and the semiconductor layer is etched, a very thick layer can be etched. . The thickness of the semiconductor layer to be etched is generally 50 mm or less, preferably 35 mm or less, more preferably 5 mm or less, still more preferably 1 mm or less, and most preferably 500 μm or less. When etching an extremely thick semiconductor layer, when etching a GaN substrate having a thickness of about 3 mm to 35 mm using an SrF ₂ mask, a GaN epitaxial layer or the like grown on the substrate is further etched. For example, most of the thickness and the thin film crystal growth layer are etched at the same time. Of course, it is possible to etch only the thin film crystal growth layer of about 7 μm without etching the substrate. At that time, since the selection ratio is large, the width of the groove by etching can be shortened as appropriate. For example, the width can be 100 μm or less, preferably 10 μm or less, and further 3 μm or less. The aspect ratio (depth / width) of the groove depth and the groove opening width can be selected as appropriate. In the case of a III-V nitride semiconductor layer, it can be 0.1 or more, preferably 2 or more. Yes, up to about 50, for example about 30 is possible.

  In addition, the depth for etching the group III-V nitride semiconductor layer in the present invention can be selected as appropriate, and FIG. 7 shows the case where the layer 2 is entirely etched up to the substrate. It is also possible to continuously etch a part of the substrate (which may be a non-semiconductor material such as sapphire) by changing the type of etching gas. It is possible to appropriately select how much or to what layer the III-V nitride semiconductor layer is etched.

  After the etching of the group III-V nitride semiconductor layer shown in FIG. 7 is completed, the etching mask layer may be removed if necessary, or a different process is performed while leaving the etching mask layer. It doesn't matter. In general, it is preferable to remove the etching mask layer.

  FIG. 8 shows the structure after the etching mask layer 3 is removed. The metal fluoride layer constituting the etching mask layer 3 may be removed by any method. For example, the metal fluoride layer may be removed by washing with an etchant containing an acid or alkali. it can. In the patterning process of the metal fluoride layer described above, conditions were selected such that the metal fluoride was easily etched and the semiconductor layer was difficult to etch, but the same conditions as patterning were also adopted in the process of removing the metal fluoride layer. can do.

Accordingly, an etchant for wet etching is preferably an aqueous solution containing an acid such as hydrochloric acid, hydrofluoric acid, sulfuric acid, phosphoric acid, or nitric acid. If necessary, an oxidizing agent such as hydrogen peroxide, a diluent such as ethylene glycol (wetting agent, And surfactants). The material is selected in consideration of the material of the metal fluoride layer and the film formation conditions, but preferably contains at least hydrochloric acid or hydrofluoric acid. For example, when removing SrF ₂ , hydrochloric acid is desirable, and CaF ₂ is removed. For this purpose, hydrofluoric acid is desirable. Further, it can be removed by alkali, and in any etching, light irradiation, heating, or the like may be used in combination as appropriate for promoting the reaction or improving the selectivity.

  In addition, since the metal fluoride layer is used as a mask layer at the time of dry etching of the III-V nitride semiconductor layer, the wet etching rate tends to decrease, that is, the solubility in the etchant tends to decrease. Considering this point, it is preferable to determine each condition of the entire process.

Although the etching mask layer that has become unnecessary is removed as described above, it is also possible to use the etching mask layer as a mask for selective growth, for example, and further form a semiconductor layer without removing the etching mask layer. It is. In particular, when epitaxial growth is performed, a metal fluoride material such as SrF ₂ can be used as a selective growth mask.

[Description of different embodiments]
One particular embodiment of the invention will be described. In this embodiment, as shown in FIG. 9, the etching method of the present invention is such that the group III-V nitride semiconductor layer 2 on the substrate 1 already has a step, and a metal layer is formed on the semiconductor layer. This is an example applied to a structure in which the electrodes 7 and 8 are formed.

For example, when a group III-V nitride semiconductor layer in which a metal layer such as an electrode or wiring is formed of aluminum or the like is etched by the etching method of the present invention, an acid is removed when the metal fluoride is removed after the etching is completed. Alternatively, metal layers such as electrodes and wiring may be eroded and removed by an etchant containing alkali. In such a case, the etching mask layer has a multilayer structure including a metal fluoride layer and a second mask layer other than the metal fluoride, and the surface of the semiconductor layer including the metal layer is a layer other than the metal fluoride. It is preferable to coat with a second mask layer resistant to the etchant. The second mask layer needs to be removed under conditions that do not attack the metal layer. Examples of the second mask layer include oxides such as SiO _x , AlO _x , TiO _x , TaO _x , HfO _x, and ZrO _x , nitrides such as SiN _x , AlN _x , and combinations thereof. These are very preferable because they are resistant to wet etching and can be removed by a dry etching method that does not etch metal or the like at the same time. Particularly preferred are SiN _x and SiO _x because production is relatively easy, and SiN _x is particularly preferred.

FIG. 10 shows etching of a multilayer structure of a non-metal fluoride layer such as SiN _x and a metal fluoride layer on the group III-V nitride semiconductor layer 2 having metal layers (electrodes 7 and 8) from the semiconductor layer side. When the mask layer 9 is formed, and the layer 2 is dry-etched as shown in FIGS. 11 and 12, the metal fluoride layer on the surface functions as a mask. Thereafter, in order to remove the etching mask layer 9, the metal fluoride layer is first removed with acid or alkali. At this time, the second mask layer that is not a metal fluoride such as SiN _x is used as an electrode 7 made of aluminum or the like. , 8 are protected. Next, the non-metal fluoride layer such as SiN _{x is} removed by dry etching without eroding the metal layer, and the structure of FIG. 13 can be obtained.

Note that only a part of the etching mask layer, for example, the upper part of the metal layer (for example, the electrodes 7 and 8) may be formed as a multilayer structure, and the upper part of the part other than the metal layer may be formed as a single layer. Furthermore, the multi-layered etching mask layer can be used in any scene during the manufacture of a semiconductor device, but it is desirable to use it in consideration of the consistency of the entire process.
Therefore, in consideration of process consistency, an example in which etching is performed using an etching mask partially having a multilayer structure will be described. First, FIG. 14 is a view showing a state in which the recess 25 is formed by forming the second etching mask 21 formed of a mask material other than the metal fluoride and etching the semiconductor layer 2 formed on the substrate 1. It is. The second etching mask 21 is formed of SiNx, for example, and masks a region including the metal layer (electrode 7). A region not covered with the second etching mask 21 is etched to form a recess 25. Even if the semiconductor layer 2 is a material that is difficult to etch, such as GaN, if the depth of the recess 25 is shallow, it can be sufficiently etched with a known mask material such as SiNx.
Next, when performing deep etching using the metal fluoride layer as a mask, the metal fluoride mask 22 is formed as shown in FIG. 15 without removing the second etching mask 21. Therefore, the surface of the semiconductor layer on and near the metal layer (electrode 7) has a two-layer structure of a metal fluoride mask and a second etching mask.
Next, as shown in FIG. 16, using the metal fluoride mask 22 as a mask, the semiconductor layer 2 is deeply etched to form a groove 26. As described above, since the metal fluoride layer has high dry etching resistance, deep etching is possible. Next, when the metal fluoride mask 22 is removed by, for example, acid, the second etching mask 21 remains as shown in FIG. For this reason, the metal layer is not eroded when the metal fluoride mask 22 is removed by wet etching. Finally, the second etching mask 21 is removed by a method in which neither the metal layer (electrode 7) nor the semiconductor layer is damaged, and a shallow recess 25 and a deep groove 26 are formed in the semiconductor layer 2 as shown in FIG. The resulting structure is obtained. Such a method can be selected depending on the material of the semiconductor layer, the material of the metal layer, and the like. For example, when the surface of the metal layer is Al or the like, and the semiconductor layer is a GaN layer or the like, When the etching mask is SiNx or the like, it is preferable to perform dry etching such as reactive ion etching using a fluorine-based gas as a reactive gas. As described above, when the semiconductor device manufacturing process includes the first etching process for etching the semiconductor layer shallowly and the second etching process for etching the semiconductor layer deeply, other than metal fluoride as a mask in the first etching process. The second mask is used to form a metal fluoride layer mask layer on the second etching step without removing the mask after the etching, and partially or entirely to have a multilayer structure. The manufacturing method can be simplified while effectively protecting the metal layer.

  Furthermore, in the present invention, the formation of the metal fluoride layer is performed by a vacuum evaporation method, particularly by a method of heating without directly applying charged particles such as electrons and plasma, such as a resistance heating method, to the material. Although it is preferable to suppress the divergence, it is also preferable to apply a multilayer structure similar to the above as the etching mask layer in order to further improve the step coverage, particularly the side wall coverage.

For example, an oxide layer and a nitride layer formed by plasma CVD are excellent in the coverage of the side wall of the stepped substrate. Such layers include oxides such as SiO _x , AlO _x , TiO _x , TaO _x , HfO _x and ZrO _x , nitrides such as SiN _x , AlN _x and combinations thereof. Particularly preferred are SiN _x and SiO _x because production is relatively easy, and SiN _x is particularly preferred.

  Thus, it is preferable that the etching mask layer has a multilayer structure of a metal fluoride layer and a layer other than the metal fluoride layer in terms of both protection of the metal layer and step coverage. In particular, the manufacturing process can be simplified while protecting the metal layer by adopting a partial multiple mask in consideration of process consistency.

  The etching method of the present invention described above can be used in an etching process for forming a groove in a group III-V nitride semiconductor layer in a method for manufacturing a semiconductor device.

  In addition, the semiconductor stacked structure having the III-V nitride semiconductor layer of the present invention and the etching mask layer including the metal fluoride layer formed at a temperature of 150 ° C. to 480 ° C. is a process of the above-described etching method. And is extremely useful as an intermediate member for manufacturing a semiconductor device having a fine structure such as a fine and deep groove.

  The features of the present invention will be described more specifically with reference to the following examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

<Example 1>
SrF ₂ films were vacuum-deposited by a resistance heating method on Si-doped GaN semiconductor layers grown by MOCVD on a sapphire substrate at various different substrate temperatures. The formed SrF ₂ film was examined in detail for patterning characteristics as an etching mask for dry etching of the GaN layer, resistance during dry etching, wet etching characteristics during the subsequent removal process, and the like.

For the patterning of the SrF ₂ film after film formation, wet etching was performed at room temperature using an etchant in which hydrochloric acid (containing 36% hydrogen chloride) and water were mixed at a volume ratio of 1:10 using a resist as a mask. The etching rate, the linearity of the side wall of the formed SrF ₂ film pattern, and the controllability of the absolute value of the opening width were evaluated. Further, dry etching of the Si-doped GaN layer using the SrF ₂ mask patterned as described above was performed using Cl ₂ plasma, and the suitability of the SrF ₂ mask during dry etching was evaluated. Furthermore, etching at room temperature during removal of the Si-doped GaN semiconductor layer from the etchant of hydrochloric acid (containing 36% hydrogen chloride) and water (1:10 by volume) of the SrF ₂ film that has undergone the history of dry etching by chlorine plasma. The rate was also measured.

When forming SrF ₂ , a sample in which a Ti / Al / Au metal and a SiN _x film are further formed on the Si-doped GaN semiconductor layer is set in the same chamber, and the heat history during the formation of the SrF ₂ mask is set. The resistance of the metal electrode part and the change of the surface state were also confirmed. The confirmation of the surface condition of the metal was observed after the SrF ₂ film was removed and the SiN _x film was also removed after the SrF ₂ film was formed.

  Table 1 shows the etching rate measurement and evaluation results.

表１より、１５０℃以上の基板温度で成膜されたＳｒＦ_２膜は、ドライエッチングに使用されるエッチングマスクとして適当であることが明らかである。また、ドライエッチング後にＳｒＦ_２膜を実用的な速度で除去すること、および下層に金属層が存在する場合等を考慮すると、４８０℃以下の基板温度で成膜されたＳｒＦ_２膜が好ましいことが判る。

From Table 1, it is clear that an SrF ₂ film formed at a substrate temperature of 150 ° C. or higher is suitable as an etching mask used for dry etching. In addition, considering that the SrF ₂ film is removed at a practical rate after dry etching and a metal layer is present in the lower layer, an SrF ₂ film formed at a substrate temperature of 480 ° C. or lower is preferable. I understand.

<Example 2>
An embodiment in which an element isolation groove is formed by etching in a group III-V nitride semiconductor layer constituting a semiconductor light emitting device will be described with reference to FIGS.

A c + plane sapphire substrate 1 having a thickness of 430 μm was prepared, and a III-V nitride semiconductor layer 2 was formed thereon as follows. First, an MOCVD method was used to form an undoped GaN layer grown at a low temperature of 10 nm as a first buffer layer, and then an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C. as a second buffer layer. Further, a Si-doped (Si concentration 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer, and Si as the first conductivity type (n-type) contact layer. A doped (Si concentration: 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si doped (Si concentration: 1.5 × 10 ¹⁸ cm) as a first conductivity type (n-type) first cladding layer. ^-3 ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Further, as an active layer structure, an undoped GaN layer formed as a barrier layer with a thickness of 13 nm at 850 ° C. and an undoped In _0.1 Ga _0.9 N formed as a quantum well layer with a thickness of 2 nm at 720 ° C. The layers were alternately formed so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and a Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is formed to a thickness of 0.1 μm as the second conductivity type (p-type) first cladding layer. Formed to a thickness. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as a second conductivity type (p-type) contact layer.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, epitaxial growth was completed, and the structure up to the formation of the III-V group nitride semiconductor layer in FIG. 1 was produced.

Next, as shown in FIG. 2, a single layer of SrF ₂ was formed as an etching mask layer 3 at 450 ° C. at a deposition rate of 0.2 nm / sec by vacuum deposition at 450 nm. Next, as shown in FIG. 3, a resist mask layer 4 was formed by spin coating, and then a resist pattern was formed by photolithography. Next, in order to pattern the etching mask layer 3 (SrF ₂ single layer) using the resist pattern 4, hydrochloric acid (containing 36% hydrogen chloride) and water are immersed in an etchant having a volume ratio of 1:10 for 240 seconds, and SrF ₂ The layer was etched as in FIG. The etched SrF ₂ layer was excellent in linearity, did not cause unintended peeling, and maintained high adhesion. Next, the resist layer was removed by acetone and oxygen plasma ashing as shown in FIG. 6 to expose the etching mask of the SrF ₂ layer on the surface. Next, all the semiconductor epitaxial layers corresponding to the trenches for separating the elements were etched using inductively coupled chlorine plasma as shown in FIG. During the dry etching process, the SrF ₂ layer was hardly etched even though the GaN-based material having a thickness of more than 3.8 μm (average 3.868 μm) was dry-etched. Finally, as shown in FIG. 8, it is immersed in an etchant having a deposition ratio of hydrochloric acid and water of 1:10 for 300 seconds to completely remove the unnecessary SrF ₂ layer, and a groove for separation between elements of the semiconductor light emitting device. Completed the formation. The width of the manufactured groove for element separation was 100 μm.

<Example 3>
Different embodiments will be described with reference to FIG. 1 and FIGS. A c + plane sapphire substrate 1 having a thickness of 430 μm was prepared, and a group III-V nitride semiconductor layer 2 was formed thereon as follows. First, an MOCVD method was used to form an undoped GaN layer grown at a low temperature of 20 nm as the first buffer layer, and then an undoped GaN layer of 1 μm thickness was formed at 1040 ° C. as the second buffer layer 2. Continuously, 2 μm of a Si-doped (Si concentration 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed as the first conductivity type (n-type) second cladding layer, and Si as the first conductivity type (n-type) contact layer. A doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si doped (Si concentration 1.5 × 10 10) as a first conductivity type (n-type) first cladding layer. ^{An 18} cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Further, as the active layer structure, an undoped GaN layer formed at 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed at 2 nm at 715 ° C. as a quantum well layer, a quantum well layer Were formed alternately so that there were 3 layers in total and both sides would be barrier layers. Further, the growth temperature is set to 1025 ° C., and a Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is formed to a thickness of 0.1 μm as the second conductivity type (p-type) first cladding layer. Formed to a thickness. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as a second conductivity type (p-type) contact layer.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the epitaxial growth was completed (structure of FIG. 1).

In order to perform the first etching process for exposing the first conductivity type (n-type) contact layer, the etching mask was formed on the semiconductor laminated structure after the epitaxial growth. Here, the SrF ₂ layer was formed on the entire surface of the group III-V nitride semiconductor layer using a vacuum deposition method at a substrate temperature of 200 ° C. and a deposition rate of 0.5 nm / sec. Then by a photolithographic Gufi step, a photoresist pattern is formed SrF ₂ layer on and patterned to partially etch the SrF ₂ layer with hydrochloric acid, to prepare a mask for the first etching. Then, as a first etching step, a p-GaN contact layer, a p-GaN second cladding layer, a p-AlGaN first cladding layer, an active layer structure comprising an InGaN quantum well layer and a GaN barrier layer, and an n-AlGaN first cladding layer Etching by inductively coupled plasma using BCl ₃ gas was performed partway through the n-GaN contact layer to expose the n-type contact layer serving as an n-type carrier injection portion.

After the plasma etching by inductively coupled plasma was completed, the SrF ₂ mask layer was completely removed with hydrochloric acid. Here, the SrF ₂ mask formed at a substrate temperature of 200 ° C. is formed with a mask with excellent linearity during patterning, and is hardly etched even by plasma etching, and has good etching resistance to chlorine-based plasma. Met.

  Next, in order to pattern the p-side electrode 7 by the lift-off method on the formed step, a resist pattern was formed by a photolithography method. As the metal layer A for forming the p-side electrode 7, Pd 20 nm and Au 1000 nm were laminated by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, the p-side electrode was completed by heat treatment (formation of the p-side electrode 7 in FIG. 9). Thus, since the p-side electrode 7 was formed without being exposed to a plasma process or the like, the p-side current injection region was not damaged.

  Then, in order to further pattern the n-side electrode 8 by a lift-off method, a resist pattern was formed by a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as a metal layer for forming the n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode 8 (formation of the n-side electrode 8 in FIG. 9).

  The structure up to FIG. 9 was formed by the steps up to here.

Subsequently, in order to form the etching mask layer 9 as a multilayer film of a SiN _x film and a SrF ₂ film, first, a 200 nm SiN _x film was formed using a p-CVD method at a film forming temperature of 400 ° C. Then, at a high temperature of 400 ° C., to form the SrF ₂ layer mask to a thickness of 400 nm. At this time, the SrF ₂ mask was formed while revolving the dome on which the sample was mounted at a deposition rate of 0.5 nm / sec, and the shape of FIG. 10 was obtained.

Further, in order to separate the light emitting units, a photoresist pattern having an opening in a separation groove forming portion is formed by using a photolithography method, and an etching mask having a laminated structure of SrF ₂ and SiN _x is formed using this resist mask. Layer 9 was wet etched to form openings 10. Etching of the SrF ₂ layer was carried out selectively using an etchant mixed at a volume ratio of hydrochloric acid (containing 36% hydrogen chloride): water = 1: 10 for 240 seconds, followed by etching of the SiN _x layer, Etching was selectively performed for 3 minutes using an etchant having a volume ratio of 1: 5 for hydrofluoric acid and ammonium fluoride. At this time, a patterned etching mask layer excellent in linearity and adhesion was obtained in both the SrF ₂ part and the SiN _x part (FIG. 11).

Next, in the structure of FIG. 11, the III-V nitride semiconductor layer 2 is dry-etched from the opening 10 of the etching mask layer 9 by inductively coupled plasma excitation using Cl ₂ gas, so that the separation groove 11 is formed. Formed. During the etching, the multilayer mask used as an etching mask was hardly etched (FIG. 12).

Finally, all SrF ₂ parts were removed by soaking in hydrochloric acid for 5 minutes. At this time, the SiN _x mask portion was not etched at all. Therefore, the electrode layer was not attacked by hydrochloric acid. Then, in order to remove the unnecessary SiN _x mask, reactive etching using SF ₆ gas was performed for 1 minute, and the SiN _x mask was removed to obtain the shape of FIG.

  Next, the elements were cut out along the separation grooves between the formed elements, and the light emitting device was completed.

It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining 1 embodiment which applied the etching method of this invention to the III-V nitride semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 embodiment which applied the etching method of this invention to the III-V nitride semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 embodiment which applied the etching method of this invention to the III-V nitride semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 embodiment which applied the etching method of this invention to the III-V nitride semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 embodiment which applied the etching method of this invention to the III-V group nitride semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 III-V nitride semiconductor layer 3 Etching mask layer 4 Resist mask layer 7 Electrode 8 Electrode 9 Etching mask layer 10 Opening 11 Groove 21 Second etching mask (SiNx, etc.)
22 Metal fluoride mask 25 Recess 26 Groove

Claims (24)

Forming a metal fluoride layer on at least a part of the etching mask on the III-V nitride semiconductor layer;
Patterning the metal fluoride layer by etching;
And etching the group III-V nitride semiconductor layer using the patterned metal fluoride layer as a mask. A method for etching a group III-V nitride semiconductor layer, comprising: The metal fluoride layer contains a divalent or trivalent metal element;
The patterning process of the metal fluoride layer is performed by wet etching,
The method according to claim 1, wherein the etching process of the group III-V nitride semiconductor layer is performed by dry etching. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and a method according to claim 2, wherein the selected from the group consisting of.   4. The method according to claim 2, wherein the forming step of the metal fluoride layer is performed by a vacuum deposition method.   The method according to claim 2, wherein the dry etching is plasma-excited dry etching using a gas species containing at least chlorine atoms. The gas species containing chlorine _{atoms, Cl 2, BCl 3, SiCl} 4, CCl 4 and a method according to claim 5, wherein the selected from the group consisting of combinations of two or more thereof.   7. The method according to claim 5, wherein plasma excitation during the dry etching is performed by inductively coupled excitation.   The method according to claim 2, wherein the metal fluoride layer is formed at a temperature of 150 ° C. to 480 ° C. A patterning step of the metal fluoride layer,
Forming a patterned photoresist film on the metal fluoride layer by photolithography; and
9. A sub-process of wet-etching the metal fluoride layer using an etchant containing an acid or alkali using the patterned photoresist film as a mask. the method of.   The method according to claim 9, wherein the etchant contains hydrochloric acid or hydrofluoric acid.   The method according to claim 2, further comprising a step of removing the metal fluoride layer with an etchant containing an acid or an alkali after the step of etching the group III-V nitride semiconductor layer.   The etching mask formed on the group III-V nitride semiconductor is resistant to an etchant used in the metal fluoride layer and the metal fluoride layer and a layer other than the metal fluoride. 12. The method according to claim 2, further comprising a multilayer structure portion with a second mask layer, wherein the metal fluoride layer becomes an etching-resistant layer during dry etching.   The method of claim 12, wherein the second mask layer is an oxide or nitride layer.   14. The method of claim 12 or 13, wherein the second mask layer is selected from silicon nitride, silicon oxide, and combinations thereof.   15. A method according to any one of claims 12 to 14, wherein the second mask layer is smaller than the metal fluoride layer.   The method according to claim 12, wherein the second mask layer covers a metal layer.   The method according to claim 1, wherein the III-V nitride semiconductor layer is formed with irregularities before the etching mask is formed. A III-V nitride semiconductor layer;
A semiconductor multilayer structure having an etching mask layer including a metal fluoride layer formed at a temperature of 150 ° C. to 480 ° C.   The semiconductor stacked structure according to claim 18, wherein the etching mask layer is composed of only the metal fluoride layer.   19. The semiconductor multilayer structure according to claim 18, wherein the etching mask layer has a multilayer structure portion of the metal fluoride layer and an oxide or nitride layer formed below and in contact with the metal fluoride layer.   21. The semiconductor multilayer structure according to claim 18, wherein the etching mask layer is patterned. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and the semiconductor stacked structure according to any one of claims 18 to 21, characterized in that it is selected from the group consisting of .   A method for manufacturing a semiconductor device, comprising a step of forming a groove in a group III-V nitride semiconductor layer by the etching method according to claim 1.   A semiconductor device formed by the manufacturing method according to claim 23.

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