JP2007324585A - Semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element of flip-chip mount type which can emit blue or ultraviolet light and has a high output and high efficiency. <P>SOLUTION: The semiconductor compound light-emitting element has a thin-film crystal layer, a second conductivity-type side electrode 27 and a first conductivity-type-side electrode 28, wherein a main light take-out direction is from a buffer layer side viewed from an active layer structure. The electrodes 28 and 27 do not have spatial superposition with each other, and are formed on the opposite side to the light take-out direction, and a supporter connected to the electrodes 28, 27 and supporting the light-emitting device is provided. Further, the light-emitting device has an insulating layer, i. e. an insulating layer (a) contacting one part of the main light take-out direction side of the first conductivity-type-side electrode and covering one part of the opposite side to that of the main light take-out direction of the second conductivity-type-side electrode, and (b) covering the side wall surfaces of the first conductivity-type semiconductor layer, the active layer and the second conductivity-type semiconductor layer, out of the side wall of the thin-film crystal layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a compound semiconductor light emitting device, and more particularly to a light emitting diode (LED) using a GaN-based material. Note that in this specification, the expression “light-emitting diode or LED” is used as a term including a general light-emitting element including a laser diode, a superluminescent diode, and the like.

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue or ultraviolet LEDs with the illumination application in mind.

  In order to increase the output of the element, that is, to improve the total radiant flux, it is indispensable to increase the size of the element and to secure the resistance against a large input power. A flip chip mount structure is known as an effective structure for increasing the output and efficiency of LEDs. In this structure, a predetermined semiconductor layer is deposited on a sapphire substrate, an n-side electrode and a p-side electrode for current injection are formed on the opposite side of the substrate, and the substrate side is the main light extraction direction. For this reason, since the light emitted from the light emitting element is not blocked and the electrode can be used as a light reflecting surface, the light extraction efficiency is improved.

  However, since a pair of electrodes on the p-side and n-side are formed on the same side in the flip-chip structure, when the element is mounted on the support (wiring, heat dissipation substrate) by soldering, p It is necessary to consider so that a short circuit between the side electrode and the n-side electrode and a short circuit between the electrode and the p-type semiconductor layer or the n-type semiconductor layer do not occur. For this reason, various insulation ensuring structures have been proposed.

Japanese Patent No. 3453238 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2001-127348 (Patent Document 2) describe an insulating substrate surface, an n-type nitride semiconductor layer surface, and a p-side nitride semiconductor layer surface. In addition, an element is disclosed in which an insulating coating continuous from the end face of the n-type nitride semiconductor layer to the electrode-side surface is formed. The element structure of Patent Document 1 is shown in FIGS. In order to manufacture this structure, first, an n-type nitride semiconductor layer 102 and a p-type nitride semiconductor layer 103 are sequentially grown on a sapphire substrate 101, and the end portions of the n-type layer 102 and the p-type layer 103 are formed by RIE. Using this method, dry etching is performed to remove the surface of the sapphire substrate 101 so as to have a shape as shown in FIG. Subsequently, part of the p-type layer 103 and the n-type layer 102 is dry-etched using the RIE method to expose the n-type layer 102 so as to have a shape as shown in FIG. After etching, a negative electrode (n-side electrode) 104 is formed on the n-type layer 102 surface, and a positive electrode (p-side electrode) 105 is formed on the p-type layer 103 surface. An insulating film 106 made of SiO ₂ is formed so as to cover the end face of the n-type layer 102 removed by etching and the surface on the electrode side, thereby completing the light emitting element of FIG. At this time, the exposed surfaces of the negative electrode 104 and the positive electrode 105 are exposed so as to be bonded. And the mounting structure shown in FIG.17 (b) is obtained by connecting the negative electrode 104 and the positive electrode 105 to the conductive part 111 on the wiring board 110 via the conductive adhesive 107.

In this structure, since the semiconductor end face is covered with an insulating material, an effect is seen in preventing an electrical short circuit, but the electrode material is likely to deteriorate when an insulating layer (insulating film) is formed. There's a problem. In the p-side electrode, since Au is often used as a layer exposed on the surface, the influence of deterioration is small. In particular, the n-side electrode has high reflectivity and is easily ohmic with an n-type GaN-based material. Since a material containing Al or the like is often used as a material that can realize contact, it is easily affected by the film formation process of the insulating layer. The insulating film is formed of SiO ₂ , TiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ or the like by vapor deposition, sputtering, CVD, etc. In any case, a part of the n-side electrode material is Even if the exposed part is properly covered with a mask material, the entire material is subject to the effects of oxidation, nitridation, etc., and the electrode material deteriorates when trying to inject a large current for high output operation of the device. There is a concern that the influence of the above will become noticeable and eventually cause deterioration of the element. Furthermore, if the exposed portion of the electrode is formed by etching after the insulating layer is formed, the exposed portion itself is affected by the etching process, and in some cases, the electrode material itself may be etched. For example, Al is easily etched with an etchant capable of etching an insulating film such as HF.

  Therefore, the structures described in Patent Documents 1 and 2 cannot be said to be a structure that takes into account the process history that should be taken into account when the element is operated at a high output and the damage to the element constituent material due to the process history. It is an unsuitable structure. This problem is exactly the same in the element of Patent Document 2.

  Further, in the structure of Patent Document 1, since the insulating film is formed on the side wall of the n-side nitride semiconductor layer and the entire surface of the peripheral portion of the element of the substrate, the wafer process is completed, and then each of the LED elements There is a problem that the insulating layer is likely to be peeled off in a scribing process using diamond for separation (scratching for elements) or a scribing process using a high-power laser. The peeling of the insulating layer causes a short circuit at the time of mounting, and as a result, the yield of device manufacturing decreases. The element of Patent Document 2 has the same structural problem as that of Patent Document 1.

  In addition, for small LED elements, Japanese Patent Application Laid-Open No. 2003-17757 (Patent Document 3) discloses a flip chip type element structure (see FIG. 18) mainly for increasing the area of the p-side electrode and the n-side electrode. Proposed. In order to manufacture this flip chip type light emitting device, first, the n-type layer 202 is grown on the sapphire substrate 201 by vapor phase growth or vapor deposition, and the p-type layer 203 is grown thereon. Subsequently, after removing a part of the outer peripheral portion of the p-type layer 203 by etching or the like, a first connection layer (a part of an electrode) 206 is formed around the n-type layer 202 and on the p-type layer 203. A second connection layer (a part of the electrode) 207 is formed by vapor deposition or the like. After that, an insulating layer 208 such as an oxide film is grown to cover the whole, and unnecessary portions of the insulating layer 208 are removed by photolithography. Finally, the first electrode 204 and the second electrode 205 are formed and individually chipped to complete the light emitting element structure.

  In this structure, the electrode layers (first and second connection layers) that should ensure good ohmic contact both receive an insulating layer formation history. In particular, when an electrode material containing Al, Ag, or the like is used for electrode portions (first and second connection layers) that should ensure good ohmic contact with a semiconductor material, the oxide film is formed. It is easily oxidized. Since this structure is not a structure in which damage to the element constituent material due to the process history is taken into consideration, it is not suitable for increasing the output. Further, since unnecessary portions of the insulating layer are removed after formation over the entire surface having the electrodes, etching damage cannot be ignored in electrode materials containing Al, Ag, and the like. That is, with such a shape, it is impossible to realize a manufacturing process that takes into account element degradation during high-power operation.

  Further, in Patent Document 3, as shown in FIG. 18, since the first semiconductor layer (n-type layer 202) is not removed around the element, the first semiconductor is used in the scribe process for element isolation. Damage may remain in the layer. Furthermore, since the first semiconductor layer (n-type layer 202) remains exposed, when flip chip mounting is performed, the first semiconductor layer portion may be short-circuited by solder or the like. The shape of the insulating layer for implementation is not an appropriate shape.

  Furthermore, in JP-A-11-251633 (Patent Document 4), an insulating layer is provided on the p-side electrode (positive electrode), and the n-side electrode (negative electrode) is used as a part of the p-side electrode (positive electrode). A stacked structure is shown with an insulating film interposed therebetween. With this structure, the area of the n-side electrode can be effectively increased in a small GaN-based LED. However, since the semiconductor layer and the electrode layer exist around the element, in the scribing process for element isolation, there is a possibility that the semiconductor layer may be damaged and electrode peeling may occur.

Similarly, in JP 2000-114595 A (Patent Document 5), in order to effectively increase the area of the n-side electrode, an insulating layer is provided on the p-side electrode (positive electrode), and the n-side electrode ( A structure in which a negative electrode) is overlapped with a part of a p-side electrode (positive electrode) via an insulating layer is shown. However, even in this structure, since the semiconductor layer exists around the element, damage may remain in the semiconductor layer in the scribing process for element isolation.
Japanese Patent No. 3453238 JP 2001-127348 A JP 2003-17757 A JP-A-11-251633 JP 2000-114595 A

  As described above, the conventional light emitting diode structure does not have a structure that can eliminate various kinds of damage that may occur in the manufacturing process. There was a problem, and it was difficult to increase the output and efficiency of the LED.

  An object of the present invention is to provide a flip-chip mount type semiconductor light-emitting element that is a light-emitting element capable of emitting blue or ultraviolet light and has high output and high efficiency.

  The present invention relates to the following matters.

1. A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the main light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the side opposite to the main light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a main light extraction direction side of the first conductive type side electrode And a part of the second conductivity type side electrode opposite to the main light extraction direction, and (b) against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface with the non-backed side wall surface of the buffer layer that has not receded. At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and has no end step surface, A compound semiconductor light emitting device comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed at least in a main light extraction direction portion of the buffer layer.

2. For the receding sidewall surface of the thin film crystal layer,
(Ii) The buffer layers together form a receding side wall surface and have no end step surface,
2. The light emitting device according to claim 1, further comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed in at least a main light extraction direction portion of the buffer layer.

3. For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to 1 above, wherein the insulating layer covers at least a part of the receding side wall surface of the buffer layer but is not formed on the end step surface.

4). For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to 1 above, wherein the insulating layer covers a surface on an end step surface from a position away from an end of the light emitting element, and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. element.

  5). 5. The light emitting device according to 4 above, wherein a layer constituting a portion of the buffer layer whose side wall surface is not covered with the insulating layer is an undoped type.

6). 6. The light emitting device according to any one of ₁ to 5 above, wherein the width _{L1w of the} narrowest portion among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. .

7). The width L _{2w of the} narrowest portion among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer is 15 μm or more, Light emitting element.

8). 8. The light emitting device as described in 7 above, wherein the L _2w is 100 μm or more.

  9. Any one of the above 1 to 8, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. A light emitting device according to any one of the above.

  10. Said 1-9 characterized by said 2nd conductivity type side electrode including the layer which consists of a material containing the element chosen from the group which consists of Ni, Pt, Pd, Mo, Au, and those 2 or more types of combinations. The light emitting element in any one of.

11. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The light-emitting element according to any one of 1 to 10 above, wherein the light-emitting element is a single layer.

  12 12. The light-emitting element according to any one of 1 to 11 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  13. 13. The light-emitting element according to 12 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

14 14. The light emitting device as described in 13 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

15. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the buffer layer from the first conductive semiconductor layer side is reflected by the buffer layer is represented by R2, and the second conductive semiconductor layer is formed on the insulating layer. R12 is a reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident from the side is reflected by the insulating layer, and the light having the emission wavelength of the light emitting element that is perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. When the reflectance reflected by the insulating layer is represented by R11, and the reflectance by which the light having the emission wavelength of the light emitting element perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is represented by R1q. ,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The light emitting device as described in any one of 1 to 14 above, wherein the insulating layer is configured to satisfy all of the above conditions.

16. 1 to 15 above, wherein the thin film crystal layer is formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. The light emitting element in any one of.

  17. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 17. The light emitting device as described in any one of 1 to 16 above, which contains an element selected from the group consisting of Al.

18. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
18. The light-emitting element according to any one of 1 to 17 above, wherein

  19. 19. The light emitting device as described in any one of 1 to 18 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  20. 20. The light emitting device as described in any one of 1 to 19 above, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having a metal layer by solder.

  21. 21. The bonding according to claim 20, wherein the first conductive type side electrode and the second conductive type side electrode and the metal layer of the support are joined only by metal solder, or by metal solder and metal bumps. Light emitting element.

22. 22. The light emitting device as described in 20 or 21 above, wherein the base material of the support is selected from the group consisting of metal, AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN and CuW.

  23. 23. The light emitting device according to any one of 20 to 22, wherein a metal layer is not formed in a separation region between the light emitting devices of the support.

  24. 3. The light emitting device according to 2 above, wherein a surface of the substrate on the light extraction side is not flat.

  25. 4. The light emitting device according to 3 above, wherein a surface of the buffer layer on the light extraction side is not flat.

26. R3 is the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is reflected by the substrate, and the light of the emission wavelength of the light emitting element that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
3. The light emitting device according to 2 above, wherein a low reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above.

27. R3 is a reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the first conductive type semiconductor layer is reflected by the buffer layer, and the light emission that is perpendicularly incident on the light extraction side space from the buffer layer When the reflectance at which the light having the emission wavelength of the element is reflected at the interface with the space is represented by R4,
R4 <R3
4. The light emitting device according to 3 above, wherein a low reflection optical film is provided on the light extraction side of the buffer layer so as to satisfy the above.

  ADVANTAGE OF THE INVENTION According to this invention, it is a light emitting element which can emit blue or ultraviolet light, Comprising: A high output and highly efficient flip chip mount type semiconductor light emitting element can be provided.

  In the structure of the present invention, process damage at each step in the manufacturing process is eliminated, so that the function of the light emitting element is not impaired and the element is highly reliable.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”.

Further, in the present invention, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), plasma assist MBE, PLD (Pulsed).
Laser Deposition), PED (Pulsed Electron Deposition), VPE (Vapor Phase Epitaxy), LPE (Liquid
In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth equipment such as the (Phase Epitaxy) method, carrier treatment by subsequent heat treatment, plasma treatment, etc. It is described as thin film crystal growth including activation treatment.

  1A, 2 and 3A show typical examples of the compound semiconductor light emitting device of the present invention (hereinafter simply referred to as a light emitting device). 1B and FIG. 3B are diagrams in which a part of FIG. 1A and FIG. 3A is omitted for explanation. 4A and 4B are diagrams showing a shape in the middle of fabrication in order to explain the structure of the light emitting element in detail. Hereinafter, a description will be given with reference to FIGS. 1A to 4B.

  1A, 2 and 3A, the light emitting device of the present invention includes a buffer layer 22, a first conductive type semiconductor layer including a first conductive type clad layer 24, and a second type including a second conductive type clad layer 26. A conductive semiconductor layer, a compound semiconductor thin film crystal layer having an active layer structure 25 sandwiched between the first and second conductive semiconductor layers, a second conductive side electrode 27, and a first conductive side electrode 28 Have

  The second conductivity type side electrode 27 is arranged on a part of the surface of the second conductivity type clad layer 26, and the portion where the second conductivity type clad layer 26 and the second conductivity type side electrode 27 are in contact is the second current. An injection region 35 is formed. Further, the second conductivity type cladding layer, a part of the active layer structure, and a part of the first conductivity type cladding layer are removed, and the first conductivity type cladding layer 24 exposed at the removed portion is formed. The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the substrate by arranging the first conductivity type side electrode 28 in contact therewith. . The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are connected to a metal layer 41 on the support 40 via a metal solder 42, respectively.

  In the present invention, the first conductivity type side electrode and the second conductivity type side electrode do not spatially overlap each other. This means that, as shown in FIGS. 1A, 2 and 3A, when the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are projected onto the substrate surface, shadows do not overlap. .

  When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” or the like. At the same time, in the present invention, the insulating layer is disposed at an optimal position so as not to damage the element and affect the performance or affect the yield.

  The light emitting device of the present invention can take different forms at two locations: (I) the step shape of the end of the light emitting device, and (II) the shape of the insulating layer at the end of the light emitting device. (I) The step shape of the end portion of the light emitting element is roughly divided by (i) the middle of the buffer layer depending on the etching depth when forming the inter-device isolation groove for element isolation in the manufacturing process. ii) There are two options: up to (or deeper than) the substrate surface. In addition, since the wall surface of the inter-device isolation groove recedes from the element end after element isolation, in the present invention, the surface that appears as the side wall surface when forming the inter-device isolation groove is referred to as “recessed side wall surface” for the element after element isolation. " Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A step surface is formed at the end of the light emitting element between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end step surface”.

  Corresponding to the depths (i) to (ii) of the inter-device separation grooves, in (i), part of the buffer layer constitutes the receding side wall surface with respect to the receding side wall surface of the thin film crystal layer, and the rest The side wall of the buffer layer (on the main light extraction direction side) is a non-retreating side wall surface, and has an end step surface at the end of the buffer layer. In (ii), the side wall of the buffer layer also forms the receding side wall surface (because it becomes the side wall surface of the inter-device isolation trench), and therefore there is no end step surface in the present invention in which the substrate does not exist after completion of the device. Even in the case of (ii), the wall surface of the inter-device separation groove is receded from the element end surface when separated without forming the inter-device separation groove. It is called “retreat side wall surface”.

  FIG. 2 and FIG. 3A (FIG. 3B) correspond to (i). (Ii) It is FIG. 1A (FIG. 1B).

  (II) Regarding the shape of the insulating layer at the end of the light emitting element, in the manufacturing process, (i) insulation of the region including the center on the groove bottom surface while leaving the insulating layer formed on the side wall of the inter-device separation groove There is a choice of removing only the layer, or (ii) removing the insulating layer including all of the insulating layer formed on the bottom surface of the groove and a part of the side wall in the groove, and manufacturing as a result. There are two types of light-emitting elements: (i) a shape in which the insulating layer is attached to the groove bottom surface, and (ii) a shape in which the insulating layer is separated from the groove bottom surface. FIG. 3A (FIG. 3B) corresponds to (i). FIG. 1A (FIG. 1B) and FIG. 2 correspond to (ii).

  In the present invention, since the growth substrate is removed during the manufacturing process, it is not preferable that the substrate is provided with an insulating layer when the substrate is removed. Therefore, in combination with the above, (I) the step shape of the end of the light emitting element is (ii) the shape without a step in the buffer layer, and (II) the shape of the insulating layer at the end of the light emitting element is (i) A combination that forms a shape in which the insulating layer is attached to the bottom surface of the groove is not included in the present invention.

  The shape of the light-emitting element of the present invention is (II) the shape of the insulating layer at the end of the light-emitting element, the first aspect: (ii) the shape in which the insulating layer is separated from the groove bottom surface, the second aspect: A description will be given separately in the order of the shape of the layer attached to the bottom surface of the groove.

  However, in common with the light emitting device of the present invention, the insulating layer does not reach the end of the buffer layer in the main light extraction direction.

[First embodiment]
The form belonging to the first aspect is shown in FIGS. First, a typical form will be described with reference to FIG. 1A. As shown in FIG. 1A, the light-emitting element of the present invention does not have a substrate in the main light extraction direction. The insulating layer 30 includes at least a first conductivity type semiconductor layer (first conductivity type cladding layer 24 in the figure), an active layer structure 25, and a second conductivity type among the side wall surfaces exposed when the thin film crystal layer is removed. The side wall surface of the semiconductor layer (the second conductivity type cladding layer 26 in the figure) is covered. Further, at least the main light extraction direction side of the side wall surface of the buffer layer 22 is an insulating layer non-formation portion 15 that is not covered with the insulating layer, and in some cases, this extends over the entire side wall surface of the buffer layer 22. It may be. Thus, in the light emitting device of the present invention, there is no insulating layer at the device end on the main light extraction direction side of the buffer layer. This is the same even when the buffer layer has an end step surface in other embodiments.

  Moreover, it is preferable that the buffer layer of the insulating layer non-formation part 15 which is not covered with the insulating layer is an undoped part which is not doped. If the exposed part is a highly insulating material, there is no possibility of short circuit due to the wrapping of solder, and the element is highly reliable.

  This structure passes through the shape shown in FIG. 4A before element division during the manufacturing process. In the middle of the manufacturing process, the insulating layer 30 is removed from the substrate surface (groove bottom surface) in the groove of the inter-device separation groove 13 and the insulating layer non-forming portion 15 on the groove side wall surface adjacent to the substrate surface (groove bottom surface). Yes. In the present invention, the substrate 21 is peeled off during the manufacturing process. At this time, since the insulating layer 30 is not in contact with the substrate 21, the insulating layer is not peeled when the substrate is peeled off. Therefore, in addition to ensuring reliable insulation, the thin film crystal layer is not damaged by the tension generated when the insulating layer is peeled off.

  In the light-emitting element after separation obtained as a result, there is an insulating layer non-formed portion 15 that is not covered with the insulating layer on the main light extraction direction side of the wall surface of the buffer layer 22 as shown in part A of FIG. 1A. To do. In other words, this shape ensures that there is no peeling of the insulating layer on the side surface of the thin film crystal layer. As a result, this light-emitting element can prevent an unintended short circuit even if the solder wraps around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element is not impaired and the element is highly reliable.

Furthermore, the insulating layer 30 is in contact with a part of the substrate side (main light extraction direction side) of the first conductivity type side electrode 28 as shown in a portion B of FIG. 1B. That is, an insulating layer is interposed between a part between the first conductivity type side electrode 28 and the first conductivity type semiconductor layer (the first conductivity type cladding layer 24 in this embodiment). As a result, the area of the first conductivity type side electrode 28 is larger than the area of the first current injection region 36. As shown in FIG. 1B, when the width of the narrowest portion among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer is L _1w , L _1w is preferably 7 μm or more, particularly 9 μm or more. preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

Furthermore, the insulating layer 30 covers a part on the support side (opposite to the main light extraction direction) of the second conductivity type side electrode 27, as shown in part C of FIG. 1B. That is, the area of the electrode exposed portion 37 of the second conductivity type side electrode 27 is smaller than the area of the second conductivity type side electrode 27, and the area of the second current injection region 35 is equal to the area of the second conductivity type side electrode 27. equal. As shown in FIG. 3, when the width of the narrowest portion of the width covered with the insulating layer from the periphery of the second conductivity type side electrode is L _2W , L _2W is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material. L _2w is usually 2000 μm or less, preferably 750 μm or less.

  In addition, the first conductive semiconductor layer (first conductive clad layer 24 in this embodiment) and the second conductive semiconductor layer (second conductive clad layer 26 in this embodiment) on the support side (main light extraction direction). The exposed portion of the surface on the opposite side is also usually covered with an insulating layer 30 as shown in the figure to prevent short circuits.

  Due to such a positional relationship between the insulating layer and each electrode, it is possible to manufacture by a process with little process damage.

[First aspect 2]
The other form which belongs to a 1st aspect is demonstrated using FIG. 1A is different from the light emitting device of FIG. 1A in that (I) the step shape of the end portion of the light emitting device is (ii) the shape in which there is no step in the buffer layer. The light-emitting element indicated by (i) is that it has a shape having an end step surface based on the inter-device separation groove at the end of the buffer layer.

  This shape is manufactured by forming the inter-device isolation groove partway in the buffer layer, and as a result, in the completed device, at least the first conductive type semiconductor layer, the active layer structure and the second conductive type semiconductor layer are Retreating inward from the end of the element, a receding side wall surface is formed, and an end step surface exists between the element end wall surface (non-retreating side wall surface).

  FIG. 2 shows an example of a light emitting device manufactured by forming an inter-device separation groove partway through the buffer layer 22. As shown in part A, up to the light emitting device end, a part of the buffer layer 22 exists as a non-retreat side wall surface, the wall surface retreats from the element end from the middle of the buffer layer 22, and the side wall surface of the second conductivity type semiconductor layer In addition, a receding side wall surface (side wall of the inter-device separation groove) is formed. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. The non-retreating side wall surface (side wall portion of the element end) is not covered with the insulating layer, the end step surface is not covered with the insulating layer, and the retreating side wall surface (side wall of the inter-device separation groove) The insulating layer non-formed portion 15 that is not covered with the insulating layer exists on the main light extraction direction side. The insulating layer non-forming portion 15 may extend over the entire side wall surface of the buffer layer 22 in some cases.

  A device in which the insulating layer covering the sidewall does not reach the end of the light emitting element even when the inter-device separation groove is formed up to the middle of the combined buffer layer as in this example Since it is guaranteed that the insulating layer is not peeled off, and the exposed layer is made of a highly insulating material, a highly reliable device similar to the light-emitting element shown in FIG. 1A can be obtained.

[Second embodiment]
In the second aspect, (II) the shape of the insulating layer at the end of the light emitting element is (i) the shape in which the insulating layer is attached to the bottom surface of the groove. In the light emitting device of FIG. 3A, the device separation groove is formed partway through the buffer layer 22 before the device is divided, and the insulating layer 30 covers the entire groove bottom surface of the device separation groove 13. Instead, the scribe region 14 where the insulating layer 30 is not formed is formed on the bottom surface of the groove. Therefore, it is only necessary to brake the buffer layer at the time of element separation such as scribe and braking during the manufacturing process, and the layer related to the device performance among the thin film crystal layers, that is, the first conductivity type semiconductor layer and the active layer structure. Further, the second conductive type semiconductor layer is not directly damaged. In addition, since the insulating layer is not peeled off because it is divided from the scribe region without the insulating layer on the bottom surface of the groove, the thin film crystal layer can be separated from the thin film crystal layer by pulling when the insulating layer is peeled off in addition to maintaining reliable insulation. There is no damage.

In the separated light-emitting element obtained as a result, the insulating layer does not cover the entire surface of the end step surface (groove bottom surface) formed in the buffer layer, as shown in part A of FIGS. 3A and 3B. The substrate surface on the inner side than the position separated from the element end by L _ws is covered. When divided from the center of the width of the scribe region 14, the distance L _ws that is not covered with the insulating layer corresponds to approximately ½ of the width of the scribe region 14 in the range of manufacturing fluctuation or the like. In other words, this shape ensures that there is no peeling of the insulating layer on the side surface of the thin film crystal layer. As a result, this light emitting element can prevent an unintended short circuit even if there is a solder wrap around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element is not impaired and the element is highly reliable.

L _ws may be larger than 0 in a completed device, but is usually 10 μm or more, preferably 15 μm or more. As a design value, if the width of the scribe region 14 is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

  Also in the light-emitting element of the second embodiment, by forming the exposed layer with a highly insulating material, a highly reliable device is obtained as in the light-emitting element in the form of FIG. 1A. Further, the shape of the other parts of the second mode is the same as that of the first mode.

  Below, each member and structure which comprise an apparatus are demonstrated in detail.

<Board>
In the present invention, a substrate on which a semiconductor layer can be grown is selected and a substrate that can be finally removed is used. The substrate need not be transparent, but when the substrate is peeled off by laser debonding, which will be described later, in the manufacturing process, it is preferable to transmit laser light having a specific wavelength. Further, it is preferably an electrically insulating substrate. This is because, in the manufacturing process, when the substrate is similarly peeled by the laser debonding method, it is difficult to adopt such a substrate peeling method due to absorption by free electrons or the like in the conductive substrate. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less It is desirable from the viewpoint of electrical resistance and crystallinity. In addition, when chemical etching is premised when removing the substrate, ZnO that can be easily removed with hydrochloric acid or the like is desirable.

  The substrate used in the present invention is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. it can. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture an integrated compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer described later, so that a threading transition that occurs at the interface between the thin film crystal layer and the substrate can be activated in the light emitting element or the light emitting unit described later. It is also possible not to introduce it in the vicinity of the layer.

  In one embodiment of the present invention, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication so that the crystal growth of the semiconductor light emitting device and the mechanical strength in the element fabrication process are ensured. It is normal to keep it. After the necessary semiconductor layer is grown using the substrate, the substrate is removed by, for example, polishing, etching, laser debonding, or the like. In particular, when the film is peeled off by an optical method such as laser debonding, it is desirable to use a double-sided polished substrate during the growth of a thin film crystal. This is because if a single-side polished substrate is used for a laser irradiated from a surface on which no thin film crystal is grown, it will be incident from a rough surface, and an unnecessarily large laser output is required during laser debonding. It is.

<Buffer layer>
The buffer layer 22 mainly grows a thin film crystal on the substrate, suppresses transition, alleviates the imperfection of the substrate crystal, and reduces various mismatches between the substrate crystal and the desired thin film crystal growth layer. Formed for the purpose of thin film crystal growth.

  The buffer layer is formed by thin film crystal growth, and is used when a thin film crystal growth of an InAlGaN-based material, InAlBGaN-based material, InGaN-based material, AlGaN-based material, GaN-based material, or the like, which is a desirable form in the present invention, is performed on a different substrate. Since the lattice constant matching with the substrate is not necessarily ensured, the buffer layer is particularly important. For example, when a thin film crystal growth layer is grown by metal organic vapor phase epitaxy (MOVPE method), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or a low temperature growth GaN layer formed near 500 ° C. Can also be used. Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer 22 is not necessarily a single layer, and a GaN layer grown at a temperature of about 1000 ° C. without doping is further formed on the GaN buffer layer grown at a low temperature in order to improve the crystallinity. You may make it have about several micrometers. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. The buffer layer may be doped with Si or the like, or may be formed by stacking a doped layer and an undoped layer in the buffer layer.

  As a typical embodiment, a low-temperature buffer layer in which a thin film crystal is grown at a low temperature of about 350 ° C. to less than 650 ° C. in contact with a substrate, and a high-temperature buffer layer in which a thin film crystal is grown at a high temperature of about 650 ° C. to 1100 ° C. The thing of a 2 layer structure is mentioned.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to the present invention. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  In the completed device, as already described, at least the vicinity of the substrate side (the substrate side when the buffer layer is formed) of the sidewall surface of the buffer layer is not covered with the insulating layer.

  In the present invention, since the substrate is removed during the manufacturing process, in one embodiment of this aspect, the surface of the buffer layer becomes the main light extraction surface. As will be described later, as one method of peeling the substrate, a part of the buffer layer is optically decomposed and peeled off using light that is transparent to the substrate and absorbs the buffer layer. A method is mentioned. When such a method is adopted, a material suitable for the method is selected. For example, when the substrate is sapphire and the buffer layer is GaN, a KrF excimer laser having a wavelength of 248 nm is irradiated from the substrate side where the thin film crystal growth is not performed, and the buffer layer GaN is decomposed into metal Ga and nitrogen. As a result, laser debonding for peeling off the substrate can also be performed.

In the present invention, since there is no substrate in the main light extraction direction, it is desirable that a so-called low reflection coating layer or low reflection optical film is formed on the surface of the buffer layer in the main light extraction direction. Reflection due to a difference in refractive index at the buffer layer-air interface can be suppressed, and higher output and higher element efficiency can be achieved. Here, the reflectance with which the light of the emission wavelength of the light emitting element perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer side to be described later is reflected by the buffer layer is R3, and the space from the buffer layer to the light extraction side is R3. When the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident is reflected at the interface with the space is represented by R4,
R4 <R3
It is desirable to provide a low reflection optical film on the light extraction side of the buffer layer so as to satisfy the above. For example, when the buffer layer is GaN, it is desirable to use Al ₂ O ₃ or the like as the low reflection coating film. This is because it is desirable that the refractive index of the low-reflection coating film is close to √n _bf with respect to the refractive index n _bf of the buffer layer at the light emission wavelength of the device, so that Al ₂ O with respect to the square root of the refractive index of GaN. _{This is because} the refractive index of ₃ is close.

It is also preferable that the surface in the light extraction direction of the buffer layer is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Here, when the emission wavelength of the element is λ (nm), the degree of the rough surface of the buffer layer is the average roughness Ra (nm).
λ / 5 (nm) <Ra (nm) <10 × λ (nm)
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

  In the present invention, at least a part of the buffer layer is exposed at the device end. Therefore, at least the exposed portion is preferably an undoped portion, since insulation failure due to solder or the like during device assembly can be suppressed.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In the exemplary embodiment of the present invention, a first conductivity type cladding layer 24 is present in contact with the buffer layer 22 as shown in FIG. The first conductivity type clad layer 24 functions together with the second conductivity type clad layer 26 described later to the active layer structure 25 described later to efficiently inject carriers and suppress overflow from the active layer structure. In addition, it has a function for realizing light emission in the quantum well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The first conductivity type semiconductor layer includes a layer doped to the first conductivity type in addition to the above-mentioned layer having a cladding function, such as a contact layer, for improving the function of the device or for manufacturing reasons. . In a broad sense, the entire first conductivity type semiconductor layer may be considered as the first conductivity type cladding layer, and in this case, the contact layer and the like can also be regarded as a part of the first conductivity type cladding layer.

  In general, the first conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described later and a material larger than the average band gap of the active layer structure described later. It is desirable. Furthermore, the first conductivity type cladding layer is generally made of a material that forms a so-called type I band lineup in relation to the barrier layer in the active layer structure. Under such guidelines, the first conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure, and the like prepared for realizing a desired emission wavelength.

  For example, when C + plane sapphire is used as a substrate and a laminated structure of low-temperature grown GaN and high-temperature grown GaN is used as a buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material is used as the first conductivity type cladding layer. A material, an InAlBGaN-based material, or a multilayer structure thereof can be used.

The carrier concentration of the first conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 5 × 10 ¹⁷ cm ⁻³ or more, and most preferably 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and most preferably 7 × 10 ¹⁸ cm ⁻³ or less. Here, when the first conductivity type is n-type, Si is most desirable as a dopant.

  In the example of FIG. 1, the structure of the first conductivity type cladding layer shows a first conductivity type cladding layer composed of a single layer, but the first conductivity type cladding layer is composed of two or more layers. Also good. In this case, for example, a GaN-based material and an AlGaN-based material, an InAlGaN-based material, or an InAlBGaN-based material can be used. Further, the entire first conductivity type cladding layer may be a superlattice structure as a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the first conductivity type cladding layer.

  In the portion of the first conductivity type clad layer that is in contact with the first conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  A part of the first conductivity type cladding layer is etched, and the exposed side wall, the etched part, etc. of the first conductivity type cladding layer are in contact with the first conductivity type side electrode described later. A structure in which all except one current injection region is covered with an insulating layer is desirable.

  In addition to the first conductivity type cladding layer, a different layer may exist as necessary as the first conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

<Active layer structure>
An active layer structure 25 is formed on the first conductivity type cladding layer 24. The active layer structure is a layer that emits light by recombination of electrons and holes (or holes and electrons) injected from the above-described first conductivity type cladding layer and the second conductivity type cladding layer described later. A structure including a quantum well layer and including a barrier layer disposed adjacent to the quantum well layer or disposed between the quantum well layer and the cladding layer. Here, in order to realize high output and high efficiency, which are one object of the present invention, when the number of quantum well layers in the active layer structure is W and the number of barrier layers is B, B = W + 1 is preferably satisfied. That is, the relationship between the cladding layer and the entire layer of the active layer structure is formed as “first conductivity type cladding layer, active layer structure, second conductivity type cladding layer”, and the active layer structure is defined as “barrier layer, quantum well. It is desirable for high output to be formed as “layer, barrier layer” or “barrier layer, quantum well layer, barrier layer, quantum well layer, barrier layer”. FIG. 6 schematically shows a structure in which five quantum well layers and six barrier layers are stacked.

  Here, in the quantum well layer, the layer thickness is as thin as the de Broglie wavelength in order to express the quantum size effect and increase the luminous efficiency. For this reason, in order to achieve high output, it is desirable to provide not only a single quantum well layer but also a plurality of quantum well layers and separate them into an active layer structure. At this time, a layer that is separated while controlling the coupling between the quantum well layers is a barrier layer. In addition, it is desirable that the barrier layer exists for separation of the cladding layer and the quantum well layer. For example, when the cladding layer is made of AlGaN and the quantum well layer is made of InGaN, a form in which a barrier layer made of GaN exists between them is desirable. This is also desirable from the viewpoint of thin film crystal growth because it can be easily changed when the optimum temperature for crystal growth is different. When the clad layer is made of InAlGaN having the widest band gap and the quantum well layer is made of InAlGaN having the narrowest band gap, InAlGaN having an intermediate band gap can be used for the barrier layer. Furthermore, in general, the difference in the band gap between the cladding layer and the quantum well layer is larger than the difference in the band gap between the barrier layer and the quantum well layer, and considering the efficiency of carrier injection into the quantum well layer, The quantum well layer is preferably not directly adjacent to the cladding layer.

  It is desirable that the quantum well layer is not intentionally doped. On the other hand, it is desirable to dope the barrier layer to reduce the resistance of the entire system. In particular, the barrier layer is preferably doped with an n-type dopant, particularly Si. This is because Mg, which is a p-type dopant, easily diffuses in the device, and it is important to suppress the diffusion of Mg during high output operation. Therefore, Si is effective, and it is desirable that the barrier layer is doped with Si. However, it is preferable not to perform doping at the interface between the quantum well layer and the barrier layer.

  The active layer structure side wall of one element is preferably covered with an insulating layer 30 as shown in FIG. In this case, when flip-bonding the element manufactured according to the present invention, there is an advantage that a short circuit due to solder or the like on the side wall of the active layer structure does not occur.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductivity type cladding layer 26 efficiently injects carriers into the aforementioned active layer structure 25 together with the aforementioned first conductivity type cladding layer 24 and suppresses overflow from the active layer structure. It has a function for realizing light emission in the well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The second conductivity type semiconductor layer includes a layer doped to the second conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire second conductivity type semiconductor layer may be considered as the second conductivity type cladding layer. In that case, the contact layer or the like can also be regarded as a part of the second conductivity type cladding layer.

  In general, the second conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described above and a material larger than the average band gap of the active layer structure described above. It is desirable. Furthermore, the second conductivity type clad layer is generally made of a material that forms a so-called type I band lineup, particularly in relation to the barrier layer in the active layer structure. Under such guidelines, the second conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure and the like prepared for realizing a desired emission wavelength. For example, when C + plane sapphire is used as the substrate and GaN is used as the buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material, an AlGaBInN-based material, or the like can be used as the second conductivity type cladding layer. . Further, a laminated structure of the above materials may be used. Also, the first conductivity type cladding layer and the second conductivity type cladding layer can be made of the same material.

The carrier concentration of the second conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 4 × 10 ¹⁷ cm ⁻³ or more, and further preferably 5 × 10 ¹⁷ cm ⁻³ or more. × 10 ¹⁷ cm ⁻³ or more is most preferable. Preferably 7 × ¹⁰ 18 ^{cm -3} or less as an upper limit, more preferably 3 × ¹⁰ 18 ^{cm -3} or less, and most preferably 2 × ¹⁰ 18 ^{cm -3} or less. Here, Mg is most desirable as the dopant when the second conductivity type is p-type.

  In the example of FIG. 1A, the structure of the second conductivity type cladding layer shows an example of a single layer, but the second conductivity type cladding layer may be composed of two or more layers. Good. In this case, for example, a GaN-based material and an AlGaN-based material can be used. The entire second conductivity type cladding layer may be a superlattice structure composed of a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the second conductivity type cladding layer.

  In general, in a GaN-based material, when the n-type dopant is Si and the p-type dopant is Mg, the crystallinity of p-type GaN, p-type AlGaN, and p-type AlInGaN is n-type GaN, n It does not reach each of type AlGaN and n-type AlInGaN. Therefore, in device fabrication, it is desirable to implement a p-type cladding layer with poor crystallinity after crystal growth of the active layer structure. From this viewpoint, the first conductivity type is n-type and the second conductivity type is p-type. Is desirable.

  In addition, it is desirable that the thickness of the p-type cladding layer with poor crystallinity (which corresponds to the second conductivity type cladding layer in the case of taking a desirable form) is somewhat thin. In the present invention in which flip chip bonding is performed, the substrate side is the main light extraction direction, so there is no need to consider light extraction from the second-conductivity-type-side electrode side, which will be described later. It is possible to form a membrane electrode. For this reason, it is not necessary to expect current diffusion in the lateral direction in the second conductivity type side cladding layer as in face-up mounting, and the second conductivity type side cladding layer may be thinned to some extent. It is also advantageous from the structure. However, when it is extremely thin, the carrier injection efficiency is lowered, and therefore there is an optimum value. The thickness of the second conductivity type side cladding layer can be selected as appropriate, but is preferably 0.05 μm to 0.3 μm, and most preferably 0.1 μm to 0.2 μm.

  In the portion of the second conductivity type clad layer that is in contact with the second conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  It is desirable that the exposed side wall of the second conductivity type cladding layer be entirely covered with an insulating layer except for a second current injection region that realizes contact with the second conductivity type side electrode described later.

  Furthermore, in addition to the second conductivity type cladding layer, a different layer may exist as necessary as the second conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

  In addition, unless it is contrary to the summary of this invention, you may form the layer which does not enter into the above-mentioned category as needed as a thin film crystal layer.

<Second conductivity type side electrode>
The second conductivity type side electrode realizes a good ohmic contact with the second conductivity type nitride compound semiconductor, and becomes a reflection mirror in a good emission wavelength band when flip-chip mounted, When flip chip mounting is performed, good adhesion to a support or the like using a solder material or the like is realized. For this purpose, the material can be selected as appropriate, and the second conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  Further, when the second conductivity type is p-type and the second conductivity type side electrode side of the second conductivity type side cladding layer is GaN, Ni, Pt, Pd, A material containing either Mo or Au or two or more elements thereof is preferable. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy.

  In a particularly preferred embodiment, the first layer on the p-side cladding layer side of the second conductivity type side electrode is Ni, and the surface of the second conductivity type side electrode opposite to the p-side cladding layer side is Au. This is because Ni has a large work function absolute value, which is convenient for p-type materials, and Au is preferable as the outermost material in view of resistance to process damage described later, mounting convenience, and the like.

  The second conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the second conductivity type carrier can be injected. For example, when the second conductivity type side contact layer is provided, the second conductivity type side electrode is in contact with it. Formed.

<First conductivity type side electrode>
The first-conductivity-type-side electrode achieves good ohmic contact with the first-conductivity-type nitride compound semiconductor, and when flip-chip mounted, it becomes a reflection mirror in a good emission wavelength band, When chip mounting is performed, good adhesion to a support with a solder material or the like is realized. For this purpose, a material can be selected as appropriate. The first conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  If the first conductivity type is n-type, the n-side electrode is preferably made of Ti, Al, Ag, Mo, or a material containing two or more elements thereof. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy. These are because the absolute value of the work function of these metals is small. In addition, Al is usually exposed on the side opposite to the main light extraction direction of the n-side electrode.

  In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. It is desirable not to. This is because when the light emitting element is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while securing a sufficient area to ensure sufficient adhesion to the support or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like.

  Here, the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is preferably 15 μm or more. This is because a margin is required in the process of forming the first conductivity type side electrode, which is preferably formed by a photolithography process and a lift-off method.

  The first conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the first conductivity type carrier can be injected. For example, when the first conductivity type side contact layer is provided, the first conductivity type side electrode is in contact with it. Formed.

<Insulating layer>
When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer”. The structure and shape are as described above.

The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation. For example, single layer oxides, nitrides, fluorides and the like are preferable. Specifically, SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF It is preferably selected from _{x 1} , CaF _x , SrF _x , MgF _{x and the} like. These can secure insulating properties stably over a long period of time.

On the other hand, the insulating layer 30 can be a multilayer film of an insulator. Since this is a dielectric multilayer film, by appropriately adjusting the refractive index of the dielectric in the insulating layer, so-called high reflection having a relatively high optical reflectivity with respect to the light generated in the light emitting element. The function of the coating can also be expressed. For example, when the center value of the light emission wavelength of the element is λ, SiO _x and TiO _x are laminated to have an optical thickness of λ / 4n (where n is the refractive index of each material at the wavelength λ). Thus, it is possible to realize high reflection characteristics. In this way, when the chip is flip-chip bonded, it is possible to increase the light extraction efficiency in the main extraction direction, and an unintentional short circuit caused by soldering materials, etc. It is very desirable to prevent both of them.

Specifically, the reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the buffer layer from the first conductivity type semiconductor layer side including the first conductivity type cladding layer is reflected by the buffer layer is represented by R2, and is insulated. The reflectance of the light emitting wavelength of the light emitting element that is perpendicularly incident from the side of the second conductive type semiconductor layer including the second conductive type cladding layer in the layer is reflected by the insulating layer as R12, and the first conductive type cladding is used in the insulating layer. Light having the emission wavelength of the light emitting element that is perpendicularly incident from the first conductive type semiconductor layer including the layer is reflected by the insulating layer as R11, and is vertically incident from the active layer structure including the quantum well layer in the insulating layer. When the reflectance at which the light emitting wavelength of the light emitting element is reflected by the insulating layer is represented by R1q,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
It is preferable that the insulating layer is configured so as to satisfy at least one of the conditions, in particular, all of the expressions 1 to 3.

These are desirable ranges for an insulating layer formed of a dielectric multilayer film to function efficiently as an optical reflecting mirror. Further, considering the stability of the material and the range of refractive index, it is desirable that the dielectric film contains fluoride, and specifically, AlF _x , BaF _x , CaF _x , SrF _x , MgF It is desirable that any of _x is included.

<Support>
Although it is essential that the support 40 can serve as a support for the thin film crystal layer when the substrate is peeled off, the support 40 can also have functions of current introduction and heat dissipation after device completion. Highly desirable. From this viewpoint, the base material of the support is preferably selected from the group consisting of metal, AlN, SiC, diamond, BN, and CuW. These materials are preferable in that they are excellent in heat dissipation and can efficiently suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as a support. In addition, when a portion of the thin film crystal layer is decomposed into metal Ga and nitrogen by laser irradiation when removing the substrate, which will be described later, it is desirable to perform wet etching when removing the metal Ga. The body is preferably made of a material that is not etched. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric or the like, SiNx formed by various CVD methods, SiO ₂ or the like is desirable.

  From the viewpoint that the support further has functions of current introduction and heat dissipation after completion of the element, it is desirable that the support has electrode wiring for current introduction on the base material, and the device is mounted on this electrode wiring. It is desirable that the mounting portion has an adhesive layer for joining the device and the support as appropriate. Here, although it is possible to use a paste containing Ag, a metal bump, or the like as the adhesive layer, it is very desirable from the viewpoint of heat dissipation that it is made of metal solder. The metal solder can realize a flip chip mount that is overwhelmingly excellent in heat dissipation compared with a paste material containing Ag, a metal bump, and the like. Here, examples of the metal solder include In, InAg, InSn, SnAg, PbSn, AuSn, AuGe, and AuSi. In particular, a high melting point solder such as AuSn, AuSi, or AuGe is more desirable. This is because when a large current is injected to operate the light emitting element at an ultrahigh output, the temperature in the vicinity of the element rises to about 200 ° C. The melting point of the solder material is higher than the element temperature during driving. The metal solder which has is more preferable. In some cases, it is also desirable to use bumps in order to cancel out the level difference of the elements at the time of flip chip mounting, and further to join the metal solder material while filling the periphery thereof.

Further, since the device is usually separated by dividing the support as will be described later, in the completed light emitting device, it is preferable that an isolation region where no metal wiring exists is present around the support 40. As shown in FIG. 5, when the width of the region where no metal wiring exists is L _WSPT2 (in FIG. 5, the left side is _represented by L _{WSPT2 (left)} and the right side is represented by L _{WSPT2 (right))} , L _WSPT2 is In the completed device, it may be larger than 0, but the preferred range differs depending on what method is used in the separation step as described below.

When separating by scribing, it is usually 10 μm or more, preferably 15 μm or more. Therefore, it is preferable that 2L _WSPT2 is 30 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 300 μm or less, preferably 200 μm or less.

Further, when separating by dicing, L _WSPT2 is usually 100 μm or more, preferably 500 μm or more. Therefore, it is preferable that 2L _WSPT2 is 1000 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 2000 μm or less, preferably 1500 μm or less.

  An embodiment in which the support is not divided is also possible. For example, a plurality of light emitting elements can be mounted on one support. By freely changing the metal wiring on the support, each light emitting element on one support can be connected in parallel, connected in series, or mixed.

〔Production method〕
Next, the manufacturing method of the semiconductor light emitting device of the present invention will be described.

<The manufacturing method of the light emitting element of a 1st aspect>
In one example of the manufacturing method, as shown in FIG. 7, first, a substrate 21 is prepared, and a buffer layer 22, a first conductivity type cladding layer 24, an active layer structure 25, and a second conductivity type cladding layer 26 are thinly formed on its surface. Films are sequentially formed by crystal growth. The MOCVD method is desirably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, the VPE method, the LPE method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. In addition, various processes may be performed after the formation of the thin film crystal layer. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  After the thin film crystal layer growth, in order to realize the shape shown in FIGS. 1A to 2 in the present invention, it is preferable to form the second conductivity type side electrode 27 as shown in FIG. That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. In the case where the second conductivity type is p-type as a preferred embodiment, if the p-side electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface, This is because the hole concentration in the p-GaN cladding layer having a relatively low activation rate is reduced by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. For this reason, in the present invention, after the thin film crystal growth, the formation of the second conductivity type side electrode is performed in another process step (for example, the first etching step, the second etching step, or the insulating layer forming step described later, the second conductivity type side). It is desirable that the electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, etc.) be performed prior to this.

  In the present invention, when the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. Is a relatively stable metal such as Au, it is unlikely to be damaged by the process even after the subsequent process. Also from this viewpoint, in the present invention, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  In the present invention, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced similarly. it can.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 8, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

  Next, as shown in FIG. 9, the inter-device separation groove 13 is formed by the second etching step. In the present invention, the inter-device separation groove needs to be formed by dividing at least the first conductivity type cladding layer. In this embodiment, the inter-device separation groove 13 is formed so as to reach the substrate 21. Is done. In this case, in order to separate the device, the GaN-based material on the sapphire substrate is peeled off even when diamond scribing is performed from the side where the thin film crystal layer is formed in a process such as scribing or breaking. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to etch part of the sapphire substrate (the same applies to other substrates such as GaN) to form an inter-device separation groove.

  On the other hand, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. If the inter-device isolation groove is formed up to the middle of the buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, and insulation against sneaking of solder or the like can be maintained. (Refer to FIG. 2 for the form after the light-emitting element is completed.) In this case, the bottom surface of the groove is formed in the middle of the layer including the buffer layer, and this becomes an end step surface at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Since the bottom surface of the groove is subjected to processing such as scribing at the time of element separation, the end step surface after element separation is often not high in terms of planarity as a surface and parallelism with the layer direction. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the total sum of the layers etched by the first etching process is usually about 0.5 μm. However, in the second etching process, all of the first conductivity type cladding layer 24 and at least a part of the buffer layer 22 are used. In some cases, since it is necessary to etch the whole, it may be 3 to 7 μm, and in some cases, it may be in the range of 3 to 10 μm, and may exceed 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching process, a SiN _x mask exceeding 2 μm is required. But when it comes to SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in controllability of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate for an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of this. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _19, SiN x, SiO ₂ or the like mask 51, a metal fluoride Even if it does not exist in the entire lower portion of the chemical mask layer 52, it is sufficient if it is formed on a material that is at least susceptible to acid.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIG.

Note that the first etching step and the second etching step may be performed either first or later. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 19, first, a first etching mask 51 is formed of an acid-resistant material (preferably SiN _x ) such as SiN _x and SiO ₂ , and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the device manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the present invention is a side wall surface that appears as a side wall in the second etching step, that is, when an inter-device separation groove is formed, and is not a wall surface that appears only in the first etching.

  After the second etching step, an insulating layer 30 is formed as shown in FIG. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

  Next, as shown in FIG. 11, a predetermined portion of the insulating layer 30 is removed, and the second conductive type side electrode exposed portion 37 from which the insulating layer is removed on the second conductive type side electrode 27, the first conductive type cladding. The first current injection region 36 from which the insulating layer has been removed is formed on the layer, and the insulating layer non-formed portion 15 from which the insulating layer has been removed from the substrate surface and the side wall in the inter-device isolation trench 13 is formed.

The removal of the insulating layer 30 on the second conductivity type side electrode 27 is performed so that the peripheral portion of the second conductivity type side electrode is covered with the insulating layer. That is, the surface area of the exposed portion of the second conductivity type side electrode is smaller than the area of the second current injection region. Here, in order to prevent the occurrence of an unintended short circuit due to a margin of the element manufacturing process, particularly a photolithography process, or a solder material, a part of the second conductivity type side electrode covered with an insulating layer The width (L _2w ) of the narrowest portion is preferably 15 μm or more as described above. More desirably, it is 100 μm or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material.

For the removal of the insulating layer, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer is a single layer of SiN _x , dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

  The second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed by etching at the same time.

  In order to provide the insulating layer non-formed portion 15 by removing the insulating layer on the side wall portion in the vicinity of the substrate in the inter-device separation groove, for example, it can be formed by the following process. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device isolation trench 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer. Removal of the insulating layer on the substrate surface in the trench proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer covering the substrate side of the groove sidewall is removed with a wet etchant, and there is no insulating layer near the inter-device separation groove as shown in FIG. A shape is obtained. When the insulating layer is removed as described above, the side wall of the thin film crystal layer where the insulating layer is not present is preferably the side wall of the undoped layer. This is because an unintended electrical short circuit does not occur even when solder for joining to the support or the like adheres to the side wall when flip chip mounting is performed. Such a removed shape of the insulating layer is a desirable shape because an unintended defect such as peeling of the insulating layer does not occur accompanying the removal of the substrate, particularly during the manufacturing process of the light emitting element.

Next, as shown in FIG. 12, the first conductivity type side electrode 28 is formed. In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. The feature is not to. This is because the second conductivity type side electrode and the first conductivity type side electrode are secured while securing an area sufficient to ensure sufficient adhesion to the support when the element is flip-chip mounted with solder or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like. Among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer, the width (L _1w ) of the narrowest portion is set to be in the above-described range. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from any one of Ti, Al, Ag, and Mo. In addition, Al is usually exposed in the direction facing the main light extraction direction of the n-side electrode.

  Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode is formed so as to be in contact with a part of the first conductivity type cladding layer. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact with the first conductivity type side electrode. Can do.

  In this manufacturing method, the first conductivity type side electrode is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is formed with Al on the surface of the electrode material in a preferred embodiment. In this case, if the n-side electrode is formed before the formation of the insulating layer like the second conductivity type side electrode, the surface of the n-side electrode, that is, the Al metal, has a history of the etching process of the insulating layer. Become. As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching an insulating layer, but Al has low resistance to various etchants including hydrofluoric acid, and such a process is effectively performed. Then, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the present invention, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer is effective in reducing damage to the electrode.

  After the structure of FIG. 12 is formed in this way, preparations are made for removing the substrate. Usually, the entire structure of the wafer shown in FIG. 12 or a part thereof is first bonded to the support 40. This is because the thickness of the thin film crystal layer as a whole is at most about 15 μm, and if the substrate is peeled off, the mechanical strength becomes insufficient, and it becomes difficult to stand alone and undergo subsequent processes. It is. The material of the support is as described above.

  As shown in FIG. 13, a metal layer 41 (electrode wiring or the like) on the support 40 is connected and mounted by, for example, metal solder 42.

  At this time, in the light emitting device of the present invention, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged so as not to spatially overlap each other, and the first conductivity type side electrode is the first conductivity type side electrode. Since it is larger than one current injection region and has a sufficient area, it is desirable to prevent both unintentional short-circuiting and ensure high heat dissipation. Further, the sidewalls of other thin film crystal layers are also protected by the insulating layer except for a part of the buffer layer, particularly the undoped portion. There is no short circuit.

  Next, after bonding the element to the support, the substrate is peeled off. Any method such as polishing, etching, or laser debonding can be used for peeling the substrate. When polishing a sapphire substrate, it is possible to remove the substrate using an abrasive such as diamond. It is also possible to remove the substrate by dry etching. Furthermore, for example, when a sapphire is a substrate and a thin film crystal growth portion is formed of an InAlGaN-based material, the sapphire substrate transmits from the sapphire substrate side, and is absorbed by GaN used for the buffer layer, for example, 248 nm. It is also possible to perform laser debonding by decomposing part of GaN in the buffer layer into metal Ga and nitrogen by using a KrF excimer laser, and peeling the substrate. FIG. 14 schematically shows a state where the substrate 21 is peeled off by laser debonding.

When using ZnO, ScAlMgO ₄ or the like as a substrate, the substrate can be removed by wet etching using an etchant such as HCl.

  In the present invention, since there is no portion where the insulating layer is in contact with the substrate, when the substrate is peeled off, the insulating layer is not peeled off secondarily.

  Thereafter, as shown in FIG. 14, in the separation region 47 corresponding to the location where the inter-device separation groove exists, the light emitting element is separated together with the support to obtain a single light emitting element. Here, it is preferable that no metal wiring exists in the separation region of the support. This is because separation between devices is difficult if metal wiring exists here.

  For the cutting of the separation region portion of the support, an appropriate process such as dicing, scribing and braking can be selected depending on the base material. Further, when the inter-device separation groove is formed up to the middle of the buffer layer, the inter-device separation groove is used to perform damage by diamond scribe, ablation of a part of the buffer layer by laser scribe, or the like. Thus, separation between the light emitting elements in the thin film crystal growth layer portion can be easily realized. Thereafter, the support can be separated into light emitting elements by dicing. In some cases, the light-emitting elements can be separated simultaneously by dicing the thin film crystal growth layer and the support.

  As described above, the light emitting device having the mode shown in FIGS. 1A to 2 is completed.

<The manufacturing method of the light emitting element of a 2nd aspect>
To manufacture the light emitting device of the second aspect shown in FIG. 3A, etching is stopped in the middle of the buffer layer when forming the inter-device separation groove in the description of the manufacturing method of the first aspect. Similarly, when the insulating layer 30 is formed and the insulating layer is etched, as shown in FIG. 4B, the insulating layer is removed from the region including the center of the inter-device separation groove to form a scribe region. In the first aspect, all of the insulating layer on the bottom surface of the groove is removed, but in this aspect, an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape, and side etching is not performed. A part of the insulating layer deposited on the bottom of the groove may be removed to form a scribe region. The width of the scribe region 14 can be set so as to obtain a predetermined L _ws as described above. Thereafter, the light emitting device shown in FIG. 3A is completed in the same manner as in the first embodiment.

  In common with the first aspect and the second aspect, in this manufacturing method, as described, formation of a thin film crystal layer, formation of a second conductivity type side electrode, etching process (first etching process and second etching process) The formation of the insulating layer, the removal of the insulating layer (formation of the exposed portion of the second conductivity type side electrode, formation of the first current injection region, formation of the scribe region) and formation of the first conductivity type side electrode are carried out in this order. It is desirable to obtain a light emitting device that does not damage the thin film crystal layer directly under the second conductivity type side electrode and that does not damage the first conductivity type side electrode. The device shape reflects the process flow. That is, the light emitting element has a structure in which the second conductivity type side electrode, the insulating layer, and the first conductivity type side electrode are laminated in this order. In other words, the second conductivity type side electrode is in contact with the second conductivity type clad layer (or other second conductivity type thin film crystal layer) without an insulating layer interposed, There is a portion covered with an insulating layer, and an insulating layer is interposed between the first conductivity type side electrode and the first conductivity type side cladding layer (or other first conductivity type thin film crystal layer) around the electrode. There is a part that is.

  The features of the present invention will be described more specifically with reference to the following examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

(Example 1)
The light emitting element shown in FIG. 15 was manufactured by the following procedure. Reference is made to FIGS.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 10 nm is first formed thereon as the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 4 μm was formed at 1040 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to here generally corresponds to FIG. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second cladding layer 26b, the p-AlGaN first cladding layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches The active layer structure 25, the n-AlGaN first cladding layer 24a, the n-GaN contact layer 24c, the n-GaN second cladding layer 24b, and the undoped GaN buffer layer 22 are all made of Cl ₂ gas. ICP etching was performed. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. At this time, SiN _x and SiO _x are formed one layer at a time so that the optical wavelength is 1/4 with respect to the light emission wavelength of the device, and have a relatively high reflectance with respect to the light emission wavelength. I made it. The structure completed through the steps up to here generally corresponds to FIG.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the side wall of the substrate 21, a resist mask was formed by using a photolithography technique. Next, the portion of the dielectric multilayer film (insulating layer) not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Further, due to the side etching effect using hydrofluoric acid, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer was also removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps so far generally corresponds to FIG.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIG.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting element are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit or the like of the element did not occur.

  Next, in order to perform substrate peeling, a laser beam emitted from a KrF excimer laser (wavelength 248 nm) was irradiated from the surface of the substrate 21 where thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). . Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a separation region portion in the support and an inter-device separation groove in the wafer were simultaneously cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. In this way, the compound semiconductor light emitting device shown in FIG. 15 was completed.

(Example 2)
In Example 1, Examples 1 and 2 were repeated except that the thin film crystal layer was formed as follows after the buffer layer 22 was formed. That is, after forming the buffer layer 22 in Example 1, a 4 μm thick Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is further formed as the first conductivity type (n-type) second cladding layer 24 b. A Si-doped (Si concentration: 8 × 10 ¹⁸ cm ⁻³ ) GaN layer having a thickness of 0.5 μm is formed as the first conductivity type (n-type) contact layer 24c, and the first conductivity type (n-type) is further formed. A Si-doped (Si concentration: 5.0 × 10 ¹⁸ cm ⁻³ ) Al _0.10 Ga _0.90 N layer having a thickness of 0.1 μm was formed as the first cladding layer 24a. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, in the same manner as in Example 1, the light emitting device shown in FIG. 15 was completed. At this time, an unintended short circuit of the element did not occur.

In the processes of Examples 1 and 2, the SiN _x mask was removed after the first etching step, but it may be removed after the second etching step without removing the SiN _x mask.

  Furthermore, in Example 1 and Example 2, the light emitting element shown in FIG. 2 can be manufactured by stopping the etching in the second etching process in the middle of the buffer layer (however, the insulating layer is a multilayer dielectric). film). For element isolation, the element isolation region in the support may be cut together with the buffer layer at the bottom of the inter-device isolation groove.

Further, in order to manufacture the light emitting device shown in FIG. 3A, in Example 1 and Example 2, the etching in the second etching process is stopped in the middle of the buffer layer, and further, the side etching of the insulating layer is not advanced. for example, as the width of the scribe region becomes 100 [mu] m (L _WS is 50μm in the device after separation) may be carried out by forming a scribe region while leaving the insulating layer in the groove bottom surface (where the insulating layer Is a multilayer dielectric film).

(Example 3)
The light emitting element shown in FIG. 16 was manufactured by the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 3 μm was formed at 1040 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The quantum well layers were alternately formed so that the total number of the quantum well layers was three and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Then, in order to implement the second etching step of forming a device separation trench, using a vacuum deposition method to form a SrF ₂ mask to the whole wafer surface. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. All of the thin-film crystal layers up to the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, and the undoped GaN buffer layer 22 are made of Cl ₂ gas. ICP etching was used. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer present on the substrate side portion of the sidewall, a resist mask was formed by using a photolithography technique. Next, the portion of the insulating layer not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Further, the insulating layer on the substrate side portion of the side wall of the undoped buffer layer was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 was covered with an SiN _x insulating layer of 150 μm. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting elements are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit or the like of the element did not occur.

  Next, in order to perform substrate peeling, laser light emitted from a KrF excimer laser (248 nm) was irradiated from the surface of the substrate 21 on which thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a dicing saw was used to simultaneously cut the support body separation region and the inter-device separation groove in the wafer. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the compound semiconductor light emitting device shown in FIG. 16 was completed.

It is a figure which shows the example of the light emitting element of a 1st aspect. It is a figure for showing the positional relationship of the light emitting element of the 1st mode. It is a figure which shows the example of the light emitting element of a 1st aspect. It is a figure which shows the example of the light emitting element of a 2nd aspect. It is a figure for showing the positional relationship of the light emitting element of the 2nd mode. It is a figure which shows an example of the structure before completion of the light emitting element of a 1st aspect. It is a figure which shows an example of the structure before completion of the light emitting element of a 2nd aspect. It is a figure for showing the positional relationship of the light emitting element of the aspect of this invention. It is a figure which shows an active layer structure typically. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. 2 is a view showing a light emitting device manufactured in Example 1. FIG. 6 is a view showing a light emitting device manufactured in Example 2. FIG. It is a figure which shows the conventional light emitting element. It is a figure which shows the conventional light emitting element. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light emitting element 13 Device separation groove 14 Scribe area | region 15 Insulating layer non-formation part 22 Buffer layer 22a 1st buffer layer 22b 2nd buffer layer 24 1st conductivity type cladding layer 24a 1st conductivity type 1st cladding layer 24b 1st One conductivity type second cladding layer 24c First conductivity type (n-type) contact layer 25 Active layer structure 26 Second conductivity type cladding layer 26a Second conductivity type first cladding layer 26b Second conductivity type second cladding layer 26c Second Conductive type (p-type) contact layer 27 Second conductive type side electrode 28 First conductive type side electrode 30 Insulating layer 35 Second current injection region 36 First current injection region 37 Exposed surface 40 of second conductive type side electrode Support 41 Metal layer 42 Metal solder 45 Low reflection optical film 47 Separation region 50b in support body Light extraction surface 51 First etching mask (SiN _x, etc.)
52 Second etching mask (metal fluoride mask)
55 End step surface

Claims (27)

A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the main light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the side opposite to the main light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a main light extraction direction side of the first conductive type side electrode And a part of the second conductivity type side electrode opposite to the main light extraction direction, and (b) against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface with the non-backed side wall surface of the buffer layer that has not receded. At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and has no end step surface, A compound semiconductor light emitting device comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed at least in a main light extraction direction portion of the buffer layer. For the receding sidewall surface of the thin film crystal layer,
(Ii) The buffer layers together form a receding side wall surface and have no end step surface,
2. The light emitting device according to claim 1, further comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed in at least a main light extraction direction portion of the buffer layer. For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
The light emitting device according to claim 1, wherein the insulating layer covers at least a part of the receding side wall surface of the buffer layer, but is not formed on the end step surface. For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
2. The insulating layer covers a surface that coincides with a side wall receding surface of the first conductivity type semiconductor layer on the end step surface from a position away from the light emitting element end. Light emitting element.   5. The light emitting device according to claim 4, wherein a layer constituting a portion of the buffer layer whose side wall surface is not covered with the insulating layer is an undoped type. The light emission according to any one of claims 1 to 5, wherein the width _{L1w of the} narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is 5 µm or more. element. The width _{L2w of the} narrowest part among the width _{| variety of the} part with which the said 2nd conductivity type side electrode is covered with the said insulating layer is 15 micrometers or more, The any one of Claims 1-6 characterized by the above-mentioned. Light emitting element. The light emitting device according to claim 7, wherein L _2w is 100 μm or more.   The first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and a combination of two or more thereof. The light emitting element in any one.   The second conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ni, Pt, Pd, Mo, Au, and combinations of two or more thereof. The light emitting device according to any one of 9. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The light-emitting element according to claim 1, wherein the light-emitting element is a single layer.   The light-emitting element according to claim 1, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.   The light emitting element according to claim 12, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride. It said _{fluoride, AlF x, BaF x, CaF} x, the light emitting device of claim 13 wherein the selected from the group consisting of SrF _x and MgF _x. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the buffer layer from the first conductive semiconductor layer side is reflected by the buffer layer is represented by R2, and the second conductive semiconductor layer is formed on the insulating layer. R12 is a reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident from the side is reflected by the insulating layer, and the light having the emission wavelength of the light emitting element that is perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. When the reflectance reflected by the insulating layer is represented by R11, and the reflectance by which the light having the emission wavelength of the light emitting element perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is represented by R1q. ,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The light-emitting element according to claim 1, wherein the insulating layer is configured to satisfy all of the conditions. The thin film crystal layer is formed by being formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. The light emitting device according to any one of 15.   The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and The light-emitting element according to claim 1, comprising an element selected from the group consisting of Al. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting element according to claim 1, wherein:   The light emitting device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The light emitting device according to claim 1, wherein the first conductivity type side electrode and the second conductivity type side electrode are bonded to a support having a metal layer by solder.   21. The bonding between the first conductivity type side electrode and the second conductivity type side electrode and the metal layer of the support is made of only metal solder, or metal solder and metal bumps. The light emitting element of description. The base material of the support, a _{metal, AlN, Al 2 O 3,} Si, glass, SiC, diamond, light emitting device according to claim 20 or 21, wherein the selected from the group consisting of BN and CuW.   23. The light emitting device according to claim 20, wherein a metal layer is not formed in a separation region between the light emitting devices of the support.   The light emitting device according to claim 2, wherein a surface of the substrate on the light extraction side is not flat.   4. The light emitting device according to claim 3, wherein a surface of the buffer layer on a light extraction side is not flat. R3 is the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is reflected by the substrate, and the light of the emission wavelength of the light emitting element that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
The light emitting device according to claim 2, wherein a low reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above. R3 is a reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the first conductive type semiconductor layer is reflected by the buffer layer, and the light emission that is perpendicularly incident on the light extraction side space from the buffer layer When the reflectance at which the light having the emission wavelength of the element is reflected at the interface with the space is represented by R4,
R4 <R3
4. The light emitting device according to claim 3, wherein a low reflection optical film is provided on the light extraction side of the buffer layer so as to satisfy the above condition.

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