JP2007329465A - Method of manufacturing semiconductor light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a flip-chip mounting semiconductor light-emitting device which can emit blue or ultraviolet light with high power and high efficiency, and has a high luminance uniformity at a light extracting surface. <P>SOLUTION: The method of manufacturing the light-emitting device includes: (a) a step of forming a buffer layer, a light uniforming layer, and a thin-film crystal layer; (c) a step of forming a second conductive side electrode; (d) a step of exposing one part of a first conductive semiconductor layer; (e) a step of forming an inter-apparatus separating trenches by executing etching from a surface to (i) one part of the light uniforming layer, (ii) one part of the buffer layer, or (iii) the substrate; (f) a step of forming an insulating layer on the overall surface; (g) a step of removing the insulating layer of a trench center region of the substrate surface in the inter-apparatus separating trenches; (h) a step of forming a first current injection region on the surface of the first conductive semiconductor layer; (i) a step of exposing one part of the second conductive side electrode on the surface of the second conductive side electrode; and (j) a step of forming a first conductive side electrode so as to contact the first current injection region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a compound semiconductor light emitting device, and more particularly to a light emitting diode (LED) using a GaN-based material. Note that in this specification, the expression “light-emitting diode or LED” is used as a term including a general light-emitting element including a laser diode, a superluminescent diode, and the like.

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue or ultraviolet LEDs with the illumination application in mind.

  In order to increase the output of the element, that is, to improve the total radiant flux, it is indispensable to increase the size of the element and to ensure the resistance against large input power. A flip chip mount structure is known as an effective structure for increasing the output and efficiency of LEDs. In this structure, a predetermined semiconductor layer is deposited on a sapphire substrate, an n-side electrode and a p-side electrode for current injection are formed on the opposite side of the substrate, and the substrate side is the main light extraction direction. For this reason, since the light emitted from the light emitting element is not blocked and the electrode can be used as a light reflecting surface, the light extraction efficiency is improved.

  However, since a pair of electrodes on the p-side and n-side are formed on the same side in the flip-chip structure, when the element is mounted on the support (wiring, heat dissipation substrate) by soldering, p It is necessary to consider so that a short circuit between the side electrode and the n-side electrode and a short circuit between the electrode and the p-type semiconductor layer or the n-type semiconductor layer do not occur. For this reason, various insulation ensuring structures have been proposed.

Japanese Patent No. 3453238 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2001-127348 (Patent Document 2) describe an insulating substrate surface, an n-type nitride semiconductor layer surface, and a p-side nitride semiconductor layer surface. In addition, an element is disclosed in which an insulating coating continuous from the end face of the n-type nitride semiconductor layer to the electrode-side surface is formed. The element structure of Patent Document 1 is shown in FIGS. In order to manufacture this structure, first, an n-type nitride semiconductor layer 102 and a p-type nitride semiconductor layer 103 are sequentially grown on a sapphire substrate 101, and the end portions of the n-type layer 102 and the p-type layer 103 are formed by RIE. Using this method, dry etching is performed to remove the surface of the sapphire substrate 101 so as to have a shape as shown in FIG. Subsequently, dry etching is performed on the p-type layer 103 and part of the n-type layer 102 by using the RIE method to expose the n-type layer 102 so as to have a shape as shown in FIG. After etching, a negative electrode (n-side electrode) 104 is formed on the n-type layer 102 surface, and a positive electrode (p-side electrode) 105 is formed on the p-type layer 103 surface. An insulating film 106 made of SiO ₂ is formed so as to cover the end face of the n-type layer 102 removed by etching and the surface on the electrode side, and the light emitting device of FIG. 19 is completed. At this time, the exposed surfaces of the negative electrode 104 and the positive electrode 105 are exposed so as to be bonded. And the mounting structure shown in FIG.19 (b) is obtained by connecting the negative electrode 104 and the positive electrode 105 to the conductive part 111 on the wiring board 110 via the conductive adhesive 107.

In this structure, since the semiconductor end face is covered with an insulating material, an effect is seen in preventing an electrical short circuit, but the electrode material is likely to deteriorate when an insulating layer (insulating film) is formed. There's a problem. In the p-side electrode, since Au is often used as a layer exposed on the surface, the influence of deterioration is small. In particular, the n-side electrode has high reflectivity and is easily ohmic with an n-type GaN-based material. Since a material containing Al or the like is often used as a material that can realize contact, it is easily affected by the film formation process of the insulating layer. The insulating film is formed of SiO ₂ , TiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ or the like by vapor deposition, sputtering, CVD, etc. In any case, a part of the n-side electrode material is Even if the exposed part is properly covered with a mask material, the entire material is subject to the effects of oxidation, nitridation, etc., and the electrode material deteriorates when trying to inject a large current for high output operation of the device. There is a concern that the influence of the above will become noticeable and eventually cause deterioration of the element. Furthermore, if the exposed portion of the electrode is formed by etching after the insulating layer is formed, the exposed portion itself is affected by the etching process, and in some cases, the electrode material itself may be etched. For example, Al is easily etched with an etchant capable of etching an insulating film such as HF. This problem is exactly the same in the element of Patent Document 2.

  Therefore, the structures described in Patent Documents 1 and 2 cannot be said to be a structure that takes into account the process history that should be taken into account when the element is operated at a high output and the damage to the element constituent material due to the process history. It is an unsuitable structure.

  Further, in the structure of Patent Document 1, since the insulating film is formed on the side wall of the n-side nitride semiconductor layer and the entire surface of the peripheral portion of the element of the substrate, the wafer process is completed, and then each of the LED elements There is a problem that the insulating layer is likely to be peeled off in a scribing process using diamond for separation (scratching for elements) or a scribing process using a high-power laser. The peeling of the insulating layer causes a short circuit at the time of mounting, and as a result, the yield of device manufacturing decreases. The element of Patent Document 2 has the same structural problem as that of Patent Document 1.

  In addition, for a small LED element, Japanese Patent Laid-Open No. 2003-17757 (Patent Document 3) discloses a flip chip type element structure (see FIG. 20) mainly for increasing the area of a p-side electrode and an n-side electrode. Proposed. In order to manufacture this flip chip type light emitting device, first, the n-type layer 202 is grown on the sapphire substrate 201 by vapor phase growth or vapor deposition, and the p-type layer 203 is grown thereon. Subsequently, after removing a part of the outer peripheral portion of the p-type layer 203 by etching or the like, a first connection layer (a part of an electrode) 206 is formed around the n-type layer 202 and on the p-type layer 203. A second connection layer (a part of the electrode) 207 is formed by vapor deposition or the like. After that, an insulating layer 208 such as an oxide film is grown to cover the whole, and unnecessary portions of the insulating layer 208 are removed by photolithography. Finally, the first electrode 204 and the second electrode 205 are formed and individually chipped to complete the light emitting element structure.

  In this structure, the electrode layers (first and second connection layers) that should ensure good ohmic contact both receive an insulating layer formation history. In particular, when an electrode material containing Al, Ag, or the like is used for electrode portions (first and second connection layers) that should ensure good ohmic contact with a semiconductor material, the oxide film is formed. It is easily oxidized. Since this structure is not a structure in which damage to the element constituent material due to the process history is taken into consideration, it is not suitable for increasing the output. Further, since unnecessary portions of the insulating layer are removed after formation over the entire surface having the electrodes, etching damage cannot be ignored in electrode materials containing Al, Ag, and the like. That is, with such a shape, it is impossible to realize a manufacturing process that takes into account element degradation during high-power operation.

  Further, in Patent Document 3, as shown in FIG. 20, since the first semiconductor layer (n-type layer 202) is not removed around the element, the first semiconductor is used in the scribe process for element isolation. Damage may remain in the layer. Furthermore, since the first semiconductor layer (n-type layer 202) remains exposed, when flip chip mounting is performed, the first semiconductor layer portion may be short-circuited by solder or the like. The shape of the insulating layer for implementation is not an appropriate shape.

  Furthermore, in JP-A-11-251633 (Patent Document 4), an insulating layer is provided on the p-side electrode (positive electrode), and the n-side electrode (negative electrode) is used as a part of the p-side electrode (positive electrode). A stacked structure is shown with an insulating film interposed therebetween. With this structure, the area of the n-side electrode can be effectively increased in a small GaN-based LED. However, since the semiconductor layer and the electrode layer exist around the element, in the scribing process for element isolation, there is a possibility that the semiconductor layer may be damaged and electrode peeling may occur.

  Similarly, in JP 2000-114595 A (Patent Document 5), in order to effectively increase the area of the n-side electrode, an insulating layer is provided on the p-side electrode (positive electrode), and the n-side electrode ( A structure in which a negative electrode) is overlapped with a part of a p-side electrode (positive electrode) via an insulating layer is shown. However, even in this structure, since the semiconductor layer exists around the element, damage may remain in the semiconductor layer in the scribing process for element isolation.

In addition to the above problems, when the light extraction surface of the device is viewed as one light emitting surface, there is a dark portion due to the electrode portion formed excluding the active layer, and uneven current injection in the active layer. When this occurs, brightness unevenness may occur on the light extraction surface. Unevenness becomes more noticeable as the element becomes larger. For use as a next-generation lighting device, the presence of dark portions and the occurrence of unevenness are not preferable.
Japanese Patent No. 3453238 JP 2001-127348 A JP 2003-17757 A JP-A-11-251633 JP 2000-114595 A

  As described above, the conventional light emitting diode structure does not have a structure that can eliminate various kinds of damage that may occur in the manufacturing process. There was a problem, and it was difficult to increase the output and efficiency of the LED. Furthermore, improvement in the uniformity of the light emitting surface has also been demanded.

  The present invention provides a method for manufacturing a flip-chip mount type semiconductor light emitting device that is a light emitting device capable of emitting blue or ultraviolet light and has high output, high efficiency, and high brightness uniformity on a light extraction surface. For the purpose.

  The present invention relates to the following matters.

1. (A) a step (a) of forming a buffer layer and a light uniformizing layer in this order on a substrate;
(B) At least a first conductive type semiconductor layer including a first conductive type cladding layer, an active layer structure, and a thin film crystal layer having a second conductive type semiconductor layer including a second conductive type cladding layer from the substrate side. A step (b) of sequentially forming a film;
(C) a step (c) of forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
(D) a first etching step (d) in which a part of the portion where the second conductivity type side electrode is not formed is etched to expose a part of the first conductivity type semiconductor layer;
(E) In order to form an inter-device separation groove for separating adjacent light emitting elements, a part of the portion where the second conductivity type side electrode is not formed is separated from the surface, (i) the light uniformizing layer Etching is performed at a depth until at least a portion is removed, (ii) at least a portion of the buffer layer is removed, or (iii) at least reaches the substrate. Two etching steps (e);
(F) a step (f) of forming an insulating layer on the entire surface including the second conductivity type side electrode, the first conductivity type semiconductor layer exposed by the first etching step, and the inside of the inter-device isolation trench;
(G) removing an insulating layer in a region including at least the groove center of the groove bottom surface in the inter-device separation groove;
(H) removing a part of the insulating layer formed on the surface of the first conductivity type semiconductor layer and forming an opening to be a first current injection region;
(I) removing a part of the insulating layer formed on the surface of the second conductivity type side electrode and exposing a part of the second conductivity type side electrode;
(J) A method of manufacturing a light emitting device, comprising: a step (j) of forming a first conductivity type side electrode in contact with the first current injection region opened in the step (h).

  2. In the step (g), only the insulating layer in the region including the groove center on the groove bottom surface is removed while leaving the insulating layer formed on the sidewall of the inter-device separation groove. The method described.

  3. In the step (g), all of the insulating layer formed on the bottom surface of the groove in the inter-device separation groove and the insulating layer formed on at least a portion of the side wall in the inter-device separation groove on the groove bottom surface side. 2. The method according to 1 above, which is removed.

  4). 4. The method according to any one of the above items 1 to 3, wherein the layer constituting the surface exposed by removing the insulating layer is an undoped type.

5). After step (j)
Isolating the substrate in the inter-device separation groove;
The method according to any one of the above items 1 to 4, further comprising the step of joining the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount.

6). After step (j)
Bonding the first conductivity type side electrode and the second conductivity type side electrode to the metal layer on the support and mounting the support on the support; and
Removing the substrate;
The method according to any one of 1 to 4 above, further comprising a step of dividing the support to separate elements.

  7). 7. The method according to any one of 1 to 6 above, wherein the buffer layer and the light uniformizing layer are performed as a part of the thin film crystal layer prior to the formation of the first conductivity type semiconductor layer.

8). When the average refractive index of the substrate at the emission wavelength is expressed as n _sb , the average refractive index of the light uniformizing layer is expressed as n _oc , and the average refractive index of the first conductive semiconductor layer is expressed as n ₁ ,
n _sb <n _oc and n ₁ <n _oc
The method according to any one of 1 to 7 above, wherein the relationship is satisfied.

9. The light emitting wavelength of the light emitting element is λ (nm), the average refractive index of the substrate at the light emitting wavelength is n _sb , the average refractive index of the light uniformizing layer is no _oc , and the physical thickness of the light uniformizing layer is _toc (Nm), and the relative refractive index difference Δ _(oc−sb) between the light homogenization layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × ( _noc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_9. The method according to any one of 1 to 8 above, wherein t _oc is selected so as to satisfy

10. The emission wavelength of the light emitting element is λ (nm), the average refractive index at the emission wavelength of the light homogenizing layer is n _oc , the average refractive index at the emission wavelength of the first conductivity type semiconductor layer is n ₁ , and the light homogenizing layer. the physical thickness and _t oc (nm), the relative refractive index difference of the light uniformizing layer and the first conductivity type semiconductor layer delta a _{(oc-1) Δ (oc} -1) ≡ ((n oc) 2 - ( n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_10. The method according to any one of 1 to 9 above, wherein t _oc is selected so as to satisfy

11. The specific resistance ρ _oc (Ω · cm) of the entire light homogenizing layer is
0.5 ≦ ρ _oc
The light-emitting element according to any one of 1 to 10 above, wherein:

  12 12. The method according to any one of 1 to 11 above, wherein the light homogenizing layer is laminated as a plurality of layers.

13. In the step (j), the first conductivity type side electrode is _adjusted such that the width _{L1w of the} narrowest portion of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. 13. The method according to any one of 1 to 12 above, which is formed.

14 In the step (i), among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer, the width L _{2w of the} narrowest portion is not less than 15 μm. 14. The method according to any one of 1 to 13, wherein a part of the electrode is exposed.

15. 15. The method according to 14 above, wherein the L _2w is 30 μm or more.

  16. Any one of the above 1 to 15, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. The method of crab.

  17. Said 1-16, wherein said second conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ni, Pt, Pd, Mo, Au and combinations of two or more thereof. The method in any one of.

18. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The method according to any one of 1 to 17 above, wherein the method is a single layer.

  19. 19. The method according to any one of 1 to 18 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  20. 20. The method according to 19 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

21. It said _{fluoride, AlF x, BaF x, CaF} x, the method of the 20, wherein the selected from the group consisting of SrF _x and MgF _x.

22. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the light homogenizing layer from the first conductivity type semiconductor layer side is reflected by the light homogenizing layer is represented by R2, and the second insulating layer is formed on the insulating layer. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident from the conductive semiconductor layer side is reflected by the insulating layer is R12, and the light emission of the light emitting element perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. The reflectance at which light having a wavelength is reflected by the insulating layer is R11, and the reflectance at which light having the emission wavelength of the light emitting element that is perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is R1q. When represented,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The method according to any one of the above items 1 to 21, wherein the insulating layer is configured to satisfy all of the above conditions.

23. Any of the above items 1 to 22, wherein the thin film crystal layer is formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ and MgO. The method of crab.

  24. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 24. The method according to any one of 1 to 23 above, wherein an element selected from the group consisting of Al is contained.

25. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The method according to any one of 1 to 24, wherein:

  26. 26. The method according to any one of 1 to 25 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  27. 6. The method according to claim 5, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by soldering.

  28. 7. The method according to claim 6, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having the metal layer by soldering.

  29. 27. The bonding of the first conductivity type side electrode and the second conductivity type side electrode and the metal layer of the submount or the support is performed only by metal solder or metal solder and metal bumps. Or the method according to 28.

30. The sub-mount or support base material of a _{metal, AlN, Al 2 O 3,} Si, glass, SiC, diamond, to any of the above 27 to 29, characterized in that it is selected from the group consisting of BN and CuW The method described.

  31. 31. The method according to any one of 27 to 30 above, wherein a metal layer is not formed at a separation portion between the light emitting elements of the submount or the support.

  32. 6. The method according to 5 above, wherein the surface on the light extraction side of the substrate is not flat.

  33. 7. The method according to 6 above, wherein the light extraction side surface of the buffer layer is not flat.

34. R3 is the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is reflected by the substrate, and the light of the emission wavelength of the light emitting element that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
6. The method according to 5 above, wherein a low reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above condition.

35. R3 is a reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light uniformizing layer is reflected by the buffer layer, and the light emitting element that is perpendicularly incident on the light extraction side space from the buffer layer. When the reflectance at which the light of the emission wavelength is reflected at the interface with the space is represented by R4,
R4 <R3
7. The method according to 6 above, wherein a low reflection optical film is provided on the light extraction side of the buffer layer so as to satisfy the above condition.

  36. 36. The method according to any one of items 1 to 35, wherein the substrate is GaN, and all of the buffer layer is formed of GaN at a temperature of 900 ° C. or higher.

  According to the present invention, there is provided a method for manufacturing a flip-chip mount type semiconductor light emitting device capable of emitting blue or ultraviolet light and having high output, high efficiency, and high brightness uniformity on a light extraction surface. Can be provided.

  In the manufacturing method of the present invention, since process damage in each step in the manufacturing process is eliminated, a highly reliable element can be manufactured without impairing the function of the light emitting element.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”.

Further, in the present invention, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), plasma assist MBE, PLD (Pulsed).
Laser Deposition), PED (Pulsed Electron Deposition), VPE (Vapor Phase Epitaxy), LPE (Liquid
In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth equipment such as the (Phase Epitaxy) method, carrier treatment by subsequent heat treatment, plasma treatment, etc. It is described as thin film crystal growth including activation treatment.

[Description of Embodiment of the Present Invention]
1A to 3D show an embodiment of a typical compound semiconductor light emitting device (hereinafter simply referred to as a light emitting device) manufactured according to the present invention. The light emitting device manufactured by the manufacturing method of the present invention has at least three points according to the manufacturing method: (I) the step shape of the end of the light emitting device, (II) the shape of the insulating layer at the end of the light emitting device, III) Different shapes can be taken in three places, the presence or absence of a substrate.

  (I) About the step shape of the edge part of a light emitting element, it divides roughly by the etching depth at the time of forming an inter-device isolation groove in process (e) of a manufacturing method, (i) to the middle of a light uniformization layer, There are three options: (ii) halfway through the buffer layer, (iii) up to the substrate surface (or deeper). In addition, since the wall surface of the inter-device isolation groove recedes from the element end after element isolation, in the present invention, the surface that appears as the side wall surface when forming the inter-device isolation groove is referred to as “recessed side wall surface” for the element after element isolation. " Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A step surface is formed at the end of the light emitting element between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end step surface”.

  Corresponding to the depths (i) to (iii) of the inter-device separation grooves, in (i), a part of the light uniformizing layer forms a receding side wall surface with respect to the receding side wall surface of the thin film crystal layer. The remaining (main light extraction direction side) side wall of the light homogenizing layer is a non-retreating side wall surface, and has an end step surface at the end of the light homogenizing layer. Similarly, in (ii), an end step surface exists at the end of the buffer layer. In (iii), both side walls of the light uniformizing layer and the buffer layer constitute receding side wall surfaces (because they become side wall surfaces of the inter-device separation trenches), so that the substrate is exposed when the finished device has a substrate. The end portion becomes an end step surface, and when the substrate does not exist, the end step surface does not exist. Even if this end step surface does not exist, the wall surface of the inter-device separation groove is receded compared to the element end surface when separated without forming the inter-device separation groove. It is referred to as “retreat side wall surface”.

  FIG. 1B, FIG. 1D, FIG. 2B, and FIG. 3B correspond to (i). The shapes corresponding to (ii) are shown in FIGS. 1C, 1E, 2C, 2D, 3C, and 3D. FIG. 1A, FIG. 2A, and FIG. 3A correspond to (iii).

  (II) Regarding the shape of the insulating layer at the end of the light emitting element, in the step (g) of the manufacturing method, (i) the center on the groove bottom surface remains with the insulating layer formed on the side wall of the inter-device separation groove remaining. (Ii) In addition to all of the insulating layer formed on the bottom surface of the groove, the insulating layer including part of the side wall in the groove may be removed. In the light emitting device manufactured as a result, there are two types: (i) a shape in which the insulating layer is attached to the groove bottom surface, and (ii) a shape in which the insulating layer is separated from the groove bottom surface. FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, and FIG. 1E correspond to (i). 2A, 2B, 2C, 2D, 3A, 3B, 3C, and 3D correspond to (ii).

  (III) With regard to the presence or absence of the substrate, there are choices of (i) leaving the substrate on the main light extraction side during the manufacturing process and (ii) removing the substrate. There are two types: i) a form having a substrate and (ii) a form having no substrate. In the case of having a substrate, a substrate transparent to the emission wavelength is used. FIG. 1A, FIG. 1B, FIG. 1C, FIG. 2A, FIG. 2B, FIG. 2C, and FIG. FIGS. 1D, 1E, 3A, 3B, 3C, and 3D correspond to (ii).

  In the combination of (I), (II) and (III), (I): (iii) There is no step in either the light homogenizing layer or the buffer layer, and (II): (i) the side wall of the inter-device separation groove (III): (ii) The substrate is removed by removing only the insulating layer in the region including the center on the bottom surface of the groove while leaving the insulating layer formed on the substrate. Since the substrate is removed from the attached state by peeling or the like, it is not preferable in the present invention.

  About the other point, in the B part and C part in FIG. 1A-FIG. 3D, the positional relationship etc. of an insulating layer and each electrode are the same in any aspect.

  The present invention includes steps (a) to (j), and the order of the steps is shown in the flowchart of FIG. In the present invention, steps (a), (b) and (c) are performed in this order. Steps (d) and (e) are carried out after step (c), but the order of steps (d) and (e) may be either. Then, after implementing step (f), steps (g), (h) and (i) may be performed in any order, but are preferably performed simultaneously. Thereafter, step (j) is performed. Thereafter, the substrate is removed.

  Hereinafter, the manufacturing method of a typical aspect is demonstrated. The material of each constituent member will be described later collectively.

<Embodiment 1>
In Embodiment 1, a method for manufacturing the light-emitting element shown in FIG. 1A will be described.

Step (a) and step (b):
As shown in FIG. 5, first, a substrate 21 is prepared, and a buffer layer 22, a light uniformizing layer 23, a first conductivity type cladding layer 24 as a first conductivity type semiconductor layer, an active layer structure 25, and a second layer are provided on the surface. A second conductivity type cladding layer 26 is sequentially formed as a conductivity type semiconductor layer by thin film crystal growth. The MOCVD method is desirably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, the VPE method, the LPE method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. In addition, various processes may be performed after the formation of the thin film crystal layer. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

Step (c):
After the thin film crystal layer growth, as shown in FIG. 5, the second conductivity type side electrode 27 is formed. That is, the formation of the second conductivity type side electrode 27 in the second current injection region 35 (see FIG. 9) is more effective than the planned formation of the insulating layer 30 (see FIG. 8). This is performed earlier than the formation of the first conductivity type side electrode 28 (see FIG. 10) than the formation of the formation (see FIG. 9). When the p-type electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface when the second conductivity type is p-type as a desirable form, this is compared with GaN-based materials. This is because the hole concentration in the p-GaN clad layer with a low effective activation rate is lowered by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. For this reason, in the present invention, after the thin film crystal growth, the formation of the second conductivity type side electrode is performed in another process step (for example, the first etching step, the second etching step, or the insulating layer forming step described later, the second conductivity type side). The electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, etc.) are performed prior to this.

  In the present invention, when the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. Is a relatively stable metal such as Au, it is unlikely to be damaged by the process even after the subsequent process. Also from this viewpoint, in the present invention, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  In the present invention, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced similarly. it can.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

Step (d):
After forming the second conductivity type side electrode 27, as shown in FIG. 6, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

Step (e):
Next, as shown in FIG. 7, an inter-device separation groove 13 is formed by a second etching process. In this embodiment, the inter-device separation groove 13 is formed so as to reach the substrate 21. In this case, in order to separate the device, the GaN-based material on the sapphire substrate is peeled off even when diamond scribing is performed from the side where the thin film crystal layer is formed in the process of scribing, breaking, etc. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove by etching part of a sapphire substrate (the same applies to other substrates such as GaN). Here, in order to manufacture a light emitting element having a form different from that of FIG. 1A, an inter-device separation groove is formed in the middle of the light uniformizing layer. When the inter-device separation groove is formed up to the middle of the buffer layer and the others are manufactured in the same manner as in Embodiment 1, the light-emitting element of FIG. 1C is obtained. In this case, the bottom surface of the groove is formed in the middle of the combined layer of the light uniformizing layer and the buffer layer, and this becomes an end step surface at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the sum of the layers etched by the first etching step is usually about 0.5 μm. However, in the second etching step, all of the first conductivity type cladding layer 24, the light uniformizing layer 23 and the buffer are formed. Since it is necessary to etch the layer 22, it may exceed 3 μm, for example 3 μm to 7 μm, 3 to 10 μm, even 5 to 10 μm, and sometimes 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching process, a SiN _x mask exceeding 2 μm is required. But when it comes to SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in control of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _21, SiN x, SiO ₂ or the like mask 51, a metal fluoride Even if it does not exist in the entire lower portion of the chemical mask layer 52, it is sufficient if it is formed on a material that is at least susceptible to acid.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIG.

Note that either the first etching step or the second etching step may be performed first. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 21, first, a first etching mask 51 is formed of an acid-resistant material (preferably SiN _x ) such as SiN _x and SiO ₂ , and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the element manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the present invention is a side wall surface that appears as a side wall in the second etching step, that is, when an inter-device separation groove is formed, and is not a wall surface that appears only in the first etching.

Step (f):
After the second etching step, as shown in FIG. 8, the insulating layer 30 is a second conductivity type side electrode 27, a first conductivity type semiconductor layer (first conductivity type cladding layer 24) exposed by the first etching step. And an insulating layer is formed on the entire surface including the inside of the inter-device separation groove 13. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details will be described later. As a film forming method, a known method such as a plasma CVD method may be used.

Step (g), step (h), step (i):
Next, as shown in FIG. 9, in the step (g), the insulating layer 30 on the substrate in the inter-device separation trench 13 is removed to form the scribe region 14. In the step (h), a part of the insulating layer 30 on the first conductivity type cladding layer 24 is removed, and the first current injection region 36 is formed. In step (i), a part of the insulating layer 30 on the second conductivity type side electrode 27 is removed to form a second conductivity type side electrode exposed portion 37. Preferably, steps (g), (h) and (i) are performed simultaneously.

In the first embodiment, in the step (g), not all the insulating layer 30 deposited on the surface of the substrate 21 is removed, but only the central portion of the groove is removed, and the insulating layer is formed on the substrate surface on the side wall surface side of the thin film crystal layer. Leave it on. A portion where the insulating layer 30 is removed at the central portion of the groove is used as a scribe region 14 for element division. As shown in FIG. 9, when the width of the scribe region 14 is 2L _ws , L _ws may be larger than 0 in the completed device, but is usually 10 μm or more, preferably 15 μm or more. Therefore, the scribe region width 2L _ws formed in the step (g) is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

In the separated light emitting device, as shown in part A of FIG. 1A, the insulating layer does not cover the entire surface of the substrate surface exposed by retreating the side wall surface of the thin film crystal layer. _It covers the substrate surface (groove bottom surface = end step surface) on the inner side from the position separated by _ws (when divided from the center of the width of the scribe region 14 shown in FIG. 9). By providing a scribe region, the insulating layer does not peel off from the side surface of the thin film crystal layer when the element is split as described later, so that the completed light-emitting element is prevented from being unintentionally short-circuited even if the solder wraps around. The In addition, since the thin film crystal layer is not damaged, a highly reliable element can be formed without impairing the function of the light emitting element.

  In the step (h), a part of the insulating layer 30 on the first conductivity type cladding layer 24 is removed, and the first current injection region 36 is formed.

Further, the removal of the insulating layer 30 on the second conductivity type side electrode 27 in the step (i) is performed so that the peripheral portion of the second conductivity type side electrode is covered with the insulating layer as shown in FIG. To do. That is, the surface area of the exposed portion of the second conductivity type side electrode is smaller than the area of the second current injection region. In order to prevent the occurrence of unintentional short-circuiting due to the margin of the photolithography process, especially the photolithography process, and the occurrence of unintentional short-circuits due to the solder material, the width of the width covered with the insulating layer from the periphery of the second conductivity type side electrode is the most. When the width of the narrow portion is L _2W , L _2W is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material. L _2w is usually 2000 μm or less, preferably 750 μm or less.

In the steps (g), (h), and (i), for the removal of the insulating layer, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer is a single layer of SiN _x , dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

Step (j):
Next, as shown in FIG. 10, the first conductivity type side electrode 28 is formed. In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. The feature is not to. This is because when the element is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while ensuring a sufficient area to ensure sufficient adhesion with the submount or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like. As shown in FIG. 10, when the width of the narrowest portion of the width of the portion where the first conductivity type side electrode is in contact with the insulating layer is L _1w , L _1w is preferably 7 μm or more, particularly 9 μm or more. preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described later, as the electrode material, when the first conductivity type is n-type, it is desirable to include a material selected from any of Ti, Al, and Mo, or all as a constituent element. In addition, Al is usually exposed on the side opposite to the main light extraction direction of the n-side electrode. Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode is formed so as to be in contact with a part of the first conductivity type cladding layer. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact with the first conductivity type side electrode. Can do.

  Thus, since the first conductivity type side electrode is manufactured at the final stage of forming the laminated structure, it is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is preferably formed with Al on the surface of the electrode material. In this case, if the n-side electrode is formed before the formation of the insulating layer like the second conductivity type side electrode, the surface of the n-side electrode, that is, the Al metal, will history the etching process of the insulating layer. . As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching an insulating layer, but Al has low resistance to various etchants including hydrofluoric acid, and such a process is effectively performed. Then, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the present invention, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer is effective in reducing damage to the electrode.

Steps after step (j):
After the structure of FIG. 10 is formed in this way, the inter-device separation grooves are used to separate each compound semiconductor light emitting element one by one, and the substrate is damaged by diamond scribe, and laser Ablation of a portion of the substrate material by scribing is performed.

  In the element isolation step, since there is no thin film crystal layer in the inter-device isolation groove, process damage is not introduced into the thin film crystal layer. In addition, since there is no insulating layer in the scribe region, there is no possibility that the insulating layer is peeled off during scribing. In the embodiment different from that shown in FIG. 1A, the inter-device separation groove may be formed up to the middle of the combined optical homogenization layer and buffer layer. In use, the substrate is damaged by diamond scribing and ablation of a portion of the substrate material by laser scribing is performed.

  After the scribe is completed, the compound semiconductor light-emitting element is divided into elements one by one in the braking process, and is preferably mounted on the submount 40 with a solder material 42 or the like as shown in FIG. 1A. As described above, the compound semiconductor light emitting device shown in FIG. 1A is completed.

<Embodiment 2>
In Embodiment 2, a method for manufacturing the light-emitting element shown in FIG. 2A will be described.

  In the second embodiment, the steps from the step (a) to the step (f) are the same as those in the first embodiment, and correspond to FIGS.

Step (g), step (h), step (i):
As shown in FIG. 8, after the insulating layer 30 is formed in the step (f), the insulating layer is partially removed by the step (g), the step (h), and the step (i) also in this embodiment. Among these, the step (h) of forming an opening to be the first current injection region and the step (i) of exposing a part of the second conductivity type side electrode are the same as those in the first embodiment. In the present embodiment, the step (g), the step (h) and the step (i) may be performed separately or simultaneously.

  In the step (g) of the second embodiment, as shown in FIG. 11, the insulating layer 30 on the substrate 21 (that is, the groove bottom surface) is completely removed in the inter-device separation groove 13 and formed on the side wall in the groove. The insulating layer on the substrate side (that is, the groove bottom side) of the insulating layer thus formed is removed to form an insulating layer non-formed portion 15. As a forming method, the following process is possible. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device isolation trench 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer. Removal of the insulating layer on the substrate surface in the trench proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer covering the substrate side of the trench sidewall is removed with a wet etchant, and the insulating layer does not exist on the sidewall on the substrate side as shown in FIG. Is obtained.

  The side wall exposed by removing the insulating layer is at least a portion of the side wall of the buffer layer on the substrate side. In some embodiments, the entire side wall of the buffer layer 22 may be exposed. You may expose at least one part of a side wall. When a part of the side wall of the light homogenizing layer 23 is exposed, the side wall of the buffer layer is exposed in FIG. 2A, and the portion where the insulating layer is not formed in FIG. The exposed side wall where the insulating layer is not present is preferably the side wall of the undoped layer. This is because an unintended electrical short circuit does not occur even when solder for joining to the support or the like adheres to the side wall when flip chip mounting is performed. Such a removed shape of the insulating layer is a desirable shape because an unintended defect such as peeling of the insulating layer does not occur accompanying the removal of the substrate, particularly during the manufacturing process of the light emitting element. In addition, when the inter-device separation groove is formed by etching part of the substrate, only the substrate portion of the wall surface of the groove is exposed and the buffer layer may be covered. However, in the case of removing the substrate, the insulating layer is preferably not in contact with the substrate.

Step (j):
In step (j), as shown in FIG. 12, the first conductivity type side electrode 28 is formed in the same manner as in the first embodiment.

Steps after step (j):
Thus, after the structure of FIG. 12 is formed, each compound semiconductor light emitting element is separated in the same manner as in the first embodiment. In the element isolation step, since there is no thin film crystal layer in the inter-device isolation groove, process damage is not introduced into the thin film crystal layer. In addition, since there is no insulating layer in the scribe region, there is no possibility that the insulating layer is peeled off during scribing.

After the scribe is completed, the compound semiconductor light-emitting element is divided into elements one by one in a braking process, and is preferably mounted on the submount 40 with a solder material 42 or the like as shown in FIG. 2A. As described above, the compound semiconductor light emitting device shown in FIG. 2A is completed. In the manufacturing method according to the second embodiment, L _1w and L _2w are preferably set in the same manner as in the first embodiment.

  Also in this embodiment, the same effect as in the first embodiment can be obtained.

<Embodiment 3>
In Embodiment 3, a method for manufacturing the light-emitting element shown in FIG. 3A will be described.

  In the third embodiment, the steps from the step (a) to the step (j) are the same as those in the second embodiment, and the steps after the step (j) are different. However, since the substrate is removed in the third embodiment, the characteristics required for the substrate are different from those in the first and second embodiments when the substrate is prepared in the step (a). This will be described in detail in the material section.

Steps after step (j):
In the present embodiment in which the substrate is peeled off, preparation for removing the substrate is performed after the structure of FIG. 12 is formed. Usually, the entire structure of the wafer shown in FIG. 12 or a part thereof is first bonded to the support 40b. This is because the thickness of the thin film crystal layer as a whole is at most about 15 to 20 μm. Therefore, if the substrate is peeled off, the mechanical strength becomes insufficient and it becomes difficult to stand alone and undergo subsequent processes. Because it becomes.

  Therefore, as shown in FIG. 13, the metal layer 41 (electrode wiring or the like) on the support 40b is connected and mounted by, for example, metal solder 42. At this time, in the light emitting device of the present invention, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged so as not to spatially overlap each other, and the first conductivity type side electrode is the first conductivity type side electrode. Since it is larger than one current injection region and has a sufficient area, it is desirable to prevent both unintentional short-circuiting and ensure high heat dissipation. In addition, the sidewalls of other thin film crystal layers are protected by an insulating layer except at least a part of the buffer layer, and particularly the undoped part. A short circuit or the like on the side wall of the layer structure does not occur.

  Next, after bonding the element to the support, the substrate is peeled off. Any method such as polishing, etching, or laser debonding can be used for peeling the substrate. When polishing a sapphire substrate, it is possible to remove the substrate using an abrasive such as diamond. It is also possible to remove the substrate by dry etching. Furthermore, for example, when a sapphire is a substrate and a thin film crystal growth portion is formed of an InAlGaN-based material, the sapphire substrate transmits from the sapphire substrate side and is absorbed by GaN used for the buffer layer, for example, 248 nm. It is also possible to carry out laser debonding using an excimer laser having an oscillation wavelength of 1 to decompose part of GaN in the buffer layer into metal Ga and nitrogen and peel off the substrate. FIG. 14 schematically shows a state where the substrate 21 is peeled off by laser debonding.

When using ZnO, ScAlMgO ₄ or the like as a substrate, the substrate can be removed by wet etching using an etchant such as HCl.

  In the third embodiment, since the insulating layer 30 is not in contact with the substrate 21, the insulating layer is not peeled when the substrate is peeled off. Therefore, in addition to ensuring reliable insulation, the thin film crystal layer is not damaged by the tension generated when the insulating layer is peeled off.

  Thereafter, as shown in FIG. 14, the light emitting elements are separated together with the support in the separation region 47 in the support corresponding to the location where the inter-device separation groove exists, thereby obtaining a single light emitting element. Here, if metal wiring is present in the separation region of the support, it is difficult to perform separation between devices. Therefore, it is preferable that a separation region 47 in which no metal wiring is present exists around the support 40b.

  For the cutting of the separation region portion of the support, an appropriate process such as dicing, scribing and braking can be selected depending on the base material. In addition, the inter-device separation groove may be formed up to the middle of the combined layer of the optical homogenization layer and the buffer layer. The diamond scribe is damaged, and a part of the support material is ablated by laser scribe.

Here, if the width of the narrowest portion of the separation region of the support is 2L _WSPT2 , L _WSPT2 may be larger than 0 in the completed device, but usually 10 μm or more, preferably when separating by scribing, preferably 15 μm or more. Therefore, it is preferable that 2L _WSPT2 is 30 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 300 μm or less, preferably 200 μm or less.

Further, when separating by dicing, L _WSPT2 is usually 100 μm or more, preferably 500 μm or more. Therefore, it is preferable that 2L _WSPT2 is 1000 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 2000 μm or less, preferably 1500 μm or less.

  As described above, the light-emitting element of Embodiment 3 illustrated in FIG. 3A is completed.

<Other embodiments>
The processes described in Embodiments 1 to 3 can be combined to produce the forms shown in FIGS. 1B to 1E, 2B to 2D, and 3B to 3D. 1B and 1C can be manufactured by forming the inter-device separation grooves up to the middle of the light uniformizing layer 23 and halfway of the buffer layer 22 in the description of the first embodiment. 1D and FIG. 1E can be manufactured by further combining the substrate removal process described in Embodiment 3 with this embodiment. 2B, 2C, and 2D, the embodiment shown in FIG. 2B is manufactured by forming the inter-device separation groove partway through the light uniformizing layer 23 in the description of the second embodiment. The groove is formed partway through the buffer layer 22, and the shape in which the insulating layer non-formed portion 15 is stopped by the side wall of the buffer layer 22 by side etching corresponds to FIG. 2C and extends to the side wall of the light uniformizing layer 23. The shape corresponds to FIG. 2D. 3B, FIG. 3C, and FIG. 3D, the embodiment of FIG. 3B is manufactured by forming the inter-device separation groove partway through the light uniformizing layer 23 in the description of the third embodiment. The groove is formed partway through the buffer layer 22, and the shape in which the insulating layer non-formed portion 15 is stopped by the side wall of the buffer layer 22 by side etching corresponds to FIG. 3C and extends to the side wall of the light uniformizing layer 23. The shape corresponds to FIG. 3D. In any case, an appropriate etching mask shape may be prepared by photolithography suitable for the planned shape.

  In any form of manufacturing method, there is no first-conductivity-type semiconductor layer, active layer structure, and second-conductivity-type semiconductor layer in the inter-device isolation trench during the element isolation step, so that a thin film crystal that affects performance There is no introduction of process damage to the layer. Further, since there is no insulating layer in the scribe region, there is no possibility that the insulating layer is peeled off at the time of scribing or element separation. Further, by increasing the insulation of the portion exposed on the side wall that is not covered with the insulating layer, for example, an undoped layer can be used to prevent a short circuit due to solder or the like during flip chip mounting.

  As described in the above embodiment, in this manufacturing method, the formation of the thin film crystal layer, the formation of the second conductivity type side electrode, the etching process (first etching process and the second etching process), the formation of the insulating layer, the insulation Removal of the layers (formation of the second conductivity type side electrode exposed portion, formation of the first current injection region, formation of the scribe region, etc.) and formation of the first conductivity type side electrode are performed in this order. There can be obtained a light emitting device in which the thin film crystal layer directly under the second conductivity type side electrode is not damaged and the first conductivity type side electrode is not damaged. The completed element shape reflects the process flow and has a structure in which the second conductivity type side electrode, the insulating layer, and the first conductivity type side electrode are laminated in this order. In other words, the second conductivity type side electrode is in contact with the second conductivity type clad layer (or other second conductivity type thin film crystal layer) without an insulating layer interposed, There is a portion covered with an insulating layer, and an insulating layer is interposed between the first conductivity type side electrode and the first conductivity type cladding layer (or other first conductivity type thin film crystal layer) around the electrode. There is a part.

  Furthermore, the element manufactured by the present invention has the light uniformizing layer 23 in the light extraction direction from the first conductive semiconductor layer (the first conductive clad layer 24 in each embodiment). Although the light homogenizing layer will be described in detail later, it has effects such as moderate light confinement and, in some cases, light scattering, multiple reflection, and thin film interference. The light emitted from the active layer structure 25 is It is distributed throughout the light homogenization layer without being present. Therefore, when viewed from the light extraction surface 50a of the substrate, light is distributed also in a region corresponding to the non-light-emitting portion where there is no active layer for extraction of the first conductivity type side electrode 28, and light is emitted from the active layer. Even if there is unevenness, light is distributed so as to be relatively uniform. Further, since the periphery of the light uniformizing layer 23 is covered with the insulating layer 30, the main light is adjusted by adjusting the reflectance with respect to the emission wavelength of the insulating layer 30 to be high (details will be described in the section of the insulating layer). The emission from the take-out direction can be improved effectively, and as a result, the light emission efficiency of the element itself can be improved. In addition, since the light confinement effect in the light homogenization layer is increased, the in-plane uniformity of the light emission pattern is also improved.

[Explanation of materials]
<Board>
There are some differences in materials that can be used as the substrate between Embodiment 1 and Embodiment 2 in which the substrate remains in the completed light-emitting element and Embodiment 3 in which the substrate does not remain in the completed light-emitting element.

<Substrate used in the embodiment in which the substrate remains in the completed light-emitting element such as Embodiment 1 and Embodiment 2>
The material of the substrate 21 is not particularly limited as long as it is optically approximately transparent with respect to the light emission wavelength of the element. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if there is absorption, the light output is not reduced by 50% or more due to absorption of the substrate.

The substrate is preferably an electrically insulating substrate. This is because when flip chip mounting is performed, even if a solder material or the like adheres to the periphery of the substrate, current injection into the light emitting element is not affected. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less This is desirable from the viewpoint of electrical resistance and crystallinity.

  The substrate used in the present invention is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. it can. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when using a c + plane substrate of sapphire as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture a compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. Also, the substrate is intentionally roughened in relation to the buffer layer, which will be described later, so that the threading transition that occurs at the interface between the thin film crystal layer and the substrate is not introduced near the active layer of the light emitting element. It is also possible to make it.

In the present invention, since the light is confined in the light homogenization layer described later and guided so as to be distributed in the layer at the same time, the substrate has a refractive index (n _sb ) at the emission wavelength of the compound semiconductor light emitting device, It is desirable that it is relatively smaller than the average refractive index (n _oc ) of the light homogenizing layer.

  In one embodiment, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication so that the crystal growth of the semiconductor light emitting device and the mechanical strength in the device fabrication process are ensured. It is normal to leave. In order to make it easy to separate each element after growing a thin film crystal layer using this, it is appropriately thinned in the middle of the process by a polishing process, and finally the light emitting element has a thickness of about 100 μm or less. Is desirable. Moreover, it is the thickness of 30 micrometers or more normally.

  In a further different embodiment, the thickness of the substrate may be thicker than before, and may be about 350 μm, further about 400 μm, or about 500 μm.

In addition, when a substrate is selected so as to be a relatively low refractive index layer relative to the waveguide in order to confine light in a light homogenizing layer, which will be described later, and to guide the light, the emission wavelength of the light emitting element is set to λ (nm ) When the average refractive index of the substrate is expressed by n _sb , it is desirable that the physical thickness of the substrate is thicker than 4λ / _nsb .

Furthermore, it is desirable that a so-called low-reflection coating layer or low-reflection optical film is formed on the surface in the main light extraction direction of the substrate. Reflection due to a difference in refractive index at the substrate-air interface can be suppressed, so that high output and high efficiency of the device can be achieved. Here, R3 is the reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the substrate side from the buffer layer is reflected by the substrate, and the light having the light emission wavelength of the light emitting element perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
It is preferable that a low reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above. For example, when the substrate is sapphire, it is desirable to use MgF ₂ or the like as the low reflection coating film. Relative refractive index n _s of the substrate at the emission wavelength, the refractive index of the low reflecting coating film, since it is desirable near √n _s, relative to the square root of the refractive index of the sapphire, the refractive index of MgF ₂ are close It is.

In the present embodiment, it is also preferable that the surface in the main light extraction direction of the substrate is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Further, when the emission wavelength of the element is λ (nm), the roughness of the rough surface is the average roughness Ra (nm).
λ / 5 (nm) <Ra (nm) <10 × λ (nm)
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

<Substrate used in the embodiment in which the substrate does not remain in the completed light emitting device such as Embodiment 3>
In the present embodiment, a substrate capable of growing a semiconductor layer thereon is selected, and a substrate that can be finally removed is used. The substrate need not be transparent, but when the substrate is peeled off by laser debonding, which will be described later, in the manufacturing process, it is preferable to transmit laser light having a specific wavelength. Further, it is preferably an electrically insulating substrate. This is because, in the manufacturing process, when the substrate is similarly peeled by the laser debonding method, such a substrate peeling method cannot be adopted by the conductive substrate due to absorption by free electrons.

All the substrate materials that can be used in the first embodiment and the second embodiment can also be used in the third mode. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less This is desirable from the viewpoint of electrical resistance and crystallinity. When chemical etching is premised when removing the substrate, ZnO that can be easily removed with hydrochloric acid or the like is preferable.

  Further, as described in the first and second embodiments, the off-substrate can be used, the substrate may be subjected to chemical etching or heat treatment in advance, and the substrate is intentionally uneven. The points that may be attached are also the same.

  In one embodiment of this embodiment, the thickness of the substrate is usually about 250 to 700 μm in the initial stage of device fabrication, so that the mechanical strength in the semiconductor crystal growth and device fabrication process is ensured. It is normal to keep it. After the necessary semiconductor layer is grown using the substrate, the substrate is removed by, for example, polishing, etching, laser debonding, or the like. In particular, when the film is peeled off by an optical method such as laser debonding, it is desirable to use a double-sided polished substrate during the growth of a thin film crystal. This is because if a single-side polished substrate is used for a laser irradiated from a surface on which no thin film crystal is grown, it will be incident from a rough surface, and an unnecessarily large laser output is required during laser debonding. It is.

<Buffer layer>
Regarding the buffer layer, there are some differences between Embodiments 1 and 2 in which the substrate remains in the completed light-emitting element and Embodiment 3 in which the substrate does not remain in the completed light-emitting element.

<The form of the buffer layer common to all forms, such as Embodiment 1-3>
The buffer layer 22 mainly grows a thin film crystal on the substrate, suppresses transition, alleviates the imperfection of the substrate crystal, and reduces various mismatches between the substrate crystal and the desired thin film crystal growth layer. Formed for the purpose of thin film crystal growth.

  The buffer layer is formed by thin-film crystal growth, and an InAlGaN-based material, an InAlBGaN-based material, an InGaN-based material, an AlGaN-based material, an AlN-based material, a GaN-based material, or the like, which is a desirable form in the present invention, is formed on a different substrate. When growing, the buffer layer is particularly important because the lattice constant matching with the substrate is not necessarily ensured. For example, when a thin film crystal growth layer is grown by metal organic vapor phase epitaxy (MOVPE method), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or a low temperature growth GaN layer formed near 500 ° C. Can also be used. Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer 22 is not necessarily a single layer, and a GaN layer grown at a temperature of about 1000 ° C. without doping is further formed on the GaN buffer layer grown at a low temperature in order to improve the crystallinity. You may make it have about several micrometers. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. The buffer layer may be doped with Si or the like, or may be formed by stacking a doped layer and an undoped layer in the buffer layer.

  As a typical embodiment, a low-temperature buffer layer in which a thin film crystal is grown at a low temperature of about 350 ° C. to less than 800 ° C. in contact with the substrate, and a high-temperature buffer layer in which a thin film crystal is grown at a high temperature of about 800 ° C. to 1050 ° C. The thing of a 2 layer structure is mentioned. When the substrate is GaN, all of the buffer layer can be GaN formed at a high temperature of 900 ° C. or higher.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to the present invention. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  In the completed device, as already described, at least the vicinity of the substrate side (the substrate side when the buffer layer is formed) of the sidewall surface of the buffer layer is not covered with the insulating layer.

  In the present invention, the buffer layer may be integrated with a light homogenizing layer described later to realize light confinement in order to increase the uniformity of light intensity on the light extraction surface. Further, part or all of the buffer layer may also serve as the light uniformizing layer.

  The buffer layer may be an exposed portion of the inter-device separation groove. In particular, it is preferable that the undoped portion is exposed because insulation failure due to solder or the like during device assembly can be suppressed.

<Form of Buffer Layer Specific to Aspect That No Substrate Is Remaining in Embodiment 3>
In Embodiment 3, in order to confine and guide light in a light homogenizing layer to be described later, the refractive index of the buffer layer at the emission wavelength of the light emitting element is equal to or less than the average refractive index of the light homogenizing layer, preferably It is less than the average refractive index of the light homogenizing layer. The physical thickness of the buffer is desirably thicker than 4λ / n _bf , where λ (nm) represents the emission wavelength of the light emitting element and n _bf represents the average refractive index of the buffer.

  In the third embodiment, since the substrate is removed during the manufacturing process, the buffer layer becomes the main light extraction surface. As described above, as one method of peeling the substrate, a method of peeling the substrate by optically decomposing a part of the buffer layer using light that is transparent to the substrate and absorbs the buffer layer Is mentioned. When such a method is adopted, a material suitable for the method is selected. For example, when the substrate is sapphire and the buffer layer is GaN, an excimer laser having an oscillation wavelength of 248 nm is irradiated from the substrate side on which no thin film crystal is grown, and the buffer layer GaN is made of metal Ga and nitrogen. It is also possible to carry out laser debonding in which the substrate is peeled off as a result.

In this embodiment, since there is no substrate in the main light extraction direction, it is desirable that a so-called low reflection coating layer or low reflection optical film is formed on the surface of the buffer layer in the main light extraction direction. Reflection due to a difference in refractive index at the buffer layer-air interface can be suppressed, and higher output and higher element efficiency can be achieved. Here, the reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light homogenizing layer, which will be described later, is reflected by the buffer layer is R3, and the light is perpendicularly incident on the light extraction side space from the buffer layer. When the reflectance at which the light of the emission wavelength of the light emitting element is reflected at the interface with the space is represented by R4,
R4 <R3
It is desirable to provide a low reflection optical film on the light extraction side of the buffer layer so as to satisfy the above. For example, when the buffer layer is GaN, it is desirable to use Al ₂ O ₃ or the like as the low reflection coating film. This is because it is desirable that the refractive index of the low-reflection coating film is close to √n _bf with respect to the refractive index n _bf of the buffer layer at the light emission wavelength of the device, so that Al ₂ O with respect to the square root of the refractive index of GaN. _{This is because} the refractive index of ₃ is close.

In the present embodiment, it is also preferable that the main surface in the light extraction direction of the buffer layer is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Here, when the light emission wavelength of the element is λ (nm), the degree of roughness of the buffer layer is such that the average roughness Ra (nm) is:
λ / 5 (nm) <Ra (nm) <10 × λ (nm)
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

  In this form, at least a portion of the buffer layer is exposed at the device edge. Therefore, at least the exposed portion is preferably an undoped portion, since insulation failure due to solder or the like during device assembly can be suppressed.

<Light homogenization layer>
The light homogenizing layer according to the present invention guides light emitted from the active layer structure once by confining it in the layer and distributing it while leaking a part of the light. This is a layer that exhibits effects such as scattering, multiple reflection, and thin film interference, and improves uniformity on the light extraction surface of the light emitting element.

  The light uniformizing layer 23 is preferably formed of a compound semiconductor layer, and is present between the buffer layer and the first conductivity type semiconductor layer (first conductivity type cladding layer) as shown in FIGS. Is desirable. In addition, the film forming method is not particularly limited, but it is desirable to use a thin film crystal growth technique simultaneously with other thin film crystal layers in order to easily manufacture a semiconductor light emitting element.

In the present invention, the refractive index of the light homogenizing layer is selected so that light is confined at least in the layer, that is, the light distribution density is increased. Therefore, the average refractive index (n _oc ) of the light uniformizing layer is larger than the average refractive index of the first conductivity type cladding layer, and in an embodiment with the substrate, it is larger than the average refractive index (n _sb ) of the substrate. In particular, it is preferable that the average refractive index (n ₁ ) of the first conductivity type semiconductor layer existing between the light homogenizing layer and the active layer structure be larger. Moreover, it is more than the average refractive index ( _nbf ) of a buffer layer, and it is preferable that it is especially larger than the average refractive index of a buffer layer. In addition, the material constituting the light homogenizing layer is particularly preferably transparent to light emitted from the quantum well layer. In the case of a light emitting device based on a group III-V nitride such as InAlGaN, it is desirable to contain In or Al to such an extent that light emitted from the active layer structure is not absorbed. It is preferable to contain.

  Further, the light homogenizing layer does not need to be a single layer, and may be composed of a plurality of layers. When composed of a plurality of layers, for example, a plurality of layers such as AlGaN, InGaN, InAlGaN, AlN, and GaN may exist, or a superlattice structure may be used. In addition, a structure such as a quantum dot may be included, and in the case of having a size approximately equal to the emission wavelength of the element, it is possible to induce light scattering. Furthermore, the light uniformizing layer is grown into a thin film crystal, the crystal growth is interrupted once, and the surface is appropriately roughened, etc., and further thin film crystal growth is performed to appropriately scatter light, multiple reflections, thin film interference, etc. It is also possible to cause

Here, the average refractive index (nav) of each layer is the product of the refractive index (nx) of each of the n types of materials constituting the layer and the physical thickness (tx) of the material. Is divided by the total thickness,
nav = (n1 × t1 + n2 × t2 +... + nn × tn) / (t1 + t2 +... + tn)

As an example of the light uniformizing layer, for example, the active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is n-GaN, and the buffer layer Is undoped GaN and the substrate is sapphire, a single layer of undoped GaN can be used as the light uniformizing layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When the undoped GaN and Si-doped GaN laminated structure and the substrate are sapphire, a single-layer undoped GaN can be used as the light uniformizing layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When undoped GaN and Si-doped GaN are laminated, and the substrate is Si-doped GaN, In _b Ga _1-b N having a composition transparent to the emission wavelength is desired in the thick undoped GaN as the light uniformizing layer A multilayer structure having a desired number of thicknesses can be used. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

In such a structure, it is desirable that the light homogenizing layer further includes materials such as In _b Ga _1-b N and In _c Al _d Ga _1-cd N, and the composition b, c, d N-GaN that is transparent at 460 nm and may be included in the first conductivity type semiconductor layer, undoped GaN that may be included in the buffer layer, and may be included as a substrate by appropriately selecting the thickness and the like Since the refractive index can be made larger than that of sapphire, GaN, etc., it can be used as a light uniforming layer, and they may be used as a single layer or as a plurality of laminated structures selected from them and an undoped GaN layer.

  It is also preferable that the light homogenizing layer has a superlattice / quantum well structure composed of an InGaN layer and a GaN layer in which the In composition and the thickness of the InGaN layer are set so as not to absorb the emission wavelength of the compound semiconductor light emitting device.

  It is also important that the thickness of the light homogenizing layer is selected so that it functions as a multimode optical waveguide that receives a part of the light emitted from the quantum well layer and propagates the light in the layer.

The physical thickness of the light homogenizing layer is represented by t _oc (nm), the emission wavelength of the light emitting element is λ (nm), the average refractive index of the light homogenizing layer is n _oc , and the average refractive index of the first conductivity type semiconductor layer _Is expressed as n ₁ , and the average refractive index of the substrate is expressed as n _sb , the relative refractive index difference Δ _(oc−1) between the light uniformizing layer and the first conductive type semiconductor layer is expressed as Δ _(oc−1) ≡ ((n ^{_{oc) 2 - (n 1)}} 2) / (2 × (n oc) 2)
It is defined as Further, the relative refractive index difference Δ _(oc−sb) between the light uniformizing layer and the substrate is expressed by Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
It is defined as If the light uniformizing layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the first conductivity type semiconductor layer, the condition for the waveguide to be multimode is that the normalized frequency is π / 2 or more. (√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc be selected to satisfy More preferably, a thicker waveguide may be used.
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ 2 × π
It is desirable that t _oc be selected to satisfy

In Embodiments 1 and 2 in which the substrate remains in the completed light-emitting element, a condition that the waveguide becomes multimode when the light uniformizing layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the substrate. Since the normalized frequency only needs to be π / 2 or more, (√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc is selected so as to satisfy. Also in the third embodiment, there is no problem in using a substrate on which a thin film crystal is grown that satisfies such conditions.

  Specifically, for example, if the average refractive index of the light uniformizing layer is 2.50 and the average refractive index of the substrate is 1.70 at a wavelength of 460 nm, the thickness of the light uniformizing layer is about 0. If it is .13 μm or more, the above formula is satisfied. For example, if the average refractive index of the light uniformizing layer is 2.50 at the wavelength of 460 nm and the average refractive index of the first conductive semiconductor layer is 2.499, the thickness of the light uniformizing layer is as follows: If it is about 3.3 μm or more, the above formula is satisfied. As described above, the thickness of the light uniformizing layer can be appropriately selected depending on the average refractive index of the substrate, the average refractive index of the light uniformizing layer, and the average refractive index of the first conductivity type semiconductor layer when the substrate is provided. However, generally, 1 to 7 μm is preferable, and 3 to 5 μm is more preferable.

  In this way, light confinement and gentle leakage are realized, and depending on the structure, a light emitting device is realized by realizing a multimode waveguide that also exhibits effects such as light scattering, multiple reflection, and thin film interference. Makes it easier to achieve uniform light emission on the light extraction surface.

  Note that if light is extremely confined in the light homogenization layer, the light emitting element improves the uniformity of light emission but makes it difficult to extract light. Therefore, the thickness, material, structure, configuration, and refraction of the light homogenization layer are difficult. It is preferable to appropriately select a ratio and the like so that wave guide is generated while being leaky to some extent. In particular, regarding the thickness, it is not desirable that the thickness of the light uniformizing layer is extremely increased and the optical confinement of the waveguide is excessive. For example, the upper limit is preferably 30 μm or less, and is preferably 10 μm or less. More desirably, it is most desirably 5 μm or less.

Regarding the insulating property / conductivity of the light uniformizing layer, the allowable range varies depending on whether or not the insulating layer 30 covers the side wall of the light uniformizing layer 23. That is, when the insulating layer 30 covers the side wall of the light homogenizing layer 23 as shown in FIGS. 1A and 2, the insulating layer 30 may be either conductive or insulating. When at least a part of the side wall of 23 is not covered with an insulating layer, it is extremely preferable to be insulative in order to prevent a short circuit due to solder or the like. For example, the specific resistance ρ _oc (Ω · cm) of the entire layer is preferably 0.5 (Ω · cm) or more. More preferably, it is 1.0 (Ω · cm) or more, more preferably 1.5 (Ω · cm) or more, and most preferably 5 (Ω · cm) or more. In order to have a high specific resistance, the light uniformizing layer is preferably undoped. Further, in the case where the light homogenizing layer is composed of a plurality of layers, there is no problem as long as there is a partially doped layer between the undoped layers. In this case, the layer adjacent to the first conductivity type semiconductor layer (for example, the first conductivity type clad layer) may have the above specific resistance. In general, in a semiconductor, in a wavelength region transparent to a material, the refractive index of an undoped layer is intentionally doped and the refractive index is higher than that of a layer having a large number of carriers even in the same material. Therefore, the undoped layer is preferable from the viewpoint of optical characteristics and electrical characteristics. In particular, when the light uniformizing layer is an exposed portion at the device end, the exposed portion is preferably an undoped portion. Thereby, the insulation failure by the solder | pewter etc. at the time of apparatus assembly can be suppressed.

  In the present invention, the light homogenizing layer distributes and distributes light, whereas the buffer layer described above serves to reduce various mismatches when crystals grow on the substrate. Is different. However, the same layer may have two functions at the same time. In addition, when the light uniformizing layer or the buffer layer includes a plurality of layers, some layers may have two functions. Furthermore, if the growth method and conditions are different even though the composition is the same, only one function may be provided.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In the exemplary embodiment of the present invention, a first conductivity type cladding layer 24 is present in contact with the light uniformizing layer 23 as shown in FIGS. The first conductivity type clad layer 24 functions together with the second conductivity type clad layer 26 described later to the active layer structure 25 described later to efficiently inject carriers and suppress overflow from the active layer structure. In addition, it has a function for realizing light emission in the quantum well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The first conductivity type semiconductor layer includes a layer doped to the first conductivity type in addition to the above-mentioned layer having a cladding function, for improving the function of the element like a contact layer, or for manufacturing reasons. . In a broad sense, the entire first conductivity type semiconductor layer may be considered as the first conductivity type cladding layer, and in this case, the contact layer and the like can also be regarded as a part of the first conductivity type cladding layer.

  In general, the first conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described later and a material larger than the average band gap of the active layer structure described later. It is preferable. Furthermore, the first conductivity type cladding layer is generally made of a material that forms a so-called type I band lineup in relation to the barrier layer in the active layer structure. Under such guidelines, the first conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure, and the like prepared for realizing a desired emission wavelength.

  For example, when C + plane sapphire is used as the substrate and a laminated structure of GaN grown at a low temperature and GaN grown at a high temperature is used as the buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material is used as the first conductivity type cladding layer. A material, an InAlBGaN-based material, or a multilayer structure thereof can be used.

The carrier concentration of the first conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 5 × 10 ¹⁷ cm ⁻³ or more, and most preferably 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and most preferably 7 × 10 ¹⁸ cm ⁻³ or less. Here, when the first conductivity type is n-type, Si is most desirable as a dopant.

  In the example of FIG. 1A, the structure of the first conductivity type cladding layer shows a first conductivity type cladding layer composed of a single layer, but the first conductivity type cladding layer is composed of two or more layers. Also good. In this case, for example, a GaN-based material and an AlGaN-based material, an InAlGaN-based material, an InAlBGaN-based material, or an AlN-based material can be used. Further, the entire first conductivity type cladding layer may be a superlattice structure as a laminated structure of different materials. Furthermore, it is also possible to change the above-mentioned carrier concentration in the first conductivity type cladding layer.

  In the portion of the first conductivity type clad layer that is in contact with the first conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  A part of the first conductivity type cladding layer is etched, and the exposed side wall, the etched part, etc. of the first conductivity type cladding layer are in contact with the first conductivity type side electrode described later. A structure in which all except one current injection region is covered with an insulating layer is desirable.

  In addition to the first conductivity type cladding layer, if necessary, a different layer may exist as the first conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

<Active layer structure>
An active layer structure 25 is formed on the first conductivity type cladding layer 24. The active layer structure is a layer that emits light by recombination of electrons and holes (or holes and electrons) injected from the above-described first conductivity type cladding layer and the second conductivity type cladding layer described later. A structure including a quantum well layer and including a barrier layer disposed adjacent to the quantum well layer or disposed between the quantum well layer and the cladding layer. Here, in order to realize high output and high efficiency, which are one object of the present invention, when the number of quantum well layers in the active layer structure is W and the number of barrier layers is B, B = W + 1 is preferably satisfied. That is, the relationship between the cladding layer and the entire layer of the active layer structure is formed as “first conductivity type cladding layer, active layer structure, second conductivity type cladding layer”, and the active layer structure is defined as “barrier layer, quantum well. It is desirable for high output to be formed as “layer, barrier layer” or “barrier layer, quantum well layer, barrier layer, quantum well layer, barrier layer”. FIG. 15 schematically shows a structure in which five quantum well layers and six barrier layers are stacked.

  Here, in the quantum well layer, the layer thickness is as thin as the de Broglie wavelength in order to express the quantum size effect and increase the luminous efficiency. For this reason, in order to achieve high output, it is desirable to provide not only a single quantum well layer but also a plurality of quantum well layers and separate them into an active layer structure. At this time, a layer that is separated while controlling the coupling between the quantum well layers is a barrier layer. In addition, it is desirable that the barrier layer exists for separation of the cladding layer and the quantum well layer. For example, when the cladding layer is made of AlGaN and the quantum well layer is made of InGaN, a form in which a barrier layer made of GaN exists between them is desirable. This is also desirable from the viewpoint of thin film crystal growth because it can be easily changed when the optimum temperature for crystal growth is different. When the clad layer is made of InAlGaN having the widest band gap and the quantum well layer is made of InAlGaN having the narrowest band gap, InAlGaN having an intermediate band gap can be used for the barrier layer. Furthermore, in general, the difference in the band gap between the cladding layer and the quantum well layer is larger than the difference in the band gap between the barrier layer and the quantum well layer, and considering the efficiency of carrier injection into the quantum well layer, The quantum well layer is preferably not directly adjacent to the cladding layer.

  It is desirable that the quantum well layer is not intentionally doped. On the other hand, it is desirable to dope the barrier layer to reduce the resistance of the entire system. In particular, the barrier layer is preferably doped with an n-type dopant, particularly Si. This is because Mg, which is a p-type dopant, easily diffuses in the device, and it is important to suppress the diffusion of Mg during high output operation. Therefore, Si is effective, and it is desirable that the barrier layer is doped with Si. However, it is preferable not to perform doping at the interface between the quantum well layer and the barrier layer.

  The side wall of the active layer structure of one device is preferably covered with an insulating layer 30 as shown in FIG. 1A. In this case, when flip-bonding the element manufactured according to the present invention, there is an advantage that a short circuit due to solder or the like on the side wall of the active layer structure does not occur.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductivity type cladding layer 26 efficiently injects carriers into the aforementioned active layer structure 25 together with the aforementioned first conductivity type cladding layer 24 and suppresses overflow from the active layer structure. It has a function for realizing light emission in the well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The second conductivity type semiconductor layer includes a layer doped to the second conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire second conductivity type semiconductor layer may be considered as the second conductivity type cladding layer. In that case, the contact layer or the like can also be regarded as a part of the second conductivity type cladding layer.

  In general, the second conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described above and a material larger than the average band gap of the active layer structure described above. It is preferable. Furthermore, the second conductivity type clad layer is generally made of a material that forms a so-called type I band lineup, particularly in relation to the barrier layer in the active layer structure. Under such guidelines, the second conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure and the like prepared for realizing a desired emission wavelength. For example, when C + plane sapphire is used as the substrate and GaN is used as the buffer layer, GaN-based material, AlN-based material, AlGaN-based material, AlGaInN-based material, AlGaBInN-based material, etc. are used as the second conductivity type cladding layer. Can be used. Further, a laminated structure of the above materials may be used. Also, the first conductivity type cladding layer and the second conductivity type cladding layer can be made of the same material.

The carrier concentration of the second conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 4 × 10 ¹⁷ cm ⁻³ or more, and further preferably 5 × 10 ¹⁷ cm ⁻³ or more. × 10 ¹⁷ cm ⁻³ or more is most preferable. Preferably 7 × ¹⁰ 18 ^{cm -3} or less as an upper limit, more preferably 3 × ¹⁰ 18 ^{cm -3} or less, and most preferably 2 × ¹⁰ 18 ^{cm -3} or less. Here, Mg is most desirable as the dopant when the second conductivity type is p-type.

  In the example of FIG. 1A, the structure of the second conductivity type cladding layer shows an example of a single layer, but the second conductivity type cladding layer may be composed of two or more layers. Good. In this case, for example, a GaN-based material and an AlGaN-based material can be used. The entire second conductivity type cladding layer may be a superlattice structure composed of a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the second conductivity type cladding layer.

  In general, in a GaN-based material, when the n-type dopant is Si and the p-type dopant is Mg, the crystallinity of p-type GaN, p-type AlGaN, and p-type AlInGaN is n-type GaN, n It does not reach each of type AlGaN and n-type AlInGaN. Therefore, in device fabrication, it is desirable to implement a p-type cladding layer with poor crystallinity after crystal growth of the active layer structure. From this viewpoint, the first conductivity type is n-type and the second conductivity type is p-type. Is desirable.

  In addition, it is desirable that the thickness of the p-type cladding layer with poor crystallinity (which corresponds to the second conductivity type cladding layer in the case of taking a desirable form) is somewhat thin. In the present invention in which flip chip bonding is performed, the substrate side is the main light extraction direction, so there is no need to consider light extraction from the second-conductivity-type-side electrode side, which will be described later. It is possible to form a membrane electrode. For this reason, it is not necessary to expect current diffusion in the lateral direction in the second conductivity type cladding layer as in face-up mounting, and it is necessary to make the second conductivity type cladding layer thin to some extent from the element structure. Is also advantageous. However, when it is extremely thin, the carrier injection efficiency is lowered, and therefore there is an optimum value. The thickness of the second conductivity type cladding layer can be selected as appropriate, but is preferably 0.05 μm to 0.3 μm, and most preferably 0.1 μm to 0.2 μm.

  In the portion of the second conductivity type clad layer that is in contact with the second conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  It is desirable that the exposed side wall of the second conductivity type cladding layer be entirely covered with an insulating layer except for a second current injection region that realizes contact with the second conductivity type side electrode described later.

  Furthermore, in addition to the second conductivity type cladding layer, a different layer may exist as necessary as the second conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in a portion in contact with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

  In addition, unless it is contrary to the summary of this invention, you may form the layer which does not enter into the above-mentioned category as needed as a thin film crystal layer.

<Second conductivity type side electrode>
The second conductivity type side electrode realizes a good ohmic contact with the second conductivity type nitride compound semiconductor, and becomes a reflection mirror in a good emission wavelength band when flip-chip mounted, When flip chip mounting is performed, good adhesion to a support or the like using a solder material or the like is realized. For this purpose, the material can be selected as appropriate, and the second conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  Further, when the second conductivity type is p-type and the second conductivity-type side electrode side of the second conductivity-type cladding layer is GaN, Ni, Pt, Pd, Mo are used as the materials constituting the second conductivity-type side electrode. , Au, or a material containing two or more elements thereof is preferable. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy.

  In a particularly preferred embodiment, the first layer on the p-side cladding layer side of the second conductivity type side electrode is Ni, and the surface of the second conductivity type side electrode opposite to the p-side cladding layer side is Au. This is because Ni has a large work function absolute value, which is convenient for p-type materials, and Au is preferable as the outermost surface material in consideration of resistance to process damage described later, mounting convenience, and the like.

  The second conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the second conductivity type carrier can be injected. For example, when the second conductivity type side contact layer is provided, the second conductivity type side electrode is in contact with it. Formed.

<First conductivity type side electrode>
The first-conductivity-type-side electrode achieves good ohmic contact with the first-conductivity-type nitride compound semiconductor, and when flip-chip mounted, it becomes a reflection mirror in a good emission wavelength band, When chip mounting is performed, good adhesion to a support with a solder material or the like is realized. For this purpose, a material can be selected as appropriate. The first conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  If the first conductivity type is n-type, the n-side electrode is preferably made of Ti, Al, Mo, or a material containing two or more elements thereof. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy. These are because the absolute value of the work function of these metals is small. In addition, Al is usually exposed on the side opposite to the main light extraction direction of the n-side electrode.

  In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. It is desirable not to. This is because when the light emitting element is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while securing a sufficient area to ensure sufficient adhesion to the support or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like.

  Here, the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is preferably 15 μm or more. This is because a margin is required in the process of forming the first conductivity type side electrode, which is preferably formed by a photolithography process and a lift-off method.

  The first conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the first conductivity type carrier can be injected. For example, when the first conductivity type side contact layer is provided, the first conductivity type side electrode is in contact with it. Formed.

<Insulating layer>
When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer”. The structure and shape are as described above.

The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation. For example, single layer oxides, nitrides, fluorides and the like are preferable. Specifically, SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF It is preferably selected from _{x 1} , CaF _x , SrF _x , MgF _{x and the} like. These can secure insulating properties stably over a long period of time.

On the other hand, the insulating layer 30 can be a multilayer film of an insulator. Since this is a dielectric multilayer film, by appropriately adjusting the refractive index of the dielectric in the insulating layer, so-called high reflection having a relatively high optical reflectivity with respect to the light generated in the light emitting element. The function of the coating can also be expressed. For example, when the center value of the light emission wavelength of the element is λ, SiO _x and TiO _x are laminated to have an optical thickness of λ / 4n (where n is the refractive index of each material at the wavelength λ). Thus, it is possible to realize high reflection characteristics. In this way, when the chip is flip-chip bonded, it is possible to increase the light extraction efficiency in the main extraction direction, and an unintentional short circuit caused by soldering materials, etc. It is very desirable to prevent both of them.

Specifically, the reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the light uniformizing layer from the first conductive type semiconductor layer side including the first conductive type cladding layer is reflected by the light uniformizing layer is represented by R2. The reflectivity at which the light having the emission wavelength of the light emitting element perpendicularly incident from the second conductive type semiconductor layer side including the second conductive type cladding layer on the insulating layer is reflected by the insulating layer is represented by R12, and the reflectance on the insulating layer is represented by R12. An active layer structure in which the light having the emission wavelength of the light emitting element that is perpendicularly incident from the side of the first conductive type semiconductor layer including the one conductive type cladding layer is reflected by the insulating layer as R11, and the insulating layer includes a quantum well layer When the light having the emission wavelength of the light emitting element perpendicularly incident from the side is reflected by the insulating layer and is represented by R1q,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
It is preferable that the insulating layer is configured so as to satisfy at least one of the conditions, in particular, all of the expressions 1 to 3.

These are desirable ranges for an insulating layer formed of a dielectric multilayer film to function efficiently as an optical reflecting mirror. Further, considering the stability of the material and the range of refractive index, it is desirable that the dielectric film contains fluoride, and specifically, AlF _x , BaF _x , CaF _x , SrF _x , MgF It is desirable that any of _x is included.

<Submount and support>
There are some differences in the functions and shapes required for the submount or the support between Embodiments 1 and 2 in which the substrate remains in the completed light-emitting element and Embodiment 3 in which the substrate does not remain in the completed light-emitting element.

<Submount used in the embodiment in which the substrate remains in the completed light-emitting element such as the first and second embodiments>
The submount 40 in the present embodiment has a metal layer and has both functions of current injection and heat dissipation to the flip chip mounted device. The base material of the submount is preferably one of metal, AlN, SiC, diamond, BN, and CuW. These materials are desirable because they are excellent in heat dissipation and can effectively suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as submount base materials. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric or the like, SiNx formed by various CVD methods, SiO ₂ or the like is desirable.

  The light emitting element is bonded to the metal layer of the submount by various solder materials and paste materials. In order to sufficiently secure heat dissipation for high output operation and high efficiency light emission of the element, it is particularly desirable to join with metal solder. Examples of the metal solder include In, InAg, PbSn, SnAg, AuSn, AuGe, and AuSi. These solders are stable and can be appropriately selected in light of the operating temperature environment.

  It is also possible to mount a plurality of compound semiconductor light emitting elements of this embodiment on one submount. By freely changing the metal wiring on the submount, each light emitting element on one submount can be changed. These can be connected in parallel, in series, or mixed.

<Support used in embodiment in which substrate is not left on completed light-emitting device such as embodiment 3>
It is essential that the support 40b used in this embodiment can serve as a support for the thin film crystal layer when the substrate is peeled off. It is also highly desirable to have both functions. From this viewpoint, the base material of the support is preferably selected from the group consisting of metal, AlN, SiC, diamond, BN, and CuW. These materials are preferable in that they are excellent in heat dissipation and can efficiently suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as a support. In addition, when a portion of the thin film crystal layer is decomposed into metal Ga and nitrogen by laser irradiation when removing the substrate, which will be described later, it is desirable to perform wet etching when removing the metal Ga. The body is preferably made of a material that is not etched. Furthermore, it is possible to wet-etch the substrate itself, and it is desirable that the support is made of a material that is not etched. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, the top covered with a dielectric or the like, SiNx formed by various CVD methods, SiO ₂ or the like is desirable.

  From the viewpoint that the support further has functions of current introduction and heat dissipation after completion of the element, it is desirable that the support has electrode wiring for current introduction on the base material, and the device is mounted on this electrode wiring. It is desirable that the mounting portion has an adhesive layer for joining the device and the support as appropriate. Here, although it is possible to use a paste containing Ag, a metal bump, or the like as the adhesive layer, it is very desirable from the viewpoint of heat dissipation that it is made of metal solder. The metal solder can realize a flip chip mount that is overwhelmingly excellent in heat dissipation compared with a paste material containing Ag, a metal bump, and the like. Here, examples of the metal solder include In, InAg, InSn, SnAg, PbSn, AuSn, AuGe, and AuSi. In particular, a high melting point solder such as AuSn, AuSi, or AuGe is more desirable. This is because when a large current is injected to operate the light emitting element at an ultrahigh output, the temperature in the vicinity of the element rises to about 200 ° C. The melting point of the solder material is higher than the element temperature during driving. The metal solder which has is more preferable. In some cases, it is also desirable to use bumps in order to cancel out the level difference of the elements at the time of flip chip mounting, and further to join the metal solder material while filling the periphery thereof. In the third embodiment, as described above, element separation is performed by dividing the support.

  An embodiment in which the support is not divided is also possible. For example, a plurality of light emitting elements can be mounted on one support. Further, by freely changing the metal wiring on the support, each light emitting element on one support can be connected in parallel, connected in series, or mixed together.

  The features of the present invention will be described more specifically with reference to the following examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

Example 1
A light-emitting element shown in FIG. 16 (similar to FIG. 1A) was manufactured by the following procedure. 5 to 10 will be referred to as related process diagrams.

A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a thickness of 10 nm is formed as a first buffer layer 22a on the first buffer layer 22a by using the MOCVD method. As the second buffer layer 22b, an undoped GaN layer having a thickness of 0.5 μm and a Si-doped (Si concentration: 7 × 10 ¹⁷ cm ⁻³ ) GaN layer having a thickness of 0.5 μm were stacked at 1040 ° C. Subsequently, an undoped GaN layer having a thickness of 3.5 μm was formed as the light uniformizing layer 23 at 1035 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 3 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and the first conductivity type (n-type) first cladding layer 24 a is Si-doped (Si concentration 1.5 × A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps so far generally corresponds to FIG. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as the second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches All of the thin film crystal layers of the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, the undoped GaN light uniformizing layer 23, and the undoped GaN buffer layer 22 Was subjected to ICP etching using Cl ₂ gas. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, a dielectric multilayer film of SiN _x and SiO _x was formed as an insulating layer on the entire surface of the wafer by p-CVD. At this time, SiN _x and SiO _x are formed one layer at a time so that the optical wavelength is 1/4 with respect to the light emission wavelength of the device, and have a relatively high reflectance with respect to the light emission wavelength. I made it. The structure completed through the steps up to here generally corresponds to FIG.

Next, formation of the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of the n-side current injection region (36) on the n-side contact layer 24c, and formation of the scribe region 14 in the inter-device isolation trench First, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) on which the resist mask was not formed with a hydrofluoric acid-based etchant was removed. Here, the periphery of the p-side electrode 27 was covered with an insulating layer made of SiN _x and SiO _x of 150 μm. The width of the scribe region (the _{L WS} in the device after separation 50 [mu] m) 100 [mu] m was formed to have a.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another production example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this example was obtained. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIG.

Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each compound semiconductor light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. At this time, an unintended short circuit or the like of the element did not occur.

(Example 2)
The light emitting element shown in FIG. 17 (similar to FIG. 2A) was manufactured in the following procedure.

  Example 1 was repeated until the dielectric multilayer film was formed as an insulating layer on the entire surface of the wafer (generally corresponding to FIG. 8).

Next, formation of the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of the n-side current injection region 36 on the n-side contact layer 24c, and the side wall of the undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the substrate 21 side, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) that was not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Further, the dielectric multilayer film (insulating layer) at a part of the side wall of the undoped buffer layer 22 was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 was covered with an insulating layer made of SiN _x and SiO _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps so far generally corresponds to FIG.

  Next, the n-side electrode 28 was formed in the same manner as in Example 1. The structure completed through the steps up to here generally corresponds to FIG.

Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. At this time, an unintended short circuit or the like of the element did not occur.

(Example 3)
The light emitting element shown in FIG. 18 (similar to FIG. 3A) was manufactured in the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C.

As the light uniformizing layer 23, an undoped GaN layer having a thickness of 2 μm including a laminated structure of 10 layers each having an undoped In _0.05 Ga _0.95 N layer of 3 nm thickness and an undoped GaN layer of 12 nm thickness was formed. Here, the undoped GaN layer was grown at 850 ° C., and the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The well layers were alternately formed so that the total number of well layers was three and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Then, in order to implement the second etching step of forming a device separation trench, using a vacuum deposition method to form a SrF ₂ mask to the whole wafer surface. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. Active layer structure 25 composed of layers, n-AlGaN first cladding layer 24a, n-GaN contact layer 24c, n-GaN second cladding layer 24b, undoped InGaN / GaN light homogenizing layer 23 and undoped GaN buffer layer 22 All thin film crystal layers were ICP etched using Cl ₂ gas. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Also here, Au was exposed on the surface of the p-side electrode, so that the p-side electrode was not altered at all by this process.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method.

Next, the formation of the p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, the formation of the n-side current injection region 36 on the n-side contact layer 24c, and the side wall of the undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer present on the substrate side portion, a resist mask was formed using a photolithography technique. Next, the insulating layer not covered with the resist mask was removed with a hydrofluoric acid-based etchant. Further, the insulating layer on the substrate side portion of the side wall of the undoped buffer layer was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 was covered with an SiN _x insulating layer of 150 μm. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Subsequently, in order to form the n-side electrode 28, a resist pattern was formed by preparing for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40b. The entire wafer (the thin film crystal growth layer of the substrate 21, the electrode, the insulating layer, etc.) on which the light emitting element was built was bonded to this support using AuSn solder. At the time of bonding, the wafer on which the support 40b and the light emitting element are formed is heated to 300 ° C. so that the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. did. At this time, an unintended short circuit or the like of the element did not occur.

  Next, in order to perform substrate peeling, a KrF excimer laser (wavelength 248 nm) was irradiated from the surface of the substrate 21 where thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, an element isolation region portion in the support was cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the compound semiconductor light emitting device shown in FIG. 18 was completed.

(Examples 4 to 6)
In Examples 1 to 3, Examples 1 to 3 were repeated except that the thin film crystal layer was formed as follows after the light uniformizing layer 23 was formed. That is, after the light uniformizing layer 23 is formed, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm as the first conductivity type (n-type) second cladding layer 24b. A Si-doped (Si concentration: 8 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm as the first conductivity type (n-type) contact layer 24c, and the first conductivity type (n-type) first cladding is further formed. As the layer 24a, a Si-doped (Si concentration: 5.0 × 10 ¹⁸ cm ⁻³ ) Al _0.10 Ga _0.90 N layer having a thickness of 0.1 μm was formed. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, the light emitting device was completed in the same manner as in Examples 1 to 3. At this time, an unintended short circuit of the element did not occur.

In the processes of Examples 1, 2, 4, and 5, the SiN _x mask was removed after the first etching step, but it may be removed after the second etching step without removing the SiN _x mask.

  Further, by stopping the etching in the second etching step in the middle of the light homogenization layer or the buffer layer, a light emitting element having a step in the light homogenization layer or the buffer layer at the end of the element can be manufactured (however, Insulating layer is a multilayer dielectric film). At that time, an appropriate etching mask shape is prepared by photolithography suitable for the planned shape, and the shape in which the insulating layer is removed from the bottom surface of the device isolation groove by proceeding side etching of the insulating layer, or Prepare a suitable etching mask shape by photolithography suitable for the planned shape and do not proceed with side etching of the insulating layer, thereby forming a scribe region while leaving the insulating layer at a part of the groove bottom surface. It is also possible.

(Example 7)
The light emitting element shown in FIG. 1C was manufactured by the following procedure. A c + -plane GaN substrate 21 (Si concentration: 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 330 μm was prepared, and an undoped GaN layer having a thickness of 1 μm was first formed as a buffer layer at 1040 ° C. using the MOCVD method. . Subsequently, 4 μm of undoped GaN including a laminated structure of 20 layers each of undoped In _0.05 Ga _0.95 N of 3 nm and undoped GaN of 12 nm as the light uniformizing layer 23 was formed. Here, the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C., the adjacent undoped GaN layer was grown at 850 ° C., and the other GaN layers were grown at 1035 ° C.

Next, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 5 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. Si-doped (Si concentration 8 × ¹⁰ 18 ^{cm -3)} of the GaN layer was formed to 0.5μm thick, Si-doped (Si concentration: 5 × ^{10 18} as a further first conductivity type (n-type) first cladding layer 22a as A cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.05 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The well layers were formed alternately so that the total number of well layers was 7 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.05 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Then, in order to implement the second etching step of forming a device separation trench, using a vacuum deposition method to form a SrF ₂ mask to the whole wafer surface. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. The active layer structure 25 composed of layers, the n-AlGaN first cladding layer 24a, the n-GaN contact layer 24c, and the n-GaN second cladding layer 24b, and the middle part of the undoped GaN buffer layer 22, Cl ₂ gas is supplied. ICP etching was used. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method. Next, a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, an n-side current injection region on the n-side contact layer, and a scribe region 14 for an inter-device isolation trench are formed at the same time. For this purpose, first, a resist mask was formed using a photolithography technique, and then an insulating layer in a portion not covered with the resist mask was removed using RIE plasma of SF ₆ gas. Here, the periphery of the p-side electrode was covered with a SiN _x insulating layer. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Subsequently, in order to form the n-side electrode 28, a resist pattern was formed by preparing for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Further, only the undoped buffer layer and the GaN substrate were braked along this scribe line, thereby completing each compound semiconductor light emitting device. At this time, no damage was introduced into the thin film crystal layer, and no peeling of the dielectric film occurred.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element. At this time, an unintended short circuit or the like of the element did not occur.

4 is a diagram illustrating an example of a light emitting device manufactured in Embodiment 1. FIG. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured in Embodiment 2. FIG. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured in Embodiment 3. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a figure which shows the example of the light emitting element manufactured by other embodiment. It is a flowchart which shows the process order of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. It is process sectional drawing explaining one example of a manufacturing method. FIG. 6 is a process cross-sectional view illustrating an example of the manufacturing method according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating an example of the manufacturing method according to the first embodiment. It is process sectional drawing explaining an example of the manufacturing method of Embodiment 2. FIG. It is process sectional drawing explaining an example of the manufacturing method of Embodiment 2. FIG. It is process sectional drawing explaining an example of the manufacturing method of Embodiment 3. FIG. It is process sectional drawing explaining an example of the manufacturing method of Embodiment 3. FIG. It is a figure which shows an active layer structure typically. 2 is a view showing a light emitting device manufactured in Example 1. FIG. 6 is a view showing a light emitting device manufactured in Example 2. FIG. 6 is a view showing a light emitting device manufactured in Example 3. FIG. It is a figure which shows the conventional light emitting element. It is a figure which shows the conventional light emitting element. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light emitting element 13 Inter-device isolation groove 14 Scribe area | region 15 Insulating layer non-formation part 21 Substrate 22 Buffer layer 22a 1st buffer layer 22b 2nd buffer layer 23 Light equalization layer 24 1st conductivity type clad layer 24a 1st conductivity Type first cladding layer 24b first conductivity type second cladding layer 24c first conductivity type (n-type) contact layer 25 active layer structure 26 second conductivity type cladding layer 26a second conductivity type first cladding layer 26b second conductivity type Second clad layer 26c Second conductivity type (p-type) contact layer 27 Second conductivity type side electrode 28 First conductivity type side electrode 30 Insulating layer 35 Second current injection region 36 First current injection region 37 Second conductivity type side Electrode exposed portion 40 Submount 40b Support body 41 Metal layer 42 Metal solder 45 Low reflection optical film 47 Separation region (support body)
50a, 50b Light extraction surface 51 First etching mask (SiN _x, etc.)
52 Second etching mask (metal fluoride mask)
55 End step surface

Claims (36)

(A) a step (a) of forming a buffer layer and a light uniformizing layer in this order on a substrate;
(B) At least a first conductive type semiconductor layer including a first conductive type cladding layer, an active layer structure, and a thin film crystal layer having a second conductive type semiconductor layer including a second conductive type cladding layer from the substrate side. A step (b) of sequentially forming a film;
(C) a step (c) of forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
(D) a first etching step (d) in which a part of the portion where the second conductivity type side electrode is not formed is etched to expose a part of the first conductivity type semiconductor layer;
(E) In order to form an inter-device separation groove for separating adjacent light emitting elements, a part of the portion where the second conductivity type side electrode is not formed is separated from the surface, (i) the light uniformizing layer Etching is performed at a depth until at least a portion is removed, (ii) at least a portion of the buffer layer is removed, or (iii) at least reaches the substrate. Two etching steps (e);
(F) a step (f) of forming an insulating layer on the entire surface including the second conductivity type side electrode, the first conductivity type semiconductor layer exposed by the first etching step, and the inside of the inter-device isolation trench;
(G) removing an insulating layer in a region including at least the groove center of the groove bottom surface in the inter-device separation groove;
(H) removing a part of the insulating layer formed on the surface of the first conductivity type semiconductor layer and forming an opening to be a first current injection region;
(I) removing a part of the insulating layer formed on the surface of the second conductivity type side electrode and exposing a part of the second conductivity type side electrode;
(J) A method of manufacturing a light emitting device, comprising: a step (j) of forming a first conductivity type side electrode in contact with the first current injection region opened in the step (h).   In the step (g), only the insulating layer in the region including the groove center on the groove bottom surface is removed while leaving the insulating layer formed on the sidewall of the inter-device separation groove. The method according to 1.   In the step (g), all of the insulating layer formed on the bottom surface of the groove in the inter-device separation groove, and the insulating layer formed on at least a portion of the side wall in the inter-device separation groove on the groove bottom surface side. The method according to claim 1, wherein the method is removed.   4. The method according to claim 1, wherein the layer constituting the surface exposed by removing the insulating layer is an undoped type. After step (j)
Isolating the substrate in the inter-device separation groove;
The method according to claim 1, further comprising the step of joining the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount. After step (j)
Bonding the first conductivity type side electrode and the second conductivity type side electrode to the metal layer on the support and mounting the support on the support; and
Removing the substrate;
The method according to claim 1, further comprising a step of dividing the support to separate elements.   The method according to claim 1, wherein the buffer layer and the light uniformizing layer are performed as a part of the thin film crystal layer prior to the formation of the first conductive semiconductor layer. . When the average refractive index of the substrate at the emission wavelength is expressed as n _sb , the average refractive index of the light uniformizing layer is expressed as n _oc , and the average refractive index of the first conductive semiconductor layer is expressed as n ₁ ,
n _sb <n _oc and n ₁ <n _oc
The method according to claim 1, wherein the relationship is satisfied. The light emitting wavelength of the light emitting element is λ (nm), the average refractive index of the substrate at the light emitting wavelength is n _sb , the average refractive index of the light uniformizing layer is no _oc , and the physical thickness of the light uniformizing layer is _toc (Nm), and the relative refractive index difference Δ _(oc−sb) between the light homogenization layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × ( _noc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
The method according to claim 1, wherein t _oc is selected to satisfy The emission wavelength of the light emitting element is λ (nm), the average refractive index at the emission wavelength of the light homogenizing layer is n _oc , the average refractive index at the emission wavelength of the first conductivity type semiconductor layer is n ₁ , and the light homogenizing layer. the physical thickness and _t oc (nm), the relative refractive index difference of the light uniformizing layer and the first conductivity type semiconductor layer delta a _{(oc-1) Δ (oc} -1) ≡ ((n oc) 2 - ( n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
The method according to claim 1, wherein t _oc is selected so as to satisfy. The specific resistance ρ _oc (Ω · cm) of the entire light homogenizing layer is
0.5 ≦ ρ _oc
The light-emitting element according to claim 1, wherein the relationship is satisfied.   The method according to claim 1, wherein the light homogenizing layer is laminated as a plurality of layers. In the step (j), the first conductivity type side electrode is _adjusted such that the width _{L1w of the} narrowest portion of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. The method according to claim 1, wherein the method is formed. In the step (i), among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer, the width L _{2w of the} narrowest portion is not less than 15 μm. The method according to claim 1, wherein a part of the electrode is exposed. The method according to claim 14, wherein the L _2w is 30 μm or more.   The first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and a combination of two or more thereof. The method according to any one.   The second conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ni, Pt, Pd, Mo, Au, and combinations of two or more thereof. The method according to any one of 16. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The method according to claim 1, wherein the method is a single layer.   The method according to claim 1, wherein the insulating layer is a dielectric multilayer film including a plurality of layers.   The method according to claim 19, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride. It said _{fluoride, AlF x, BaF x, CaF} x, The method of claim 20 wherein the selected from the group consisting of SrF _x and MgF _x. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the light homogenizing layer from the first conductivity type semiconductor layer side is reflected by the light homogenizing layer is represented by R2, and the second insulating layer is formed on the insulating layer. The reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident from the conductive semiconductor layer side is reflected by the insulating layer is R12, and the light emission of the light emitting element perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. The reflectance at which light having a wavelength is reflected by the insulating layer is R11, and the reflectance at which light having the emission wavelength of the light emitting element that is perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is R1q. When represented,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The method according to claim 1, wherein the insulating layer is configured so as to satisfy all of the following conditions. The thin film crystal layer is formed by forming a film on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ and MgO. The method according to any one.   The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and The method according to any one of claims 1 to 23, wherein an element selected from the group consisting of Al is included. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The method according to claim 1, wherein:   26. The method according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   6. The method according to claim 5, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by soldering.   The method according to claim 6, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having the metal layer by soldering.   The bonding between the first conductivity type side electrode and the second conductivity type side electrode and the metal layer of the submount or the support is performed only by metal solder, or by metal solder and metal bumps. The method according to 27 or 28. The sub-mount or support base material of a _{metal, AlN, Al 2 O 3,} Si, glass, SiC, diamond, claim 27 to 29, characterized in that it is selected from the group consisting of BN and CuW The method described in 1.   31. The method according to claim 27, wherein a metal layer is not formed at a separation portion between the light emitting elements of the submount or the support.   6. The method according to claim 5, wherein the surface of the substrate on the light extraction side is not flat.   The method according to claim 6, wherein a surface of the buffer layer on a light extraction side is not flat. R3 is the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is reflected by the substrate, and the light of the emission wavelength of the light emitting element that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
6. The method according to claim 5, wherein a low-reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above condition. R3 is a reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light uniformizing layer is reflected by the buffer layer, and the light emitting element that is perpendicularly incident on the light extraction side space from the buffer layer. When the reflectance at which the light of the emission wavelength is reflected at the interface with the space is represented by R4,
R4 <R3
The method according to claim 6, wherein a low-reflection optical film is provided on the light extraction side of the buffer layer so as to satisfy the above condition.   The method according to claim 1, wherein the substrate is GaN, and all of the buffer layer is formed of GaN at a temperature of 900 ° C. or more.

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