JP2007324578A - Integrated semiconductor light-emitting device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated compound semiconductor light-emitting device excellent in in-plane uniformity of light emission intensity and capable of large-area light emission like a surface light source. <P>SOLUTION: The integrated compound semiconductor light-emitting device has a plurality of light-emitting units 11 formed on a transparent substrate 21. Each of the light-emitting units has thin-film crystal layers 24, 25, 26, and first and second conductivity-type side electrodes 27, 28. A light extracting direction is the substrate side. The first and second conductivity-type-side electrodes are formed on the opposite side to the light extracting direction. The light-emitting units are electrically separated from each other by inter-light-emitting unit separating trenches 12. The light-emitting units each have a plurality of light-emitting points including a separated active layer structure 25. The light-emitting device also has an optically coupling layer 23 provided between the substrate and a first conductivity-type clad layer commonly to the plurality of light-emitting units, optically coupling the light-emitting units, and distributing a light to the entire integrated compound semiconductor light-emitting device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated compound semiconductor light emitting device, and more particularly to a light emitting diode (LED) using a GaN-based material. Note that in this specification, the expression “light-emitting diode or LED” is used as a term including a general light-emitting element including a laser diode, a superluminescent diode, and the like.

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue or ultraviolet LEDs with the illumination application in mind.

  In order to increase the output of the element, that is, to improve the total radiant flux, it is essential to increase the size of the element and to ensure resistance to a large input power. In addition, an element that is sufficiently large compared to a normal LED as a point light source exhibits light emission characteristics as a surface light source, and is particularly suitable for illumination applications.

  However, an element in which the area of a normal small LED is simply increased in a similar manner generally has a problem that the uniformity of the light emission intensity of the entire element cannot be obtained. Therefore, it is conceivable to arrange a plurality of elements on the substrate. For example, a technique for forming a plurality of LEDs on the same substrate is disclosed in JP-A-11-150303 (Patent Document 1), JP-A-2001-156331 (Patent Document 2), and JP-A-2002-26384 (Patent Document 1). Document 3) and Japanese Patent Application Laid-Open No. 2003-115611 (Patent Document 4).

  Japanese Patent Application Laid-Open No. 11-150303 (Patent Document 1) discloses an integrated light-emitting component in which a plurality of LEDs are connected in series on a substrate. In this document, in order to electrically and completely separate a part having a pair of pn junctions which are a single light emitting unit, a Ni mask is used to etch a GaN layer until the insulating substrate is exposed. (See paragraph 0027). Therefore, each light emitting unit is merely an individual LED formed on the same substrate. As shown in FIG. 6 of Patent Document 1, since there is no light emission in the separation groove portion separating the light emitting units, the light emitting elements are simply arranged, and the light emission intensity is highly uniform. It is not a surface light source. Moreover, in such a form, when one of the light emitting units in the integrated element is deteriorated, there is a problem that the light emission intensity is extremely lowered only at that portion. Also in the manufacturing method, in particular, the method of dry etching a GaN-based material using a metal mask such as Ni is not necessarily high in resistance of the metal mask. However, there was a problem in the shape control of etching.

  Japanese Patent Application Laid-Open No. 2001-156331 (Patent Document 2) also describes an integrated device in which a plurality of light emitting units are formed on the same substrate. However, also in this document, as shown in FIG. 2, the light emitting units including a pair of pn junction portions are completely separated from each other by separation grooves, and are individual LEDs on the same substrate. Only. Therefore, the separation groove portion separating the light emitting units (the manufacturing method is not disclosed) does not emit light, and thus the uniformity of the light emission intensity in the entire surface light source cannot be ensured. Moreover, in such a form, even when one light emitting unit in the integrated element is deteriorated, there is a problem that the light emission intensity is extremely lowered only at that portion.

Japanese Laid-Open Patent Publication No. 2002-26384 (Patent Document 3) discloses an LED integration method for the purpose of providing an integrated nitride semiconductor light emitting device having a large area and good light emission efficiency. However, as described in FIG. 2, FIG. 3 and paragraph 0038, the separation groove between the light emitting unit and the other light emitting unit portion is formed by the RIE method until reaching the sapphire substrate using SiO ₂ as a mask. It is formed by etching. Since the light is not emitted from the separation groove portion separating the light emitting units, the uniformity of the light emission intensity in the entire surface light source cannot be ensured as in Patent Documents 1 and 2. In addition, when one of the light emitting units in the integrated element is deteriorated, there is a problem that the light emission intensity is extremely lowered only at that portion. In the separation groove forming process, SiO ₂ is used as an etching mask (the resistance of the oxide mask and the nitride mask is not necessarily high). In addition, there was a problem in etching shape control.

Japanese Patent Laid-Open No. 2003-115611 (Patent Document 4) discloses a light emitting device in which LEDs are integrated for the purpose of use as a surface emitting light source or a display. This document describes two types of devices, one of which is a device in which light emitting units including a pair of pn junctions are electrically isolated from one another (claim 4). FIG. 10 (b) and the like. This separation is formed by dicing (FIG. 10). In this type, as in the above three documents, the emission intensity is greatly reduced at the separation groove portion between the light emitting units, so that uniformity over the entire surface light source cannot be ensured. In addition, when one of the light emitting units is deteriorated, there is a problem that the light emission intensity is extremely lowered only in the vicinity thereof. The second type of device described in this document is a device in which light-emitting units including a pair of pn junction portions are electrically coupled to each other (Claim 5, FIG. 10 (a), etc.) ). In this type, the n-type semiconductor layer is common to the entire light emitting device (FIG. 10A). In such a case, not only the current flows from the n-side electrode to the nearest p-side electrode, but also the current flows from one n-side electrode to every p-side electrode. Current injection efficiency is not high. In addition, since all the p-side electrodes and all the n-side electrodes are electrically coupled, the deterioration at one place becomes the deterioration of the entire apparatus. Therefore, this type of device is essentially unsuitable for increasing the area for a surface light source.
Japanese Patent Laid-Open No. 11-150303 JP 2001-156331 A JP 2002-26384 A JP 2003-115611 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated compound semiconductor light emitting device capable of emitting light of a large area as a surface light source and having excellent in-plane uniformity of light emission intensity. It is another object of the present invention to provide a device capable of ensuring high in-plane uniformity and maintaining high in-plane uniformity even if the light emission unit shows a slight variation in emission intensity. And

  The present invention relates to the following matters.

1. An integrated compound semiconductor light emitting device having a substrate transparent to an emission wavelength and a plurality of light emitting units formed on the substrate,
The light emitting unit includes a compound semiconductor thin film crystal having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on the substrate. A layer, a second conductivity type side electrode, and a first conductivity type side electrode,
The main light extraction direction is the substrate side, and the first conductivity type side electrode and the second conductivity type side electrode are formed on the opposite side to the main light extraction direction,
The light emitting units are electrically separated by a light emitting unit separating groove provided between adjacent light emitting units,
In one light emitting unit, there are a plurality of light emitting points including the active layer structure, the second conductive type semiconductor layer, and the second conductive type side electrode, and at least one first conductive type side electrode. Provided, and the inside of one light emitting unit is electrically connected by the first conductive semiconductor layer,
Furthermore, the light emitted from one light emitting unit is provided between the substrate and the first conductive semiconductor layer in common between the plurality of light emitting units, and optically couples the plurality of light emitting units. An integrated compound semiconductor light emitting device comprising an optical coupling layer that distributes the light to other light emitting units.

  2. The optical coupling layer is a layer provided in common between the plurality of light emitting units between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. 2. The light-emitting device according to 1 above.

3. When the average refractive index of the substrate at the emission wavelength is represented by n _sb , the average refractive index of the optical coupling layer is represented by no _oc , and the average refractive index of the first conductive semiconductor layer is represented by n ₁ ,
n _sb <n _oc and n ₁ <n _oc
3. The light-emitting device according to 1 or 2 above, wherein the relationship is satisfied.

4). The emission wavelength of the light emitting device is λ (nm), the average refractive index of the substrate at the emission wavelength is n _sb , the average refractive index of the optical coupling layer is n _oc , and the physical thickness of the optical coupling layer is t _oc (nm ) And the relative refractive index difference Δ _(oc−sb) between the optical coupling layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_4. The light-emitting device according to any one of 1 to 3, wherein t _oc is selected so as to satisfy

5). The emission wavelength of the light emitting device is λ (nm), the average refractive index of the optical coupling layer at the emission wavelength is n _oc , the average refractive index of the first conductivity type semiconductor layer is n ₁ , and the physical thickness of the optical coupling layer is t _oc (nm), and the relative refractive index difference Δ _(oc-1) between the optical coupling layer and the first conductivity type semiconductor layer is Δ _(oc-1) ≡ ((n _oc ) ^2- (n ₁ ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_5. The light-emitting device according to any one of 1 to 4 above, wherein t _oc is selected so as to satisfy

6). The specific resistance ρ _oc (Ω · cm) of the entire optical coupling layer is
0.5 ≦ ρ _oc
The light-emitting device according to any one of 1 to 5 above, wherein:

  7). 7. The light emitting device according to any one of 1 to 6 above, wherein the optical coupling layer has a stacked structure of a plurality of layers.

  8). In the plurality of light emitting units, the separation grooves between the light emitting units are removed between adjacent light emitting units from the surface of the thin film crystal layer to the interface of the optical coupling layer or a part of the optical coupling layer. 8. The light emitting device according to any one of 1 to 7 above, wherein the light emitting device is formed.

  9. 9. The light emitting device according to any one of 1 to 8, wherein a width of the light emitting unit separation groove is in a range of 2 to 300 μm.

  10. 10. The light emitting device according to any one of 1 to 9, further comprising a buffer layer in contact with the substrate.

  11. The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway in the optical coupling layer. 11. The light-emitting device according to any one of 1 to 10 above.

  12 The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway in the buffer layer. 11. The light emitting device as described in 10 above.

  13. The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed to reach the substrate. The light-emitting device according to any one of 1 to 10 above.

  14 The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed by removing a part of the substrate. 11. The light-emitting device according to any one of 1 to 10 above.

  15. Of the layers covering the entire bottom surface and side surfaces in the light emitting unit separation groove and exposed on the side surfaces of the light emitting device, at least the side surfaces of the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer. And an insulating layer that is in contact with a part of the first conductivity type side electrode on the main light extraction direction side and covers a part of the second conductivity type side electrode opposite to the main light extraction direction. 15. The light-emitting device according to any one of 1 to 14 above.

  16. 16. The light emitting device according to claim 15, wherein the insulating layer covers all of the layer exposed on the side surface of the inter-device separation groove.

  17. 17. The light-emitting device according to 16 above, wherein a region not covered with the insulating layer is provided on the bottom surface of the groove between the devices as the scribe region.

  18. The insulating layer is not formed on the groove bottom surface in the inter-device separation groove, and of the layers exposed on the side surface of the inter-device separation groove, the layer does not have conductivity from the groove bottom surface side. 16. The light emitting device as described in 15 above, wherein the light emitting device is not formed at least partially.

  19. The light-emitting device according to any one of 1 to 18 above, wherein the thin-film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V.

20. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
20. The light-emitting device according to any one of 1 to 19 above, wherein

21. Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, light emitting device according to any one of the above 1 to 20, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.

  22. 19. The light emitting device according to any one of 15 to 18 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

23. The reflectance at which the light having the emission wavelength of the light emitting device perpendicularly incident on the optical coupling layer from the first conductive semiconductor layer side is reflected by the optical coupling layer is represented by R2, and the second conductive type is applied to the insulating layer. The reflectance at which the light having the emission wavelength of the light-emitting device perpendicularly incident from the semiconductor layer side is reflected by the insulating layer is R12, and the light emission wavelength of the light-emitting device perpendicularly incident on the insulating layer from the first conductivity type semiconductor layer side is R12. R11 represents a reflectance at which light is reflected by the insulating layer, and R1q represents a reflectance at which light having a light emission wavelength of the light emitting device that is perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer. When
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
23. The light-emitting device according to any one of 15 to 18 and 22, wherein the insulating layer is configured to satisfy all of the above conditions.

  24. 24. The light emitting device according to any one of 1 to 23, wherein a surface of the substrate on the light extraction side is not flat.

25. R3 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident on the substrate side from the optical coupling layer is reflected by the substrate, and the light having the light emission wavelength of the light emitting device that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
25. The light emitting device according to any one of 1 to 24 above, wherein a low reflection optical film is provided on the light extraction side of the substrate so as to satisfy the above.

  26. 26. The light-emitting device according to any one of 1 to 25 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  27. 27. The light emitting device according to any one of items 1 to 26, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal surface by solder.

28. A method of manufacturing an integrated compound semiconductor light emitting device having a plurality of light emitting units on the same substrate,
Forming an optical coupling layer on a substrate transparent to the emission wavelength;
Forming a thin film crystal layer having at least a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer;
Forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
In order to expose a part of the first conductivity type semiconductor layer on the surface and to form a plurality of light emitting points including the active layer structure, the second conductivity type semiconductor layer, and the second conductivity type side electrode, A first etching step of dividing the second conductive semiconductor layer and the active layer structure into a plurality of regions;
Forming at least one first conductivity type side electrode on the surface of the first conductivity type semiconductor layer exposed by the first etching step;
In order to form a separation groove between the light emitting units for electrically separating the light emitting units from each other, from the surface of the thin film crystal layer to the interface of the optical coupling layer, or from the surface of the thin film crystal layer to the optical coupling layer. A second etching step to remove a part,
A third etching step of removing at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer to form an inter-device separation groove for separating into a plurality of light emitting devices. A method of manufacturing an integrated compound semiconductor light emitting device.

  29. 29. The method according to claim 28, wherein the step of forming the optical coupling layer is performed as a part of the step of forming the thin film crystal layer and prior to the formation of the first conductive semiconductor layer.

30. When the average refractive index of the substrate is represented by n _sb and the average refractive index of the optical coupling layer is represented by _noc ,
n _sb <n _oc
30. The method according to the above 28 or 29, wherein the relationship is satisfied.

31. The emission wavelength of the light emitting device is λ (nm), the average refractive index of the substrate at the emission wavelength is n _sb , the average refractive index of the optical coupling layer is n _oc , and the physical thickness of the optical coupling layer is t _oc (nm ) And the relative refractive index difference Δ _(oc−sb) between the optical coupling layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
31. The method according to any one of 28 to 30 above, wherein t _oc is selected so as to satisfy

32. The light emission wavelength of the light emitting device is λ (nm), the average refractive index at the light emission wavelength of the optical coupling layer is n _oc , the average refractive index at the light emission wavelength of the first conductive semiconductor layer is n ₁ , and the physical properties of the optical coupling layer The specific thickness is t _oc (nm), and the relative refractive index difference Δ _(oc-1) between the optical coupling layer and the first conductivity type semiconductor layer is Δ _(oc-1) ≡ ((n _oc ) ² − (n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
32. The method according to any one of 28 to 31 above, wherein t _oc is selected so as to satisfy

33. The specific resistance ρ _oc (Ω · cm) of the entire optical coupling layer is
0.5 ≦ ρ _oc
33. The method according to any one of 28 to 32, wherein the relationship is satisfied.

  34. 34. The method according to any one of 28 to 33, wherein the optical coupling layer is formed as a stacked structure of a plurality of layers.

  35. 35. The method according to any one of 28 to 34, further comprising a step of forming a buffer layer on the substrate before the step of forming the optical coupling layer.

  36. The third etching step is performed simultaneously with or separately from the second etching step, and etching is performed from the surface of the thin film crystal layer to the interface of the optical coupling layer or until a part of the optical coupling layer is removed from the surface of the thin film crystal layer. 36. The method according to any one of 28 to 35, wherein:

  37. 36. The method according to 35, wherein the third etching step is performed until a part of the buffer layer is removed from the surface of the thin film crystal layer.

  38. 36. The method according to any one of 28 to 35, wherein in the third etching step, etching is performed until the surface of the substrate is reached.

  39. 36. The method according to any one of 28 to 35, wherein in the third etching step, etching is performed so as to remove part of the substrate.

40. The second and third etching steps are performed by a dry etching method using a gas species selected from the group consisting of Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations of two or more thereof. 40. The method according to any one of 28 to 39 above.

  41. 41. The method according to claim 40, wherein a patterned metal fluoride layer is used as an etching mask.

42. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and method of the above 41, wherein the selected from the group consisting of.

  43. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order, and before the step of forming the first conductivity type side electrode, 43. The method according to any one of 28 to 42, further comprising a step of forming an insulating layer.

  44. 44. The method according to claim 43, wherein the step of forming the insulating layer is performed after the first to third etching steps.

45. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, at least a part of the buffer layer is removed from the surface until at least a part of the optical coupling layer is removed (provided that the buffer layer is present), or at least. Etching is performed at a depth up to the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
36. The method according to any one of 28 to 35, further comprising a step of forming a scribe region by removing a part of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove.

46. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, at least a part of the buffer layer is removed from the surface until at least a part of the optical coupling layer is removed (provided that the buffer layer is present), or at least. Etching is performed at a depth up to the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
A step of removing all of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove and a part of the insulating layer formed on the side wall of the inter-device separation groove on the groove bottom surface side. 36. The method according to any one of 28 to 35 above, wherein

  47. The second and third etching steps are performed at the same time, and etching is performed until the interface of the optical coupling layer or until a part of the optical coupling layer is removed to form the inter-device separation groove. 46. The method according to 45 above.

  48. The second and third etching steps are performed at the same time, and etching is performed until the interface of the optical coupling layer or until a part of the optical coupling layer is removed to form the inter-device separation groove. 47. The method according to 46 above.

  49. 28-48, further comprising a step of separating the light-emitting devices into a plurality of light-emitting devices, and a step of bonding the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount. The method described.

  50. 50. The method according to 49 above, wherein the joining is performed with solder.

  According to the present invention, it is possible to provide an integrated compound semiconductor light emitting device capable of emitting light of a large area as a surface light source and having excellent in-plane uniformity of light emission intensity. In addition, even if the light emission intensity of each light emitting unit shows some degree of deterioration, it is possible to provide a device that can ensure high in-plane uniformity and continue to ensure high in-plane uniformity. .

In particular, according to the present invention, even when the area of the light-emitting device exceeds several cm ² , it is possible to realize planar blue or ultraviolet light emission with relatively high emission intensity uniformity. The present invention also relates to a flip-chip type light emitting device in which light is extracted from the substrate side, and both the p-side and n-side electrodes are disposed on the opposite side of the light extraction side. Without using the p-side and n-side electrodes, which can be mounted on a heat-dissipating submount with metal wiring by soldering etc., sufficient heat dissipation and high light extraction efficiency are ensured be able to.

  In the present invention, since the light emitting units are electrically separated from each other, but are optically coupled by the optical coupling layer, the light emitted from the quantum well layer of a certain light emitting unit is converted into another light emitting unit. Also distributed in the part. For this reason, since light is emitted from the light emitting device of the present invention even between the light emitting units whose luminance is lowered in the conventional configuration, surface light emission with relatively high uniformity can be obtained. Even if there is a variation in the light emission intensity between the light emitting units, or even when the deterioration shows a slight variation, the uniformity of the in-plane light emission intensity is high due to the presence of the optical coupling layer. Furthermore, even if a defect occurs in one light emitting unit and it cannot be lit, a certain level of light emission intensity is secured immediately above the defective light emitting unit, so that the surface uniformity is good.

  In addition, the light-emitting device of the present invention is characterized by having an appropriate number of light-emitting points in an electrically separated light-emitting unit, rather than integrating only light-emitting points that are electrically coupled. That is, when the entire light emitting device is formed only by the light emitting points that are electrically coupled, the deterioration of one light emitting point changes the current injection path of the entire device, and the light emission intensity of the entire light emitting device is reduced. This will affect the uniformity. However, when an appropriate number of a plurality of light emitting points are included in one light emitting unit, the electrical influence of the deterioration is limited to the light emitting unit. Furthermore, since the light emitting units are optically coupled as described above, the deterioration of one light emitting point, that is, the deterioration of a light emitting unit including the light emitting point is optically affected by the surrounding light emitting units that are not electrically affected. This is desirable because it is easily compensated.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”.

Further, in the present invention, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), plasma assist MBE, PLD (Pulsed).
Laser Deposition), PED (Pulsed Electron Deposition), VPE (Vapor Phase Epitaxy), LPE (Liquid
In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth equipment such as the (Phase Epitaxy) method, carrier treatment by subsequent heat treatment, plasma treatment, etc. It is described as thin film crystal growth including activation treatment.

  FIG. 1 shows an example of an integrated compound semiconductor light emitting device (hereinafter simply referred to as a light emitting device) of the present invention. In order to explain the structure of the light emitting device of FIG. 1 in detail, the structure will be described with reference to FIG. Here, as shown in FIGS. 1 and 2, an example in which three light emitting points 17 exist in one light emitting unit 11 and one light emitting device 10 is configured by four light emitting units 11 is shown. However, the number of light emitting points existing in one light emitting unit 11 and the number of integrated light emitting units are not particularly limited, and the number can be appropriately set within one provided substrate. The number of light emitting units stacked may be two, for example, or a number exceeding 500 may be stacked. Here, the number is preferably 25 to 200, and it is also preferable that they are two-dimensionally arranged. Also, the number of light emitting points present in one light emitting unit is not particularly limited. For example, two light emitting points may be used, or more than 500 may be integrated. Here, the number is preferably 5 to 100, more preferably 10 to 50, and it is also preferable that they are two-dimensionally arranged.

  In the present invention, as shown in the drawing, one light emitting unit includes at least a first conductive type semiconductor layer including a first conductive type cladding layer 24 and a second conductive type including a second conductive type cladding layer 26 on a substrate 21. And a compound semiconductor thin film crystal layer having an active layer structure 25 sandwiched between the first and second conductivity type semiconductor layers, a second conductivity type side electrode 27, and a first conductivity type side electrode 28. Have. As shown in the figure, the light emitting unit separation groove 12 defines the light emitting unit 11 in the integrated compound semiconductor light emitting device 10, but the substrate 21 and the optical coupling layer 23 are provided in common between the light emitting units. Yes. Further, the buffer layer 22 formed first on the substrate is also common between the light emitting units.

  In this example, the second conductivity type side electrode 27 is disposed on a part of the surface of the second conductivity type cladding layer 26, and the portion where the second conductivity type cladding layer 26 and the second conductivity type side electrode 27 are in contact with each other. Is the second current injection region 35. Further, the second conductivity type cladding layer, a part of the active layer structure, and a part of the first conductivity type cladding layer are removed, and the first conductivity type cladding layer 24 exposed at the removed portion is in contact. By arranging the first conductivity type side electrode 28, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the substrate. In this case, in the present invention, the active layer structure 25 and the second conductive type semiconductor layer (including the second conductive type clad layer 26) are divided in one light emitting unit and can emit light independently of each other. 17 and the first conductivity type semiconductor layer is present in common in the light emitting unit. One second conductivity type side electrode 27 is provided at each light emitting point 17. In addition, at least one first conductivity type side electrode 28 may be provided in one light emitting unit, but may be provided corresponding to the number of light emitting points. Further, the number of first conductivity type side electrodes 28 may be larger than the number of light emitting points in one light emitting unit. However, in the present invention, in particular, when the second conductivity type side electrode that is preferably implemented is a p-type electrode, the number or area of the second conductivity type side electrode is equal to the number of the first conductivity type side electrodes or More or more than the area is desirable. This is because, in one light emitting unit, a portion contributing to substantial light emission is a quantum well layer in an active layer structure that exists under (or depending on how to see) the second conductivity type side electrode. Therefore, it is preferable that the number or area of the second conductivity type side electrodes in one light emitting unit is relatively larger or wider than the number or area of the first conductivity type side electrodes. Further, in relation to a current injection region described later, it is desirable that the number or area of the second current injection regions is larger or wider than the number or area of the first current injection regions. It is most desirable that both the electrode relationship and the current injection region relationship satisfy the above.

  In the present invention, the light emitting point 17 is electrically connected to the first conductive semiconductor layer in the light emitting unit 11, and the light emitting units 11 are electrically separated from each other by the light emitting unit separating groove 12. . That is, the light emitting unit separation groove 12 divides a highly conductive layer in the thin film crystal layer, and there is no substantial electrical coupling between the light emitting units.

  On the other hand, in the present invention, the optical coupling layer 23 exists in common between the light emitting units, and the light emitting units are optically coupled. That is, light emitted from one light emitting unit reaches other unit parts by appropriate propagation and radiation (leakage) in the optical coupling layer, and is not localized only in one light emitting unit part. The other light emitting unit parts are also reached. For this purpose, it is necessary that the light emitting unit separation groove 12 reaches the interface of the optical coupling layer or reaches the optical coupling layer without being divided as shown in FIG. As will be described in detail later, the optical coupling layer is substantially insulative, and is made of a material having a relatively high refractive index in order to realize an appropriate waveguide function within the layer.

  In the present invention, the width of the light emitting unit separation groove is preferably 2 to 300 μm, more preferably 5 to 50 μm, and most preferably 8 to 15 μm. When the width of the separation groove between the light emitting units is short, the uniformity of the surface light emission is improved together with the optical coupling layer.

  FIG. 2 also shows a part of another light emitting device adjacent to the central light emitting device 10 on the same substrate. Each light emitting device 10 is separated by an inter-device separation groove 13. The scribing region 14 in the inter-device separation groove 13 is scribed and braked to separate each light emitting device, and the second conductivity type side electrode is connected to the metal surface 41 on the submount 40 via the metal solder 42. 27 and the first conductivity type side electrode 28 are connected to each other to obtain a light emitting device as shown in FIG.

  In this example, the inter-device separation groove is formed by removing the thin film crystal layer until it reaches the substrate, which is one of the preferred forms. On the other hand, a mode in which the inter-device separation groove is formed up to the middle of the combined optical coupling layer and buffer layer is also preferable, and a mode in which a part of the substrate is removed is also possible. In any of these cases, the insulating layer can be easily formed on the side wall of the highly conductive layer on the active layer structure side of the optical coupling layer. In either case, the light is divided into light emitting devices one by one by being divided at the scribe region in the device separation groove.

  In the light emitting device of the present invention, the insulating layer 30 covers most of the exposed portions including the surfaces and side walls of the thin film crystal layers 22 to 26. However, the side wall portion of the light emitting device of FIG. The shape of the insulating layer in the inter-device separation groove 13 in the state of FIG. 2 that is not separated can take several forms. In any form, it is preferable that before the light emitting device is separated, a portion where no insulating layer exists is present in the inter-device separation groove 13 that partitions the light emitting device. And it is preferable to isolate | separate between light emitting devices from the part in which an insulating film does not exist. As a result, in the preferable shape of the light emitting device of the present invention, the insulating layer covering the side wall does not reach the end of the light emitting device. Specific examples of preferred forms of the insulating layer are shown below.

  In one embodiment of the present invention, as shown in FIG. 2, the insulating layer 30 does not cover the entire surface of the inter-device separation groove 13 but is in contact with the substrate surface (ie, the groove bottom surface). The scribe region 14 where the insulating layer 30 is not formed is formed. For this reason, it is preferable since the thin film crystal layer is not damaged during the separation between devices and the insulating layer is not peeled off. In the light emitting device obtained as a result, the insulating layer 30 does not reach the end of the substrate as shown in part A of FIG. As a result of ensuring that the insulating layer does not peel off in the device having this shape, the function of the light emitting device is not impaired even if the side wall solder of the light emitting unit wraps around, and the device is highly reliable It becomes.

  Further, in a different embodiment of the present invention, as shown in FIG. 4, there is an insulating layer non-formed portion 15 in which the insulating layer 30 is not formed by the substrate surface (that is, the groove bottom surface) and the groove sidewall portion adjacent to the substrate. To do. This structure is also preferable because peeling of the insulating layer does not occur during device separation. In the obtained light emitting device, there is an insulating layer non-forming portion 15 where the insulating layer 30 does not reach the substrate surface, as shown in part B of FIG. In this figure, the entire wall surface of the buffer layer 22 and a part of the wall surface of the optical coupling layer 23 are exposed, but the side wall of the optical coupling layer is covered and a part of the side wall of the buffer layer is exposed. Also good. The exposed part is preferably an undoped undoped layer. Preferably, the optical coupling layer is also covered with an insulating layer. In the device having this shape, it is guaranteed that there is no peeling of the insulating layer, and if the exposed material is a highly insulating material, the device is as reliable as the light emitting device in the form of FIG. It becomes. In addition, when the inter-device separation groove is formed by etching up to a part of the substrate, only the substrate portion of the wall surface of the groove is exposed and the buffer layer may be covered with an insulating layer.

  When the inter-device separation groove is formed up to the middle of the combined optical coupling layer and buffer layer, a light emitting device having the following shape is obtained. First, when the inter-device separation groove is formed up to the middle of the optical coupling layer 23, for example, as shown in FIGS. 17 and 18, the optical coupling layer 23 and the buffer layer 22 exist up to the end of the light emitting device, and the buffer All the wall surfaces of the layer are exposed, and the optical coupling layer has a level difference based on the bottom surface of the inter-device separation groove. The side wall of the optical coupling layer is covered with the insulating layer so as to coincide with the side wall of the buffer layer. And a side wall portion (side wall of the inter-device separation groove) that enters from the end of the light emitting device. Here, the ends of the optical coupling layer 23 and the buffer layer 22 coincide with the end face of the substrate in FIGS. May come out. In the example of FIG. 17, the insulating layer 30 includes a separation groove bottom surface portion and a side wall portion of the separation groove from the position of the groove bottom surface away from the end of the optical coupling layer 23, as indicated by C portion in FIG. 17. It is covered. This corresponds to a form in which the inter-device separation groove is stopped in the middle of the optical coupling layer 23 in FIGS. 1 and 2. 18 corresponds to a form in which the inter-device separation groove is stopped in the middle of the optical coupling layer 23 in FIGS. 3 and 4, and as shown in a D part of FIG. Of the entered side wall portion (side wall of the inter-device separation groove), there is a portion that is not covered with the insulating layer on the main light extraction direction side.

  Next, when the inter-device separation groove is formed partway through the buffer layer 22, for example, as shown in FIGS. 19 and 20, the buffer layer 22 exists up to the end of the light emitting device. There is a step based on the bottom surface of the inter-separation groove, and the side walls of the buffer layer are not covered by the insulating layer (device end portion) and the side wall portion entering from the end of the light emitting device (inter-device separation groove) Side wall). Also in this case, the end of the buffer layer 22 coincides with the end face of the substrate in FIGS. 19 and 20. However, depending on the separation method, the end of the buffer layer 22 may enter inside the substrate 21 or exit outside the substrate 21. . In the example of FIG. 19, the insulating layer 30 covers the separation groove bottom surface portion and the side wall portion of the separation groove from the position of the groove bottom surface away from the end of the buffer layer 22 as indicated by E portion in FIG. 19. Furthermore, the side wall of the optical coupling layer 23 (side wall of the inter-device separation groove) is covered. This corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIGS. 1 and 2. 20 corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIGS. 3 and 4, and enters the inner side from the end of the light emitting device as shown in F part of FIG. In the side wall portion (side wall of the inter-device separation groove), there is a portion not covered with the insulating layer on the main light extraction direction side.

  As in these examples, when the inter-device separation groove is formed up to the middle of the combined optical coupling layer and buffer layer, the insulating layer covering the side wall does not reach the end of the light-emitting device. The device that is capable of ensuring that the insulating layer does not peel off, and that the exposed layer is made of a highly insulating material, so that it is as reliable as the light emitting device in the form of FIGS. It becomes a high device.

  Furthermore, in the light emitting device of the present invention, the insulating layer 30 is in contact with a part of the first conductivity type side electrode 28 on the main light extraction direction side as shown in FIG. 1, that is, the first conductivity type side electrode 28. There is a portion where an insulating layer is interposed around the contact portion between the first conductive type semiconductor layer and the first conductive type semiconductor layer (first conductive type clad layer 24 in the figure), and the main light extraction direction of the second conductive type side electrode 27 That is, there is no insulating layer between the second conductivity type side electrode 27 and the second conductivity type semiconductor layer (second conductivity type clad layer 26 in the figure). It is preferable that there is a covering portion around the second conductivity type side electrode 27. This form means that the insulating layer 30 is formed after the second conductivity type side electrode 27 is formed, and the first conductivity type side electrode 28 is formed after the insulating layer 30 is formed. Although a manufacturing method based on such an order will be described later, since the second conductive type semiconductor layer such as the second conductive type cladding layer 26 is less damaged and the first conductive type side electrode is less damaged, it is highly efficient. A light emitting device is obtained. That is, the light emitting device having such a structure means high efficiency.

  Further, the size of the second conductivity type side electrode 27 is the same as that of the second current injection region 35, but the exposed surface 37 (second conductivity type side electrode exposed portion) of the second conductivity type side electrode is The size is preferably smaller than the size of the current injection region 35. Furthermore, an opening is provided in part of the insulating layer 30 covering the surface of the first conductivity type cladding layer 24 so that the first conductivity type side electrode 28 contacts the first conductivity type cladding layer 24. One current injection region 36 is formed. The area of the first conductivity type side electrode 28 is preferably larger than that of the first current injection region.

  It is also desirable that the second conductivity type side electrode and the first conductivity type side electrode do not overlap in space.

  Below, each member and structure which comprise an apparatus are demonstrated in detail.

<Board>
The material of the substrate 21 is not particularly limited as long as it is optically approximately transparent with respect to the light emission wavelength of the element. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if there is absorption, the light output is not reduced by 50% or more due to absorption of the substrate.

The substrate is preferably an electrically insulating substrate. This is because when flip chip mounting is performed, even if a solder material or the like adheres to the periphery of the substrate, current injection into the light emitting device is not affected. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less It is desirable from the viewpoint of electrical resistance and crystallinity.

  The substrate used in the present invention is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. it can. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when using a c + plane substrate of sapphire as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture an integrated compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer described later, so that a threading transition that occurs at the interface between the thin film crystal layer and the substrate can be activated in the light emitting element or the light emitting unit described later. It is also possible not to introduce it in the vicinity of the layer.

  In the present invention, since the light is confined in the optical coupling layer, which will be described later, and partially guided, the refractive index at the emission wavelength of the integrated compound semiconductor light emitting device is relative to the average refractive index of the optical coupling layer. It is desirable to be small.

  In one embodiment of the present invention, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication so that the crystal growth of the semiconductor light emitting device and the mechanical strength in the element fabrication process are ensured. It is normal to keep it. In order to make it easy to separate each element after growing a thin film crystal layer using this, it is appropriately thinned in the middle of the process by a polishing process, and finally the light emitting device has a thickness of about 100 μm or less. Is not good. Moreover, it is the thickness of 30 micrometers or more normally.

  Further, in a different form of the present invention, the thickness of the substrate may be different from the conventional one, and may be about 350 μm, further about 400 μm, or about 500 μm.

In addition, in order to confine light in an optical coupling layer, which will be described later, and to guide the light, when the substrate is selected to be a low refractive index layer relative to the waveguide, the physical thickness of the substrate is the light emission of the light emitting device. When the wavelength is λ (nm) and the average refractive index of the substrate is n _sb , it is preferably thicker than 4λ / n _sb .

Furthermore, it is desirable that a so-called low-reflection coating layer or low-reflection optical film is formed on the surface in the main light extraction direction of the substrate. Reflection due to a difference in refractive index at the substrate-air interface can be suppressed, so that high output and high efficiency of the device can be achieved. Here, the reflectance at which the light of the emission wavelength of the light emitting device that is perpendicularly incident on the substrate side from the optical coupling layer is reflected by the substrate is R3, and the light of the light emission wavelength of the light emitting device that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4, it is desirable to have a low reflection optical film on the light extraction side of the substrate so that the reflectance R4 with respect to the light emission wavelength of the element satisfies R4 <R3. . For example, when the substrate is sapphire, it is desirable to use MgF ₂ or the like as the low reflection coating film. Relative refractive index n _s of the substrate at the emission wavelength, the refractive index of the low reflecting coating film, since it is desirable near √n _s, relative to the square root of the refractive index of the sapphire, the refractive index of MgF ₂ are close It is.

In the present invention, it is also preferable that the surface in the main light extraction direction of the substrate is an uneven surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. When the light emission wavelength of the device is λ (nm), the roughness of the rough surface is such that the average roughness Ra (nm) is λ / 5 (nm) <Ra (nm) <10 × λ (nm).
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

<Buffer layer>
When the thin film crystal is grown on the substrate, the buffer layer 22 mainly includes suppression of transition, relaxation of imperfection of the substrate crystal, reduction of various mismatches between the substrate crystal and a desired thin film crystal growth layer, and the like. Formed for the purpose of thin film crystal growth.

  When a thin film crystal is grown on a dissimilar substrate such as InAlGaN-based material, InAlBGaN-based material, InGaN-based material, AlGaN-based material, or GaN-based material, which is a desirable form of the present invention, the lattice constant matching with the substrate is not necessarily ensured. The buffer layer is particularly important because it is not. For example, when a thin-film crystal growth layer after the optical coupling layer, which will be described later, is grown by metal organic vapor phase epitaxy (MOVPE method), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or near 500 ° C. It is also possible to use a low-temperature grown GaN layer formed in (1). Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer 22 is not necessarily a single layer, and a GaN layer grown at a temperature of about 1000 ° C. without doping is further formed on the GaN buffer layer grown at a low temperature in order to improve the crystallinity. You may make it have about several micrometers. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. In the present invention, since the buffer layer exists in common between the light emitting units in the compound semiconductor light emitting device, it is desirable not to have a doped layer. However, when the buffer layer has a layer doped from the viewpoint of crystallinity, an undoped layer is formed after the doping layer is grown, and electrical insulation between the light emitting units is completely ensured. It is essential to be able to do so. It is also possible to stack a doped layer and an undoped layer in the buffer layer.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to the present invention. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  In the present invention, since the buffer layer is a common layer between the light emitting units, it may be integrated with an optical coupling layer described later to realize optical coupling between the light emitting units. At this time, it is necessary not to disturb the electrical insulation between the light emitting units. Further, part or all of the buffer layer may also serve as the optical coupling layer.

  The buffer layer may be an exposed portion of the inter-device separation groove. In particular, it is preferable that the undoped portion is exposed because insulation failure due to solder or the like during device assembly can be suppressed.

<Optical coupling layer>
The optical coupling layer of the present invention is a layer for realizing optical coupling between the light emitting units constituting the light emitting device, and inhibits electrical insulation between the light emitting units inherent in the integrated semiconductor light emitting device. It is not a layer.

  The optical coupling layer 23 is preferably formed of a compound semiconductor layer, and is present between the buffer layer and the first conductivity type semiconductor layer (first conductivity type cladding layer in the figure) as shown in FIGS. It is desirable. In addition, the film forming method is not particularly limited, but it is desirable that the thin film crystal growth technique be used simultaneously with other thin film crystal layers in order to easily manufacture the integrated semiconductor light emitting device.

In the present invention, the refractive index of the optical coupling layer is preferably selected so that at least a certain amount of light is confined in the layer, that is, the light distribution density is increased to some extent. Accordingly, it is desirable that the average refractive index (n _oc ) of the optical coupling layer is larger than the average refractive index (n _sb ) of the substrate and the average refractive index of the first conductivity type cladding layer. In particular, the average refractive index (n ₁ ) of the first conductivity type semiconductor layer existing between the optical coupling layer and the active layer structure is preferably larger. Moreover, it is more than the average refractive index ( _nbf ) of a buffer layer, and it is preferable that it is especially larger than the average refractive index of a buffer layer. Further, it is particularly preferable that the material constituting the optical coupling layer is transparent to light emitted from the quantum well layer. In the case of a light emitting device based on a group III-V nitride such as InAlGaN, it is desirable to contain In or Al to such an extent that light emitted from the active layer structure is not absorbed. It is preferable to contain.

  Moreover, the optical coupling layer does not need to be a single layer, and may be composed of a plurality of layers. When composed of a plurality of layers, for example, a plurality of layers such as AlGaN, InGaN, InAlGaN, and GaN may exist, or a superlattice structure may be used.

Here, the average refractive index (nav) of each layer is the product of the refractive index (nx) of each of the n types of materials constituting the layer and the physical thickness (tx) of the material. Is divided by the total thickness,
nav = (n1 × t1 + n2 × t2 +... + nn × tn) / (t1 + t2 +... + tn)

  In addition, the optical coupling layer may exhibit effects such as light scattering, multiple reflection, and thin film interference depending on the structure, and these effects also improve uniformity on the light extraction surface of the entire light emitting device. Is also possible.

As an example of the optical coupling layer, for example, the active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is n-GaN, and the buffer layer is When undoped GaN and the substrate are sapphire, a single layer of undoped GaN can be used as the optical coupling layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When the laminated structure of undoped GaN and Si-doped GaN and the substrate is sapphire, a single-layer undoped GaN can be used as the optical coupling layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When an undoped GaN and Si-doped GaN layered structure is used, and the substrate is Si-doped GaN, In _b Ga _1-b N having a composition transparent to the emission wavelength is desired in the thick undoped GaN layer as the optical coupling layer. A multilayer structure having a desired number of thicknesses can be used. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

In such a structure, it is desirable that the optical coupling layer further includes materials such as In _b Ga _1-b N and In _c Al _d Ga _1-cd N, and the compositions b, c, d and N-GaN that is transparent at 460 nm and may be included in the first conductivity type semiconductor layer, undoped GaN that may be included in the buffer layer, and sapphire that may be included as the substrate by appropriately selecting the thickness and the like Can be used as an optical coupling layer, and they may be used as a single layer or as a plurality of laminated structures selected from them and an undoped GaN layer.

  It is also preferable that the optical coupling layer has a superlattice / quantum well structure composed of an InGaN layer and a GaN layer in which the In composition and the thickness of the InGaN layer are set so as not to absorb the emission wavelength of the compound semiconductor light emitting device.

  It is also important that the thickness of the optical coupling layer is selected so as to function as a multimode optical waveguide that receives a part of the light emitted from each light emitting unit and propagates the light between the light emitting units.

The physical thickness of the optical coupling layer is represented by t _oc (nm), the emission wavelength of the light emitting device is λ (nm), the average refractive index of the optical coupling layer is n _oc , and the average refractive index of the first conductive semiconductor layer is n _{1. When} the average refractive index of the substrate is expressed as n _sb , the relative refractive index difference Δ _(oc-1) between the optical coupling layer and the first conductive type semiconductor layer is expressed as Δ _(oc-1) ≡ ((n _oc ) ² − (N ₁ ) ² ) / (2 × (n _oc ) ² )
It is defined as In addition, the relative refractive index difference Δ _(oc−sb) between the optical coupling layer and the substrate is expressed as Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
It is defined as If the optical coupling layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the first conductivity type semiconductor layer, the condition for the waveguide to be multimode is that the normalized frequency is π / 2 or more. To (√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc be selected to satisfy At the same time, if the optical coupling layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the substrate, the condition for the waveguide to become multimode is that the normalized frequency is π / 2 or more. (√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc is selected so as to satisfy.

  Specifically, for example, when the average refractive index of the optical coupling layer is 2.50 and the average refractive index of the substrate is 1.70 at a wavelength of 460 nm, the thickness of the optical coupling layer is about 0.13 μm. If it is more, the above formula is satisfied. For example, if the average refractive index of the optical coupling layer is 2.50 at the wavelength of 460 nm and the average refractive index of the first conductive semiconductor layer is 2.499, the thickness of the optical coupling layer is about 3 If it is 3 μm or more, the above formula is satisfied.

  Thus, by realizing the light confinement, the optical coupling between the light emitting units is strengthened, and the integrated compound semiconductor light emitting device can easily realize uniform light emission. In addition, since the optical coupling layer exists also in the light emitting unit separation grooves between the light emitting units, relatively uniform light emission can be obtained from the vicinity of the light emitting unit separation grooves.

  Note that, if light is extremely confined in the optical coupling layer, the integrated compound semiconductor light-emitting device improves light emission uniformity but makes it difficult to extract light. Therefore, the thickness, material, structure, and configuration of the optical coupling layer are difficult. It is preferable to appropriately select a refractive index or the like so that wave guide is generated while being leaky to some extent. In particular, regarding the thickness, it is not desirable to make the optical coupling layer extremely thick and make the optical confinement of the waveguide excessive. For example, the upper limit is preferably 30 μm or less, and is preferably 10 μm or less. More desirably, the thickness is most desirably 5 μm or less.

  Furthermore, although the optical coupling layer exists in common in each light emitting unit, it is essential to select a material so that electrical insulation between each light emitting unit is not hindered. If, for example, all the light emitting units in the light emitting device are electrically coupled, when one of the light emitting units (a pair of pn junctions) deteriorates, the effect is not limited to a decrease in luminous intensity of the deteriorated light emitting units. Instead, it appears as a change in the current injection path throughout the integrated compound semiconductor light emitting device. For this reason, the deterioration of one light-emitting unit appears greatly as a characteristic variation of the light-emitting device. In the present invention, it is extremely preferable to select a material for the optical coupling layer so as to ensure electrical insulation between the light emitting units. Even if the light emitting unit being driven is deteriorated by being electrically insulated, the deterioration is only one problem of the light emitting unit. In addition, since the adjacent light emitting units are optically coupled, the output of light guided by the optical coupling layer is expected to some extent from the vicinity of the degraded light emitting unit portion, and the light emission intensity is also extremely reduced. Escape from doing. For this reason, the in-plane uniformity of the emission intensity including the deteriorated portion is relatively easily maintained.

Here, the optical coupling layer has only to be substantially insulative to such an extent that a change such as deterioration in one light emitting unit does not affect other units. For example, the specific resistance ρ _oc ( (Ω · cm) is preferably 0.5 (Ω · cm) or more. More preferably, it is 1.0 (Ω · cm) or more, more preferably 1.5 (Ω · cm) or more, and most preferably 5 (Ω · cm) or more. In order to have a high specific resistance, the optical coupling layer is preferably undoped. However, in the case where the optical coupling layer is composed of a plurality of layers, even if there is a partially doped layer, this is the undoped layer. There is no problem as long as the light emitting units are not electrically coupled to each other. In this case, the layer adjacent to the first conductivity type semiconductor layer (for example, the first conductivity type clad layer) may have the above specific resistance. In general, in a semiconductor, in a wavelength region transparent to a material, the refractive index of an undoped layer is intentionally doped and the refractive index is higher than that of a layer having a large number of carriers even in the same material. Therefore, the undoped layer is preferable from the viewpoint of optical characteristics and electrical characteristics.

  In the present invention, the optical coupling layer optically couples the light emitting units and distributes and distributes light, whereas the buffer layer described above reduces various mismatches when crystals grow on the substrate. Therefore, its function is different. However, the same layer may have two functions at the same time. In addition, when the optical coupling layer or the buffer layer is composed of a plurality of layers, some layers may have two functions. Furthermore, if the growth method and conditions are different even though the composition is the same, only one function may be provided.

  As described above, there is a separation groove between the light emitting units between the light emitting units of the present invention, and this separation groove is formed so as to divide at least the first conductivity type cladding layer. In general, a cladding layer or the like is doped in order to inject carriers into a pn junction in the light emitting unit, and in order to ensure electrical insulation, in the present invention, the cladding layer can be separated by each light emitting unit. Because it is necessary. Therefore, it is sufficient that the separation groove between the light emitting units reaches the interface of the optical coupling layer. However, in order to easily form the separation groove, it is usually formed partway through the optical coupling layer.

  Moreover, it is desirable that the side surface of the thin film crystal layer exposed in the separation groove between the light emitting units is covered with an insulating layer. This is because, when the light emitting device is flip-chip mounted on a submount or the like, it is possible to prevent the occurrence of a short circuit due to soldering on the side wall of the thin film crystal layer.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In a typical embodiment of the present invention, as shown in FIG. 1, there is a first conductivity type cladding layer 24 in contact with the optical coupling layer 23 and divided between the light emitting units. The first conductivity type clad layer 24 functions together with the second conductivity type clad layer 26 described later to the active layer structure 25 described later to efficiently inject carriers and suppress overflow from the active layer structure. In addition, it has a function for realizing light emission in the quantum well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The first conductivity type semiconductor layer includes a layer doped to the first conductivity type, in addition to the above-mentioned layer having a cladding function, for improving the function of the device like a contact layer or for manufacturing reasons. . In a broad sense, the entire first conductivity type semiconductor layer may be considered as the first conductivity type cladding layer, and in this case, the contact layer and the like can also be regarded as a part of the first conductivity type cladding layer.

  Generally, the first conductivity type cladding layer is made of a material having a refractive index smaller than an average refractive index of an active layer structure described later and a material larger than an average band gap of an active layer structure described later. It is desirable. Furthermore, the first conductivity type cladding layer is generally made of a material that forms a so-called type I band lineup in relation to the barrier layer in the active layer structure. Under such guidelines, the first conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure, and the like prepared for realizing a desired emission wavelength.

For example, when C + plane sapphire is used as a substrate, GaN grown at a low temperature as a buffer layer, and undoped GaN grown at a high temperature as an optical coupling layer, a GaN-based material, an AlGaN-based material as a first conductivity type cladding layer, An AlGaInN-based material, an InAlBGaN-based material, or a multilayer structure thereof can be used. Here, in the present invention, it is desirable that the average refractive index (n _oc ) of the optical coupling layer is larger than the average refractive index (n _sb ) of the substrate and the average refractive index of the first conductivity type cladding layer. In particular, the average refractive index (n ₁ ) of the first conductivity type semiconductor layer existing between the optical coupling layer and the active layer structure is preferably larger. Moreover, it is more than the average refractive index ( _nbf ) of a buffer layer, and it is preferable that it is especially larger than the average refractive index of a buffer layer.

The carrier concentration of the first conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 5 × 10 ¹⁷ cm ⁻³ or more, and most preferably 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and most preferably 7 × 10 ¹⁸ cm ⁻³ or less. Here, when the first conductivity type is n-type, Si is most desirable as a dopant.

  In the example of FIG. 1, the structure of the first conductivity type cladding layer shows a first conductivity type cladding layer composed of a single layer, but the first conductivity type cladding layer is composed of two or more layers. Also good. In this case, for example, a GaN-based material and an AlGaN-based material, an InAlGaN-based material, or an InAlBGaN-based material can be used. Further, the entire first conductivity type cladding layer may be a superlattice structure as a laminated structure of different materials. Furthermore, it is also possible to change the above-mentioned carrier concentration in the first conductivity type cladding layer.

  In the portion of the first conductivity type cladding layer in contact with the first conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistivity with the electrode.

  A part of the first conductivity type cladding layer is etched, and the exposed side wall, the etched part, etc. of the first conductivity type cladding layer are in contact with the first conductivity type side electrode described later. A structure in which all except one current injection region is covered with an insulating layer is desirable.

  In addition to the first conductivity type cladding layer, if necessary, a different layer may exist as the first conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

<Active layer structure>
An active layer structure 25 is formed on the first conductivity type cladding layer 24. The active layer structure is a layer that emits light by recombination of electrons and holes (or holes and electrons) injected from the above-described first conductivity type cladding layer and the second conductivity type cladding layer described later. A structure including a quantum well layer and including a barrier layer disposed adjacent to the quantum well layer or disposed between the quantum well layer and the cladding layer. Here, in order to realize high output and high efficiency, which are one object of the present invention, when the number of quantum well layers in the active layer structure is W and the number of barrier layers is B, B = W + 1 is preferably satisfied. That is, the relationship between the cladding layer and the entire layer of the active layer structure is formed as “first conductivity type cladding layer, active layer structure, second conductivity type cladding layer”, and the active layer structure is defined as “barrier layer, quantum well. It is desirable for high output to be formed as “layer, barrier layer” or “barrier layer, quantum well layer, barrier layer, quantum well layer, barrier layer”. FIG. 5 schematically shows a structure in which five quantum well layers and six barrier layers are stacked.

  Here, in the quantum well layer, the layer thickness is as thin as the de Broglie wavelength in order to express the quantum size effect and increase the luminous efficiency. For this reason, in order to achieve high output, it is desirable to provide not only a single quantum well layer but also a plurality of quantum well layers and separate them into an active layer structure. At this time, a layer that is separated while controlling the coupling between the quantum well layers is a barrier layer. In addition, it is desirable that the barrier layer exists for separation of the cladding layer and the quantum well layer. For example, when the cladding layer is made of AlGaN and the quantum well layer is made of InGaN, a form in which a barrier layer made of GaN exists between them is desirable. This is also desirable from the viewpoint of thin film crystal growth because it can be easily changed when the optimum temperature for crystal growth is different. When the clad layer is made of InAlGaN having the widest band gap and the quantum well layer is made of InAlGaN having the narrowest band gap, InAlGaN having an intermediate band gap can be used for the barrier layer. Furthermore, in general, the difference in the band gap between the cladding layer and the quantum well layer is larger than the difference in the band gap between the barrier layer and the quantum well layer, and considering the efficiency of carrier injection into the quantum well layer, The quantum well layer is preferably not directly adjacent to the cladding layer.

  It is desirable that the quantum well layer is not intentionally doped. On the other hand, it is desirable to dope the barrier layer to reduce the resistance of the entire system. In particular, the barrier layer is preferably doped with an n-type dopant, particularly Si. This is because Mg, which is a p-type dopant, easily diffuses in the device, and it is important to suppress the diffusion of Mg during high output operation. Therefore, Si is effective, and it is desirable that the barrier layer is doped with Si. However, it is preferable not to perform doping at the interface between the quantum well layer and the barrier layer.

  It is preferable that the active layer structure side wall of one element is covered with an insulating layer 30 as shown in FIG. In this case, when flip-bonding the element manufactured according to the present invention, there is an advantage that a short circuit due to solder or the like on the side wall of the active layer structure does not occur.

  In the present invention, it is desirable that the light emitted from the quantum well layers in each light emitting unit has substantially the same emission spectrum. This is for realizing uniform light emission as a surface light source as a compound semiconductor light emitting device.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductivity type cladding layer 26 efficiently injects carriers into the aforementioned active layer structure 25 together with the aforementioned first conductivity type cladding layer 24 and suppresses overflow from the active layer structure. It has a function for realizing light emission in the well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The second conductivity type semiconductor layer includes a layer doped to the second conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire second conductivity type semiconductor layer may be considered as the second conductivity type cladding layer. In that case, the contact layer or the like can also be regarded as a part of the second conductivity type cladding layer.

  In general, the second conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the above-mentioned active layer structure and a material larger than the average band gap of the above-mentioned active layer structure. Things are preferable. Furthermore, the second conductivity type clad layer is generally made of a material that forms a so-called type I band lineup, particularly in relation to the barrier layer in the active layer structure. Under such guidelines, the second conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure and the like prepared for realizing a desired emission wavelength. For example, when C + plane sapphire is used as the substrate and GaN is used as the buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material, an AlGaBInN-based material, or the like can be used as the second conductivity type cladding layer. . Further, a laminated structure of the above materials may be used. Also, the first conductivity type cladding layer and the second conductivity type cladding layer can be made of the same material.

The carrier concentration of the second conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 4 × 10 ¹⁷ cm ⁻³ or more, and further preferably 5 × 10 ¹⁷ cm ⁻³ or more. × 10 ¹⁷ cm ⁻³ or more is most preferable. Preferably 7 × ¹⁰ 18 ^{cm -3} or less as an upper limit, more preferably 3 × ¹⁰ 18 ^{cm -3} or less, and most preferably 2 × ¹⁰ 18 ^{cm -3} or less. Here, Mg is most desirable as the dopant when the second conductivity type is p-type.

  The structure of the second conductivity type cladding layer is an example of a single layer formed in the example of FIG. 1, but the second conductivity type cladding layer may be composed of two or more layers. Good. In this case, for example, a GaN-based material and an AlGaN-based material can be used. The entire second conductivity type cladding layer may be a superlattice structure composed of a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the second conductivity type cladding layer.

  In general, in a GaN-based material, when the n-type dopant is Si and the p-type dopant is Mg, the crystallinity of p-type GaN, p-type AlGaN, and p-type AlInGaN is n-type GaN, n It does not reach each of type AlGaN and n-type AlInGaN. Therefore, in device fabrication, it is desirable to implement a p-type cladding layer with poor crystallinity after crystal growth of the active layer structure. From this viewpoint, the first conductivity type is n-type and the second conductivity type is p-type. Is desirable.

  In addition, it is desirable that the thickness of the p-type cladding layer with poor crystallinity (which corresponds to the second conductivity type cladding layer in the case of taking a desirable form) is somewhat thin. This is because in the present invention in which flip-chip bonding is performed, the substrate side is the main light extraction direction, so there is no need to consider light extraction from the second conductivity type side electrode side described later, and a large area thickness. It is possible to form a membrane electrode. For this reason, it is not necessary to expect current diffusion in the lateral direction in the second conductivity type cladding layer as in face-up mounting, and it is necessary to make the second conductivity type cladding layer thin to some extent from the element structure. Is also advantageous. However, when it is extremely thin, the carrier injection efficiency is lowered, and therefore there is an optimum value. The thickness of the second conductivity type cladding layer can be selected as appropriate, but is preferably 0.05 μm to 0.3 μm, and most preferably 0.1 μm to 0.2 μm.

  In the portion of the second conductivity type clad layer that is in contact with the second conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  It is desirable that the exposed side wall of the second conductivity type cladding layer be entirely covered with an insulating layer except for a second current injection region that realizes contact with the second conductivity type side electrode described later.

  Furthermore, in addition to the second conductivity type cladding layer, a different layer may exist as necessary as the second conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in a portion in contact with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

  In addition, unless it is contrary to the summary of this invention, you may form the layer which does not enter into the above-mentioned category as needed as a thin film crystal layer.

<Second conductivity type side electrode>
The second conductivity type side electrode realizes a good ohmic contact with the second conductivity type nitride compound semiconductor, and becomes a reflection mirror in a good emission wavelength band when flip-chip mounted, When flip-chip mounting is performed, good adhesion to a submount using a solder material or the like is realized. For this purpose, the material can be selected as appropriate, and the second conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  When the second conductivity type is p-type and the second conductivity-type side electrode side of the second conductivity-type cladding layer is GaN, Ni, Pt, Pd, Mo, It is desirable to include any of Au. In particular, the first layer on the p-side cladding layer side of the second conductivity type side electrode is preferably Ni, and the surface of the second conductivity type side electrode opposite to the p-side cladding layer side is Au. desirable. This is because Ni has a large work function absolute value, which is convenient for p-type materials, and Au is preferable as the outermost material in view of resistance to process damage described later, mounting convenience, and the like.

  The second conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the second conductivity type carrier can be injected. For example, when the second conductivity type side contact layer is provided, the second conductivity type side electrode is in contact with it. Formed.

  It is preferable that one second conductivity type side electrode in the present invention is provided for each light emitting point 17. Further, in the present invention, particularly when the second conductivity type side electrode that is preferably implemented is a p-type electrode, the number or area of the second conductivity type side electrode and the first conductivity type side electrode described later In number or area, it is desirable that the number or area of the former be greater or wider than the number or area of the latter. This is because, in one light emitting unit, a portion contributing to substantial light emission is a quantum well layer in an active layer structure that exists under (or depending on how to see) the second conductivity type side electrode. Accordingly, it is preferable that the number or area of the second conductivity type side electrode in one light emitting unit is relatively larger or wider than that of the first conductivity type side electrode described later. Further, in relation to the current injection region, the number or area of the second current injection region and the number or area of the first current injection region are larger or wider than the number or area of the former. It is desirable. It is most desirable that both the electrode and the current injection region satisfy the above.

<First conductivity type side electrode>
The first-conductivity-type-side electrode achieves good ohmic contact with the first-conductivity-type nitride compound semiconductor, and when flip-chip mounted, it becomes a reflection mirror in a good emission wavelength band, When chip mounting is performed, good adhesion to a submount using a solder material or the like is realized. For this purpose, a material can be appropriately selected. The first conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  If the first conductivity type is n-type, the n-side electrode desirably includes a material selected from Ti, Al, and Mo, or all of them as constituent elements. This is because the absolute value of the work function of these metals is small. In addition, Al is usually exposed in the direction facing the main light extraction direction of the n-side electrode.

  In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. It is desirable not to. This is because when the light emitting device is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while ensuring a sufficient area to ensure sufficient adhesion with the submount or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like.

  Here, the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is preferably 15 μm or more. This is because a margin is required in the process of forming the first conductivity type side electrode, which is preferably formed by a photolithography process and a lift-off method.

  The first conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the first conductivity type carrier can be injected. For example, when the first conductivity type side contact layer is provided, the first conductivity type side electrode is in contact with it. Formed.

<Insulating layer>
When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” and “anywhere between different light emitting units”. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation. For example, single layer oxides, nitrides, fluorides and the like are preferable. Specifically, SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF It is preferably selected from _{x 1} , CaF _x , SrF _x , MgF _{x and the} like. These can secure insulating properties stably over a long period of time.

On the other hand, the insulating layer 30 can be a multilayer film of an insulator. Since this is a dielectric multilayer film, by appropriately adjusting the refractive index of the dielectric in the insulating layer, so-called high reflection having a relatively high optical reflectivity with respect to the light generated in the light emitting device. The function of the coating can also be expressed. For example, when the center value of the light emission wavelength of the element is λ, SiO _x and TiO _x are laminated to have an optical thickness of λ / 4n (where n is the refractive index of each material at the wavelength λ). Thus, it is possible to realize high reflection characteristics. In this way, when the chip is flip-chip bonded, it is possible to increase the light extraction efficiency in the main extraction direction, and an unintentional short circuit caused by soldering materials, etc. It is very desirable to prevent both of them.

Specifically, the reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident on the optical coupling layer from the first conductive type semiconductor layer side including the first conductive type cladding layer is reflected by the optical coupling layer is represented by R2. The reflectance of the light emitting wavelength of the light emitting device that is perpendicularly incident from the side of the second conductive type semiconductor layer including the second conductive type cladding layer in the insulating layer is reflected by the insulating layer as R12, and the first conductive in the insulating layer The light having the emission wavelength of the light-emitting device perpendicularly incident from the first conductive semiconductor layer side including the cladding layer is reflected by the insulating layer R11, and the active layer structure side including the quantum well layer in the insulating layer When the reflectance of the light emitting wavelength of the light emitting device that is perpendicularly incident is reflected by the insulating layer as R1q,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
It is preferable that the insulating layer is configured so as to satisfy at least one of the conditions, in particular, all of the expressions 1 to 3.

These are desirable ranges for an insulating layer formed of a dielectric multilayer film to function efficiently as an optical reflecting mirror. Further, considering the stability of the material and the range of refractive index, it is desirable that the dielectric film contains fluoride, and specifically, AlF _x , BaF _x , CaF _x , SrF _x , MgF It is desirable that any of _x is included.

<Submount>
The submount 40 has a metal layer and has both functions of current injection and heat dissipation to the flip chip mounted device. The base material of the submount is preferably one of metal, AlN, SiC, diamond, BN, and CuW. These materials are desirable because they are excellent in heat dissipation and can effectively suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as submount base materials. When the submount base material is selected from metals, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric or the like, SiNx formed by various CVD methods, SiO ₂ or the like is desirable.

  The light emitting device is bonded to the metal surface on the submount by various solder materials and paste materials. In order to sufficiently secure heat dissipation for high output operation and high efficiency light emission of the element, it is particularly desirable to join with metal solder. Examples of the metal solder include In, InAg, PbSn, SnAg, AuSn, AuGe, and AuSi. These solders are stable and can be appropriately selected in light of the operating temperature environment.

  Further, the integrated compound semiconductor light emitting device of the present invention can change the metal wiring on the submount freely so that each light emitting unit in one light emitting device can be connected in parallel, in series, or It is also possible to mix them.

〔Production method〕
Next, a method for manufacturing the integrated compound semiconductor light emitting device of the present invention will be described.

  In one example of the manufacturing method of the present invention, as shown in FIG. 6, first, a substrate 21 is prepared, and a buffer layer 22, an optical coupling layer 23, a first conductivity type cladding layer 24, an active layer structure 25 and a first layer are formed on the surface. The two-conductivity-type cladding layer 26 is sequentially formed by thin film crystal growth. The MOCVD method is desirably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. In addition, various processes may be performed after the formation of the thin film crystal layer. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  After the thin film crystal layer growth, in order to realize the shape shown in FIGS. 1 and 2 in the present invention, it is preferable to form the second conductivity type side electrode 27 as shown in FIG. That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. When the p-type electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface when the second conductivity type is p-type as a desirable form, this is compared with GaN-based materials. This is because the hole concentration in the p-GaN clad layer with a low effective activation rate is lowered by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. For this reason, in the present invention, after the thin film crystal growth, the formation of the second conductivity type side electrode is another process step (for example, a first etching step, a second etching step, a third etching step, or an insulating layer forming step, which will be described later) It is desirable that the second conductivity type side electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, etc.) be performed prior to this.

  In the present invention, when the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. Is a relatively stable metal such as Au, it is unlikely to be damaged by the process even after the subsequent process. Also from this viewpoint, in the present invention, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  In the present invention, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced similarly. it can.

  Various film formation techniques such as sputtering and vacuum deposition can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique, a metal mask, etc. Site-selective vapor deposition using can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 7, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In this step, the second conductivity type semiconductor layer (second conductivity type cladding layer 26) and the active layer structure 25 are divided, and the active layer structure 25, second conductivity type semiconductor layer (second conductivity type cladding layer 26) and The shape of the independent light emitting point 17 having the second conductivity type side electrode 27 is formed. In the first etching step, the first conductivity type side electrode described later is also intended to expose the semiconductor layer in which the first conductivity type carriers are injected. Therefore, another layer such as a clad layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask, which will be described in detail in a second etching process and a third etching process described later. Particularly preferably, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl Etching is preferably performed by plasma-excited dry etching using a gas such as ₄ . Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

  Next, as shown in FIG. 8, the light emitting unit separation grooves 12 are formed by the second etching step. In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. Generally, the total sum of the layers etched by the first etching process is usually about 0.5 μm. However, in the second etching process, all of the first conductivity type cladding layer 24 and a part of the optical coupling layer 23 are used. Is often 1 μm or more, for example, in the range of 1 to 5 μm, or in the range of 3 μm or more, for example, 3 to 7 μm. In some cases, it may be in the range of 3 to 10 μm, and more than 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that needs to etch the system material, a relatively thick SiNx film is required. For example, when etching a 4 μm GaN-based material in the second dry etching process, a SiNx mask exceeding 0.8 μm is required. However, at the SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the light emitting unit separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first, second, and third etching steps, while being easy to etch for patterning (preferably wet etching). What is required is one that can be etched and that has a good patterning shape, in particular, good linearity of the side wall portion. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in control of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, as will be described later, when a mask such as SrF ₂ is exposed to plasma of chlorine or the like during dry etching of the semiconductor layer, the etching rate at the subsequent removal of the mask layer is reduced before exposure to plasma of chlorine or the like. It has a tendency to decrease in comparison. For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _21, SiN x, SiO ₂ or the like mask 51, a metal fluoride Even if it does not exist in the entire lower portion of the chemical mask layer 52, it is sufficient if it is formed on a material that is at least susceptible to acid.

  By such a second etching step, as shown in FIG. 8, a separation groove between light emitting units is formed.

  Next, as shown in FIG. 9, the inter-device separation groove 13 is formed by a third etching process. In the third etching process, the thickness of the GaN-based material to be etched is extremely deep as compared with the second etching process because it is necessary to etch all of the buffer layer and the optical coupling layer, and is 5 to 10 μm. And may exceed 10 μm. Therefore, as described in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The preferable conditions and the like (including the laminated mask) are as described for the second etching step.

  The inter-device separation groove needs to be formed by dividing at least the first conductivity type cladding layer. In one preferred embodiment of the present invention, the inter-device separation groove 13 is formed so as to reach the substrate 21 as shown in FIG. In this case, in order to separate the device, the GaN-based material on the sapphire substrate is peeled off even when diamond scribing is performed from the side where the thin film crystal layer is formed in the process of scribing, breaking, etc. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove by etching part of a sapphire substrate (the same applies to other substrates such as GaN).

  On the other hand, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. For example, if the inter-device separation groove is formed up to the middle of the combined optical coupling layer and buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, Insulation can be maintained against dust (see FIGS. 17 to 20 for the form after the light emitting device is completed). In this case, the layer exposed from the side wall without being covered with the insulating layer preferably has high insulating properties. In the embodiment in which the inter-device separation groove is formed up to the middle of the optical coupling layer, the second etching step and the third etching step can be performed at the same time, so that there is an advantage that the process can be simplified.

Note that the first etching step, the second etching step, and the third etching step may be performed first or later. In order to simplify the process, it is also preferable that the first etching step is performed first, and the second etching and / or the third etching step is performed without removing the etching mask at that time. As shown in FIG. 21, first, a first etching mask 51 is formed of an acid-resistant material (preferably SiN _x ) such as SiN _x and SiO ₂ , and etching is performed so that the first conductivity type cladding layer 24 appears. Without removing 51, a second and / or third etch mask 52 with a metal fluoride layer is formed. And after implementing a 2nd and / or 3rd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that. Even when the second etching step and the third etching step are performed separately, the first etching mask 51 may be present until both etchings are completed.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the element manufacturing process and further for securing the scribe region.

  After the third etching step, an insulating layer 30 is formed as shown in FIG. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

Next, as shown in FIG. 11, a predetermined portion of the insulating layer 30 is removed, and the second conductive type side electrode exposed portion 37 from which the insulating layer is removed on the second conductive type side electrode 27, the first conductive type cladding. A first current injection region 36 from which the insulating layer has been removed is formed on the layer, and a scribe region 14 from which the insulating layer has been removed is formed in the inter-device isolation trench 13. The insulating layer 30 on the second conductivity type side electrode 27 is desirably removed so that the peripheral portion of the second conductivity type side electrode is covered with the insulating layer. That is, the surface area of the exposed portion of the second conductivity type side electrode is preferably smaller than the area of the second current injection region. Here, in order to prevent the occurrence of an unintentional short-circuit due to a margin of a photolithography process, particularly a photolithography process, or a solder material, the width of the width covered with the insulating layer from the periphery of the second conductivity type side electrode Among them, when the width of the narrowest portion is L _2W , L _2W is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material. L _2w is usually 2000 μm or less, preferably 750 μm or less.

For the removal of the insulating layer, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer is a single layer of SiN _x , dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

Further, the second conductivity type side electrode exposed portion 37, the first current injection region 36, and the scribe region 14 may be formed separately, but are usually formed by etching at the same time. If the width of the scribe region 14 (FIG. 2) is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _ws is usually 300 μm or less, preferably 200 μm or less.

  In a different embodiment of the present invention (corresponding to FIGS. 3 and 4), as shown in FIG. 12, the insulating layer on the side wall near the substrate in the inter-device separation groove is also removed, and the insulating layer non-formed portion is formed. 15 is provided. The simultaneous removal of a part of the insulating layer on the side wall of the groove can be formed by the following process, for example. When a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation groove 13 is formed by photolithography, and then wet etching is performed using an etchant capable of etching the insulating layer, the inside of the inter-device separation groove is obtained. The removal of the insulating layer on the substrate surface proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer covering the substrate side of the groove side wall is removed with a wet etchant. As shown in FIG. A non-existing shape is obtained. When the insulating layer is removed as described above, the side wall of the thin film crystal layer where the insulating layer is not present is preferably the side wall of the undoped layer. This is because, when flip chip mounting is performed, an unintended electrical short circuit does not occur even if solder for bonding with the submount adheres to the side wall.

  In the present invention, an unintended electrical short circuit or the like at the time of mounting can be prevented in either of the forms shown in FIGS. Usually, as shown in FIG. 11, it is sufficient to form the scribe region 14 where no insulating layer exists on the substrate. Even when the inter-device separation groove is formed up to the middle of the combined optical coupling layer and buffer layer, when the insulating film is deposited by the above process, it is deposited not on the substrate surface but on the groove bottom surface. Although the point is different, the same process can be adopted.

  Next, as shown in FIGS. 13 and 14, a first conductivity type side electrode 28 is formed. 13 and 14 show a structure in which a first conductivity type side electrode 28 is formed with respect to the structures of FIGS. 11 and 12, respectively. As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from Ti, Al, and Mo, or all of them. In addition, Al is usually exposed in the direction facing the main light extraction direction of the n-side electrode.

Various film formation techniques such as sputtering and vacuum deposition can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique or a place selection using a metal mask, etc. An appropriate vapor deposition or the like can be used as appropriate. Here, in order to allow a margin in the formation process to some extent, if the width of the narrowest portion among the portions where the first conductivity type side electrode is in contact with the insulating layer is L _1w , L _1w is 7 μm or more. Particularly, 9 μm or more is preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  In this example, the first conductivity type side electrode is formed so as to be in contact with a part of the first conductivity type cladding layer. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact with the first conductivity type side electrode. Can do.

  In the manufacturing method of the present invention, the first conductivity type side electrode is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is preferably formed with Al on the surface of the electrode material. In this case, if the n-side electrode is formed before the formation of the insulating layer like the second conductivity type side electrode, the surface of the n-side electrode, that is, the Al metal, will history the etching process of the insulating layer. . As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching an insulating layer, but Al has low resistance to various etchants including hydrofluoric acid, and such a process is effectively performed. Then, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the present invention, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer is effective in reducing damage to the electrode.

  After the structures of FIG. 13 (FIG. 2) and FIG. 14 (FIG. 4) are formed in this way, inter-device isolation grooves are used to separate each integrated compound semiconductor light-emitting device one by one. Then, the substrate is damaged by diamond scribe, and a part of the substrate material is ablated by laser scribe.

  When there is no thin-film crystal layer in the inter-device separation groove during the inter-device separation step (the structure shown in FIGS. 13 and 14 corresponds to this), no process damage is introduced into the thin-film crystal layer. Further, as shown in FIGS. 13 and 14, when there is no insulating layer in the scribe region, there is no possibility that the insulating layer is peeled off at the time of scribing.

  In addition, when the inter-device separation groove is formed to the middle of the combined optical coupling layer and buffer layer (for example, the groove is formed to the middle of the optical coupling layer at the same depth as the separation groove between the light emitting units). In this case as well, using the inter-device separation groove, the substrate is damaged by diamond scribe, and a part of the substrate material is ablated by laser scribe.

  After the scribe is completed, the integrated compound semiconductor light emitting device is divided into devices in a braking process, and is preferably mounted on the submount with a solder material or the like.

  As described above, the integrated compound semiconductor light emitting device shown in FIGS. 1 and 3 is completed.

  In the manufacturing method of the present invention, in addition to being able to effectively manufacture an advantageous structure having an optical coupling layer, as described, formation of a thin film crystal layer, formation of a second conductivity type side electrode, etching process (first etching process) , Second etching step, third etching step), formation of the insulating layer, removal of the insulating layer (formation of the exposed portion of the second conductivity type side electrode and the first current injection region and removal of the insulating layer in the vicinity of the inter-device separation groove) The formation of the first conductivity type side electrode is preferably carried out in this order. By this process order, the thin film crystal layer directly under the second conductivity type side electrode is not damaged, and the first conductivity type side electrode is also formed. A light emitting device without damage can be obtained. The device shape reflects the process flow. That is, the light emitting device has a structure in which the second conductivity type side electrode, the insulating layer, and the first conductivity type side electrode are laminated in this order. In other words, the second conductivity type side electrode is in contact with the second conductivity type clad layer (or other second conductivity type thin film crystal layer) without an insulating layer interposed, There is a portion covered with an insulating layer, and an insulating layer is interposed between the first conductivity type side electrode and the first conductivity type cladding layer (or other first conductivity type thin film crystal layer) around the electrode. There is a part.

  The features of the present invention will be described more specifically with reference to the following examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

Example 1
The semiconductor light emitting device shown in FIG. 15 was fabricated by the following procedure. Reference is made to FIGS. 6-10, 12 and 14 for relevant process diagrams.

A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a thickness of 10 nm is formed as a first buffer layer 22a on the first buffer layer 22a by using the MOCVD method. As the second buffer layer 22b, an undoped GaN layer having a thickness of 0.5 μm and a Si-doped (Si concentration: 7 × 10 ¹⁷ cm ⁻³ ) GaN layer having a thickness of 0.5 μm were stacked at 1040 ° C. Subsequently, an undoped GaN layer having a thickness of 3.5 μm was formed as the optical coupling layer 23 at 1035 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 3 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and the first conductivity type (n-type) first cladding layer 24 a is Si-doped (Si concentration 1.5 × A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to here generally corresponds to FIG. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x mask, thereby producing a SiN x etching mask. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas is performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion, and a plurality of The shape of the luminescent point was formed.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

Next, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method in order to perform a second etching process for forming the light emitting unit separating grooves 12 in each light emitting device. Next, the SrF ₂ film in the region for forming the separation groove between the light emitting units was removed, and a mask for forming the separation groove between the light emitting units of the thin film crystal layer, that is, the SrF ₂ mask for the second etching process was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in the portion corresponding to the light emitting unit separation groove. An active layer structure 25 composed of layers, an n-AlGaN first cladding layer 24a, an n-GaN contact layer 24c, an n-GaN second cladding layer 24b, and a thin-film crystal layer up to a part of the undoped GaN optical coupling layer 23, ICP dry etching using _two gases was performed. During this second etching step, the SrF ₂ mask was hardly etched. By this step, a separation groove between the light emitting units having a width of 10 μm was formed.

After forming the light emitting unit separating groove 12 by the second etching step, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, in order to carry out the third etching step for forming the inter-device separation grooves 13 between the respective compound semiconductor light emitting devices, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region where the inter-device separation groove was to be formed was removed, and an inter-device separation groove forming mask for the thin film crystal layer, ie, a third etching step SrF ₂ mask was formed.

Next, as a third etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier at portions corresponding to the device isolation trenches. Active layer structure 25 composed of layers, n-AlGaN first cladding layer 24a, n-GaN contact layer 24c, n-GaN second cladding layer 24b, undoped GaN optical coupling layer 23, buffer layer 22 (22a, 22b) and thin film All of the crystal layer was ICP plasma etched using Cl ₂ gas. During the third etching step, the SrF ₂ mask was hardly etched. By this process, an inter-device separation groove having a width of 50 μm was formed.

After forming the inter-device separation groove 13 by the third etching step, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode 27, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. In this case, SiN _x and SiO _x are formed one by one with a thickness that is ¼ of the optical wavelength with respect to the light emission wavelength of the device, and have a relatively high reflectance with respect to the light emission wavelength. I made it. The structure completed through the steps up to here generally corresponds to FIG.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer remaining on a part of the side wall of the substrate, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) on which the resist mask was not formed with a hydrofluoric acid-based etchant was removed. Further, due to the side etching effect using hydrofluoric acid, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped portion in the buffer layer was also removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

  Next, in order to form the n-side electrode 28, a resist pattern was formed by preparing to pattern the n-side electrode by a lift-off method using a photolithography method. Here, Ti 20 nm / Al 300 nm as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIG.

Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting device formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low reflection optical film were braked along this scribe line to complete each integrated compound semiconductor light emitting device. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal surface 41 of the submount 40 using the metal solder 42 to complete the light emitting device shown in FIG. At this time, an unintended short circuit or the like of the element did not occur.

(Example 2)
In Example 1, Example 1 was repeated except that the thin film crystal layer after the optical coupling layer 23 was formed was formed as follows. That is, in Example 1, after forming 3.5 μm-thick undoped GaN as the optical coupling layer 23 at 1035 ° C., the first conductive type (n-type) second cladding layer 24b is further doped with Si (Si concentration 5 × A 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm, and a Si-doped (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm as the first conductivity type (n-type) contact layer 24c. Further, a Si-doped (Si concentration 5.0 × 10 ¹⁸ cm ⁻³ ) Al _0.10 Ga _0.90 N layer having a thickness of 0.1 μm is formed as the first conductivity type (n-type) first cladding layer 24a. Formed. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, in the same manner as in Example 1, the light emitting device shown in FIG. 15 was completed. At this time, an unintended short circuit of the element did not occur.

In the processes of Examples 1 and 2, the SiN _x mask was removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask. It is also preferable to remove after the step.

  Furthermore, by stopping the etching in the third etching step in the middle of the buffer layer, the light emitting device shown in FIG. 20 can be manufactured (however, the insulating film is a multilayer dielectric film). Further, at that time, if an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape and side etching is not performed, the light emitting device shown in FIG. 19 is obtained. Moreover, the light-emitting device shown in FIG. 18 can be manufactured by stopping the etching in the third etching step in the middle of the optical coupling layer. At this time, if an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape and side etching is not performed, the light emitting device shown in FIG. 17 is obtained.

(Example 3)
The semiconductor light emitting device shown in FIG. 16 was manufactured by the following procedure.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 20 nm is first formed thereon as the first buffer layer 22a by using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C.

As the optical coupling layer 23, an undoped GaN layer having a thickness of 2 μm including a laminated structure of 10 layers each of undoped In _0.05 Ga _0.95 N of 3 nm and undoped GaN of 12 nm was formed. Here, the undoped GaN layer was grown at 850 ° C., and the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 3 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to simultaneously perform the second etching step for forming the light emitting unit separation grooves and the third etching step for forming the device separation grooves, an SrF ₂ mask was formed on the entire surface of the wafer by vacuum evaporation. . Next, the SrF ₂ film in the light emitting unit separation groove forming region and the device separation groove forming region is removed, and the thin film crystal layer separation etching mask, that is, the second etching step and the third etching step are simultaneously performed. An etching mask was formed.

Next, as the second and third etching steps to be performed simultaneously, the p-GaN contact layer 26c, the p-GaN second cladding layer 26b, and the p-AlGaN second layer in the portions corresponding to the light emitting unit separation grooves and the device separation grooves. One cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, an n-AlGaN first cladding layer 24a, an n-GaN contact layer 24c, an n-GaN second cladding layer 24b, an undoped InGaN / GaN optical The thin film crystal layer up to a part of the bonding layer 23 was subjected to ICP dry etching using Cl ₂ gas. During the second and third simultaneous etching steps, the SrF ₂ mask was hardly etched. By this process, the separation groove between the light emitting units was formed with a width of 6 μm.

The second and third etching steps were performed at the same time, and after forming the light emitting unit separation groove and the device separation groove, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiNx film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas is performed through the first clad layer 24a to the middle of the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion, and at the same time, a plurality of light emission A point shape was formed.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed as an insulating layer 30 on the entire surface of the wafer by p-CVD. Next, a p-side electrode exposed portion is formed on the p-side electrode 27 made of Pd—Au, an n-side current injection region is formed on the n-side contact layer, and an insulating layer present in the inter-device isolation trench In order to simultaneously remove a portion of the resist mask, a resist mask is formed using a photolithography technique, and then a portion where the resist mask is not formed using RIE plasma of SF ₆ gas, ie, p-side electrode exposure The formation of the portion, the formation of the n-side current injection region on the n-side contact layer 24c, and the removal of a part of the insulating layer existing in the inter-device isolation trench were performed. Here, the periphery of the p-side electrode was covered with a SiN _x insulating layer. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region. Further, for example, as described in the first and second embodiments, an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape, and the shape of FIG. 16 shows this shape.) Also, an appropriate etching mask shape is prepared by photolithography suitable for the planned shape, and the side etching of the insulating layer is not advanced, so that FIG. Shape is also possible. Further, in one light emitting unit, the insulating layer was removed so that the number and area of the n-side current injection regions were smaller and smaller than the number and area of the p-side current injection regions.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, p was not altered at all.

  Next, in order to form the n-side electrode 28, a resist pattern was formed by preparing to pattern the n-side electrode by a lift-off method using a photolithography method. Here, patterning was performed so that the number and area of the n-side electrodes in the light emitting unit were smaller and smaller than the number and area of the p-side electrodes. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, this element was joined to the metal surface 41 of the submount 40 using metal solder 42 to complete the light emitting device. At this time, an unintended short circuit or the like of the element did not occur.

Example 4
In Example 3, a light emitting device was fabricated in the same manner as in Example 3 except that the configurations of the substrate and the thin film crystal layer were changed as follows.

First, a c + -plane GaN substrate 21 (Si concentration: 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 300 μm is prepared. On top of this, undoped GaN having a thickness of 2 μm is first formed at 1040 ° C. as a buffer layer 22 using MOCVD. Formed.

Next, 4 μm of undoped GaN including a laminated structure of 20 layers each of undoped In _0.05 Ga _0.95 N of 3 nm and undoped GaN of 12 nm was formed as the optical coupling layer 23. Here, the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C., the adjacent undoped GaN layer was grown at 850 ° C., and the other GaN layers were grown at 1035 ° C.

Next, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. Si-doped (Si concentration 7 × ¹⁰ 18 ^{cm -3)} of the GaN layer was formed to 0.5μm thick, Si-doped (Si concentration: 5 × ^{10 18} as a further first conductivity type (n-type) first cladding layer 24a as A cm ^-3 ) Al _0.10 Ga _0.90 N layer was formed to a thickness of 0.1 µm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 8 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  Thereafter, the light emitting device was completed in the same manner as in Example 3. At this time, an unintended short circuit or the like of the element did not occur.

In Examples 3 and 4, the second and third etching steps were performed simultaneously, and then the first etching step was performed. However, the first etching step was performed first, and then the second and third etching steps were performed simultaneously. You may implement. In that case, it is also preferable to perform the second and third etching steps without removing the SiN _x mask used in the first etching step.

It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows the structure before completion of one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows the structure before completion of one example of the light-emitting device of this invention. It is a figure which shows an active layer structure typically. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. 1 is a view showing a light emitting device manufactured in Example 1. FIG. 6 is a view showing a light emitting device manufactured in Example 2. FIG. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light-emitting device 11 Light-emitting unit 12 Separation groove 13 between light-emitting units 14 Inter-device separation groove 14 Scribe area 15 Insulating layer non-formation part 17 Light emission point 21 Substrate 22 Buffer layer 22a First buffer layer 22b Second buffer layer 23 Optical coupling layer 24 first conductivity type cladding layer 24a first conductivity type first cladding layer 24b first conductivity type second cladding layer 24c first conductivity type (n-type) contact layer 25 active layer structure 26 second conductivity type cladding layer 26a second First conductivity type cladding layer 26b Second conductivity type second cladding layer 26c Second conductivity type (p-type) contact layer 27 Second conductivity type side electrode 28 First conductivity type side electrode 30 Insulating layer 35 Second current injection region 36 First current injection region 37 Second conductivity type side electrode exposed portion 40 Submount 41 Metal surface 42 Metal solder 45 Low reflection optical film 51 First etch Gumasuku (SiN _x, etc.)
52 Second and / or third etching mask (metal fluoride mask)

Claims (50)

An integrated compound semiconductor light emitting device having a substrate transparent to an emission wavelength and a plurality of light emitting units formed on the substrate,
The light emitting unit includes a compound semiconductor thin film crystal having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on the substrate. A layer, a second conductivity type side electrode, and a first conductivity type side electrode,
The main light extraction direction is the substrate side, and the first conductivity type side electrode and the second conductivity type side electrode are formed on the opposite side to the main light extraction direction,
The light emitting units are electrically separated by a light emitting unit separating groove provided between adjacent light emitting units,
In one light emitting unit, there are a plurality of light emitting points including the active layer structure, the second conductive type semiconductor layer, and the second conductive type side electrode, and at least one first conductive type side electrode. Provided, and the inside of one light emitting unit is electrically connected by the first conductive semiconductor layer,
Furthermore, the light emitted from one light emitting unit is provided between the substrate and the first conductive semiconductor layer in common between the plurality of light emitting units, and optically couples the plurality of light emitting units. An integrated compound semiconductor light emitting device comprising an optical coupling layer that distributes the light to other light emitting units.   The optical coupling layer is a layer provided in common between the plurality of light emitting units between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. The light-emitting device according to claim 1. When the average refractive index of the substrate at the emission wavelength is represented by n _sb , the average refractive index of the optical coupling layer is represented by no _oc , and the average refractive index of the first conductive semiconductor layer is represented by n ₁ ,
n _sb <n _oc and n ₁ <n _oc
The light-emitting device according to claim 1, wherein the relationship is satisfied. The emission wavelength of the light emitting device is λ (nm), the average refractive index of the substrate at the emission wavelength is n _sb , the average refractive index of the optical coupling layer is n _oc , and the physical thickness of the optical coupling layer is t _oc (nm ) And the relative refractive index difference Δ _(oc−sb) between the optical coupling layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
The light emitting device according to claim 1, wherein t _oc is selected so as to satisfy The emission wavelength of the light emitting device is λ (nm), the average refractive index of the optical coupling layer at the emission wavelength is n _oc , the average refractive index of the first conductivity type semiconductor layer is n ₁ , and the physical thickness of the optical coupling layer is t _oc (nm), and the relative refractive index difference Δ _(oc-1) between the optical coupling layer and the first conductivity type semiconductor layer is Δ _(oc-1) ≡ ((n _oc ) ^2- (n ₁ ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
The light emitting device according to claim 1, wherein t _oc is selected so as to satisfy The specific resistance ρ _oc (Ω · cm) of the entire optical coupling layer is
0.5 ≦ ρ _oc
The light emitting device according to claim 1, wherein the relationship is satisfied.   The light emitting device according to claim 1, wherein the optical coupling layer has a laminated structure of a plurality of layers.   In the plurality of light emitting units, the separation grooves between the light emitting units are removed between adjacent light emitting units from the surface of the thin film crystal layer to the interface of the optical coupling layer or a part of the optical coupling layer. The light emitting device according to claim 1, wherein the light emitting device is formed.   The light emitting device according to any one of claims 1 to 8, wherein a width of the separation groove between the light emitting units is in a range of 2 to 300 µm.   The light emitting device according to claim 1, further comprising a buffer layer in contact with the substrate.   The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway in the optical coupling layer. The light-emitting device according to claim 1.   The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway in the buffer layer. The light-emitting device according to claim 10.   The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed to reach the substrate. The light-emitting device according to claim 1.   The light-emitting device is divided from a scribe region in an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed by removing a part of the substrate. The light-emitting device according to claim 1.   Of the layers covering the entire bottom surface and side surfaces in the light emitting unit separation groove and exposed on the side surfaces of the light emitting device, at least the side surfaces of the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer. And an insulating layer that is in contact with a part of the first conductivity type side electrode on the main light extraction direction side and covers a part of the second conductivity type side electrode opposite to the main light extraction direction. The light-emitting device according to claim 1.   16. The light emitting device according to claim 15, wherein the insulating layer covers all of the layer exposed on the side surface of the inter-device separation groove.   The light-emitting device according to claim 16, wherein a region not covered with the insulating layer is provided as a scribe region on a groove bottom surface in the inter-device separation groove.   The insulating layer is not formed on the groove bottom surface in the inter-device separation groove, and of the layers exposed on the side surface of the inter-device separation groove, the layer does not have conductivity from the groove bottom surface side. 16. The light emitting device according to claim 15, wherein the light emitting device is not formed at least partially.   The light-emitting device according to claim 1, wherein the thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a V group. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting device according to claim 1, wherein: Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, light emitting device according to any one of claims 1 to 20, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.   The light-emitting device according to claim 15, wherein the insulating layer is a dielectric multilayer film including a plurality of layers. The reflectance at which the light having the emission wavelength of the light emitting device perpendicularly incident on the optical coupling layer from the first conductive semiconductor layer side is reflected by the optical coupling layer is represented by R2, and the second conductive type is applied to the insulating layer. The reflectance at which the light having the emission wavelength of the light-emitting device perpendicularly incident from the semiconductor layer side is reflected by the insulating layer is R12, and the light emission wavelength of the light-emitting device perpendicularly incident on the insulating layer from the first conductivity type semiconductor layer side is R12. R11 represents a reflectance at which light is reflected by the insulating layer, and R1q represents a reflectance at which light having a light emission wavelength of the light emitting device that is perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer. When
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The light-emitting device according to claim 15, wherein the insulating layer is configured to satisfy all of the conditions.   24. The light emitting device according to claim 1, wherein a surface of the substrate on a light extraction side is not flat. R3 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident on the substrate side from the optical coupling layer is reflected by the substrate, and the light having the light emission wavelength of the light emitting device that is perpendicularly incident on the light extraction side space from the substrate. When the reflectance reflected at the interface with the space is represented by R4,
R4 <R3
The light emitting device according to claim 1, further comprising a low reflection optical film on the light extraction side of the substrate.   26. The light-emitting device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   27. The light emitting device according to claim 1, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal surface by solder. A method of manufacturing an integrated compound semiconductor light emitting device having a plurality of light emitting units on the same substrate,
Forming an optical coupling layer on a substrate transparent to the emission wavelength;
Forming a thin film crystal layer having at least a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer;
Forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
In order to expose a part of the first conductivity type semiconductor layer on the surface and to form a plurality of light emitting points including the active layer structure, the second conductivity type semiconductor layer, and the second conductivity type side electrode, A first etching step of dividing the second conductive semiconductor layer and the active layer structure into a plurality of regions;
Forming at least one first conductivity type side electrode on the surface of the first conductivity type semiconductor layer exposed by the first etching step;
In order to form a separation groove between the light emitting units for electrically separating the light emitting units from each other, from the surface of the thin film crystal layer to the interface of the optical coupling layer, or from the surface of the thin film crystal layer to the optical coupling layer. A second etching step to remove a part,
A third etching step of removing at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer to form an inter-device separation groove for separating into a plurality of light emitting devices. A method of manufacturing an integrated compound semiconductor light emitting device.   29. The method according to claim 28, wherein the step of forming the optical coupling layer is performed as a part of the step of forming the thin film crystal layer and prior to the formation of the first conductive semiconductor layer. When the average refractive index of the substrate is represented by n _sb and the average refractive index of the optical coupling layer is represented by _noc ,
n _sb <n _oc
30. The method of claim 28 or 29, wherein the relationship of The emission wavelength of the light emitting device is λ (nm), the average refractive index of the substrate at the emission wavelength is n _sb , the average refractive index of the optical coupling layer is n _oc , and the physical thickness of the optical coupling layer is t _oc (nm ) And the relative refractive index difference Δ _(oc−sb) between the optical coupling layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
31. The method according to any one of claims 28 to 30, wherein t _oc is selected so as to satisfy. The light emission wavelength of the light emitting device is λ (nm), the average refractive index at the light emission wavelength of the optical coupling layer is n _oc , the average refractive index at the light emission wavelength of the first conductive semiconductor layer is n ₁ , and the physical properties of the optical coupling layer The specific thickness is t _oc (nm), and the relative refractive index difference Δ _(oc-1) between the optical coupling layer and the first conductivity type semiconductor layer is Δ _(oc-1) ≡ ((n _oc ) ² − (n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
32. The method according to claim 28, wherein t _oc is selected so as to satisfy The specific resistance ρ _oc (Ω · cm) of the entire optical coupling layer is
0.5 ≦ ρ _oc
The method according to claim 28, wherein the relationship is satisfied.   The method according to claim 28, wherein the optical coupling layer is formed as a stacked structure of a plurality of layers.   The method according to any one of claims 28 to 34, further comprising a step of forming a buffer layer on the substrate before the step of forming the optical coupling layer.   The third etching step is performed simultaneously with or separately from the second etching step, and etching is performed from the surface of the thin film crystal layer to the interface of the optical coupling layer or until a part of the optical coupling layer is removed from the surface of the thin film crystal layer. 36. The method according to any one of claims 28 to 35, wherein:   36. The method according to claim 35, wherein the third etching step is performed until a part of the buffer layer is removed from the surface of the thin film crystal layer.   36. The method according to any one of claims 28 to 35, wherein in the third etching step, etching is performed until the surface of the substrate is reached.   36. The method according to any one of claims 28 to 35, wherein in the third etching step, etching is performed so as to remove a part of the substrate. The second and third etching steps are performed by a dry etching method using a gas species selected from the group consisting of Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations of two or more thereof. 40. A method according to any of claims 28 to 39.   41. The method according to claim 40, wherein a patterned metal fluoride layer is used as an etching mask. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and 42. The method of claim 41 wherein the selected from the group consisting of.   The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order, and before the step of forming the first conductivity type side electrode, 43. The method according to any one of claims 28 to 42, further comprising a step of forming an insulating layer.   44. The method according to claim 43, wherein the step of forming the insulating layer is performed after the first to third etching steps. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, at least a part of the buffer layer is removed from the surface until at least a part of the optical coupling layer is removed (provided that the buffer layer is present), or at least. Etching is performed at a depth up to the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
36. The method according to claim 28, further comprising the step of removing a part of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove to form a scribe region. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, at least a part of the buffer layer is removed from the surface until at least a part of the optical coupling layer is removed (provided that the buffer layer is present), or at least. Etching is performed at a depth up to the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
A step of removing all of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove and a part of the insulating layer formed on the side wall of the inter-device separation groove on the groove bottom surface side. 36. A method according to any one of claims 28 to 35.   The second and third etching steps are performed at the same time, and etching is performed until the interface of the optical coupling layer or until a part of the optical coupling layer is removed to form the inter-device separation groove. 46. The method of claim 45.   The second and third etching steps are performed at the same time, and etching is performed until the interface of the optical coupling layer or until a part of the optical coupling layer is removed to form the inter-device separation groove. 48. The method of claim 46.   29. The method according to claim 28, further comprising a step of separating the light-emitting devices into a plurality of light-emitting devices, and a step of bonding the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount. 48. The method according to 48.   50. The method of claim 49, wherein the joining is performed with solder.

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