JP2009135476A - Etching method and method of manufacturing optical/electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor etching method capable of easily etching even a semiconductor layer that is hardly be etched, such as a group III-V nitride semiconductor, by a relatively simple process. <P>SOLUTION: The etching method includes: a step of forming a solid layer, such as a metal fluoride layer 3, at least as one portion of an etching mask on the surface of substrates 1, 2; a step of performing polymer solution processing to the solid layer; and a step of etching the substrates with the solid layer as a mask. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to an etching method and an optical / electronic device manufacturing method using the same. In particular, for etching compound semiconductors such as In _x Al _y Ga _(1-xy) N-based III-V group compound semiconductors (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The present invention relates to an optimum etching method, a light emitting diode (LED), a super luminescent diode, a light emitting device such as a semiconductor laser, a light receiving device such as a photodiode and a solar cell, and a manufacturing method of an electronic device such as a diode and a transistor. .

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet, near-ultraviolet, or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue, near-ultraviolet or ultraviolet LEDs with the illumination application in mind.

  Here, in order to increase the output of the element, that is, to improve the total radiant flux, it is indispensable to increase the size of the element and to secure the resistance against a large input power. In addition, an element that is sufficiently large compared to a normal LED as a point light source exhibits light emission characteristics as a surface light source, and is particularly suitable for illumination applications.

However, in an element in which the area of a normal small LED is simply increased in a similar manner, the uniformity of the light emission intensity of the entire element cannot generally be obtained. Therefore, it has been proposed to integrate LEDs on the same substrate. For example, JP-A-11-150303 (Patent Document 1) discloses an integrated light-emitting component in which individual LEDs are connected in series as a light-emitting component suitable as a surface light source. Japanese Laid-Open Patent Publication No. 2002-26384 (Patent Document 2) discloses an LED integration method for the purpose of providing an integrated nitride semiconductor light emitting device having a large area and good light emission efficiency. For integration, it is necessary to electrically isolate a pair of pn junctions that are a single light-emitting unit from other light-emitting units, and a technique for forming an effective “groove” in a nitride semiconductor layer is very important. Is important to.

In Japanese Patent Application Laid-Open No. 11-150303 (Patent Document 1), in order to completely electrically separate a pair of pn junctions that are a single light emitting unit between the units, Ni is used until the insulating substrate is exposed. It describes that a GaN layer is etched using a mask (see Patent Document 1, paragraph 0027). Also in Japanese Patent Application Laid-Open No. 2002-26384 (Patent Document 2), in order to separate a pair of pn junction portions which are a single light emitting unit from other light emitting units, an RIE (reactive ion etching) method is used. The SiO ₂ is used as a mask to etch the GaN-based material until it reaches the sapphire substrate, thereby forming separation grooves between the units (see Patent Document 2, FIG. 2, FIG. 3, and paragraph 0038).

However, a metal mask such as Ni used in Patent Document 1, an oxide such as SiO ₂ used in Patent Document 2, and a known nitride mask such as SiN are used as etching masks for GaN-based materials. The etching resistance is insufficient, the selectivity cannot be obtained, and there is a problem in the etching shape control. In addition, as a real problem, in order to etch a thick GaN-based epitaxial layer exceeding several μm with an oxide mask such as SiO ₂ , an extremely thick SiO ₂ mask is required, and there is a problem in productivity. .

  Incidentally, fluoride masks have been proposed in addition to the metal mask, oxide mask and nitride mask.

For example, Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B) Vol. 8, p. 28, 1990 (Non-patent Document 1), a SrF ₂ mask and an AlF were formed by lift-off using a PMMA resist as a mask for forming a separation groove of a GaN-based material, etching an AlGaAs-based material, and performing re-growth. It is described that _three masks are formed and that an AlSrF mask is formed by MBE at room temperature. However, according to the inventor's study, the quality of a fluoride-based mask formed at room temperature is not sufficient, and although it functions as an etching mask for a material that is relatively easy to etch, such as an AlGaAs-based material, As an etching mask for a material that is very difficult to etch, such as a material, the resistance is not sufficient. Also, room temperature SrF ₂ single mask formed by, as described later, the shape of the occurrence of unintended side-etched, the photo-mask or resist mask shape for use in patterning the SrF ₂ itself SrF ₂ to itself The transfer accuracy declines.

Similarly, Japanese Patent Application Laid-Open No. 6-310471 (Patent Document 3) describes that SrF ₂ and AlF ₃ produced by a lift-off method can be used for fine etching of GaAs, InGaAs, and InGaAsP-based materials. ing. Although this document does not describe the conditions for forming an etching mask, the mask patterning method is based on the lift-off method using a resist that can be exposed to electron beams. It is estimated that the film is formed at a temperature of about 100 ° C. As described above, a mask formed at about room temperature has insufficient resistance as an etching mask for a GaN-based material, and a photomask used when unintended side etching occurs or when SrF ₂ itself is patterned. In addition, there is a problem that the transfer accuracy of the shape from the resist mask shape to SrF ₂ itself is lowered.

Further, Japanese Patent Laid-Open No. 5-36648 (Patent Document 4) also discloses a technique of etching a GaAs-based material using a metal mask or SrF ₂ mask patterned by a lift-off method. Even in this document, there is no description of the film forming conditions of the SrF ₂ mask, but since the mask patterning is based on the lift-off method, the mask film forming temperature is from room temperature to about 100 ° C. It is estimated that
Japanese Patent Laid-Open No. 11-150303 JP 2002-26384 A JP-A-6-310471 JP-A-5-36648 Journal of Vacuum Science and Technology B (J. Vac. Sci. Technol. B) Vol. 8, p. 28, 1990

  The present invention has been made in view of conventional problems. Etching that allows easy and accurate etching of a semiconductor layer that is difficult to etch, such as a group III-V nitride semiconductor, by a relatively simple process. It aims to provide a method.

  Another object of the present invention is to provide a method of manufacturing an optical / electronic device such as a semiconductor device, particularly a semiconductor light-emitting device, having the etching method as one step.

  The present invention relates to the following matters.

1. Forming a solid layer made of metal fluoride on at least a part of the etching mask on the surface of the substrate;
Treating the solid layer with a polymer solution;
And etching the substrate using the solid layer treated with the polymer solution as a mask.

2. The polymer solution treatment step includes
2. The etching method according to 1 above, comprising: a sub-step: an application step of applying a polymer solution to the solid layer; and a sub-step: a step of removing the polymer on the solid layer.

  3. 3. The etching method according to 2 above, wherein the step of removing the polymer includes solvent washing.

4). After the polymer solution treatment step,
Forming a patterned resist mask on the solid layer;
Etching the solid layer using the resist mask as an etching mask;
The etching method according to any one of the above items 1 to 3, wherein

  5). 5. The etching method as described in 4 above, wherein the resist mask is formed of a photoresist.

  6). 6. The etching method as described in 4 or 5 above, wherein the step of etching the solid layer is performed by wet etching.

  7. 7. The etching method according to 6 above, wherein the etchant used for the wet etching contains at least one selected from the group consisting of hydrochloric acid, hydrofluoric acid and concentrated sulfuric acid.

  8). 8. The etching method as described in any one of 1 to 7 above, wherein the solid layer is formed at a temperature of 150 ° C. to 480 ° C.

9. The solid _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and etching method according to any one of the above 1 to 8, wherein the selected from the group consisting of.

  10. 10. The etching method as described in any one of 1 to 9 above, wherein the step of etching the substrate is performed by dry etching.

  11. 11. The etching method as described in 10 above, wherein the dry etching is plasma-excited dry etching using a gas species containing at least chlorine atoms.

  12 The etching method according to any one of the above items 1 to 11, further comprising a step of removing the solid layer with an etchant containing an acid or an alkali after the step of etching the substrate.

  13. Any one of the above 1 to 12, wherein the etching mask formed on the substrate has a multilayer structure portion of the solid layer and a second mask layer other than a substance constituting the solid layer. The etching method as described.

  14 14. The etching method according to any one of 1 to 13, wherein the substrate includes a group III-V nitride layer.

  15. 5. The etching method as described in 4 above, wherein the side etch amount measured from the edge of the patterned resist mask, which occurs when the solid layer is etched, is 6 μm or less.

16. Forming a solid layer having voids between fine particles as at least part of an etching mask on the surface of the substrate;
Treating the solid layer with a polymer solution;
And etching the substrate using the solid layer treated with the polymer solution as a mask.

  17. The manufacturing method of the optical / electronic device which has the etching method in any one of said 1-16 as 1 process.

  According to the present invention, it is possible to provide an etching method that can easily etch even a semiconductor layer that is difficult to etch, such as a group III-V nitride semiconductor, by a relatively simple process. In particular, according to the present invention, even if the original shape formed on the photomask, metal mask, etc. is a dense fine pattern, it is more faithful and more accurate than the conventional case after the etching is completed. It becomes possible to transfer as a planar shape of the etching object. Specifically, for example, the dimensions of the original shape formed on the photomask are made to coincide with each other with a much higher accuracy as the dimension after etching of the object to be etched, or at a desired projection magnification. It becomes possible to project with high accuracy. Generally speaking, “transfer accuracy” in the entire processing process is remarkably improved. Therefore, it is extremely useful for a method for manufacturing a semiconductor device, a semiconductor light emitting device, particularly an optical / electronic device involving etching of a group III-V nitride semiconductor.

In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”. In addition, the expression “numerical value 1 to numerical value 2” is used to mean a numerical value 1 or more and 2 or less.

  Furthermore, in the present invention, “epitaxial growth” includes, in addition to the formation of an epitaxial layer in a so-called crystal growth apparatus, a subsequent activation process of carriers by heat treatment, charged particle treatment, plasma treatment, etc. of the epitaxial layer. And described as epitaxial growth.

The etching method of the present invention is as described above.
(A) On at least a part of the etching mask on the surface of the substrate, a solid layer made of a metal fluoride or a solid layer having voids between fine particles (hereinafter, each may be simply referred to as “solid layer”). And a step of forming
(B) treating the solid layer with a polymer solution;
(E) etching the substrate using the solid layer treated with the polymer solution as a mask.

  In the solid layer, a change in the chemical and / or physical state (including the possibility of surface coating or the like) is caused by the polymer solution treatment in terms of phenomena. It is also possible that the components used for polymer solution treatment remain chemically and / or physically bound. By properly utilizing the change, the solid layer is extremely useful as an accurate etching mask.

  More specifically, when patterning a solid layer using a resist, side etching from the resist end of the solid layer itself is suppressed and pattern accuracy is improved. In addition, even in the process of forming a patterned solid layer on the surface of the substrate and then treating with a polymer solution, there are steps that cause side etching problems later, or dissolution of the solid layer becomes a problem. The present invention is considered to be effective even when such steps are included.

In a preferred embodiment of the present invention,
(A) forming a solid layer on at least a part of the etching mask on the surface of the substrate;
(B) treating the solid layer with a polymer solution;
(C) forming a patterned resist mask (for solid layer etching) on the solid layer;
(D) etching the solid layer using the resist mask as an etching mask;
(E) A step of etching the substrate using the solid layer as a mask (for substrate etching). Hereinafter, the present invention will be described in the order of the steps with reference to FIGS.

<Substrate>
In the present invention, a base structure (object structure = object to be etched) means an object to be etched by the etching method of the present invention, specifically, an object to be etched using a solid layer as a mask. The substrate described below means a normal substrate that supports a layer (for example, a semiconductor layer) or is used for crystal growth. As will be described later, the substrate may be a substrate to be etched (base structure = object to be etched). In the present invention, the configuration of the substrate material, shape, laminated structure and the like to be etched can take various forms.

  The material for the substrate is not particularly limited, and examples thereof include semiconductors, metals, and inorganic materials such as oxides and nitrides. The present invention is applicable to any substrate that can be etched by dry etching using a solid layer etching mask (hereinafter referred to as a patterned solid layer). However, since the solid layer etching mask made of a metal fluoride has extremely high dry etching resistance, a large etching selectivity can be secured even when applied to a substrate that is difficult to be etched by dry etching. Can be maximized.

  For example, although not particularly limited as a semiconductor material, semiconductors generally used in semiconductor devices such as III-V compound semiconductors such as silicon, germanium, diamond, and GaN, and II-VI compound semiconductors can be used. It is also suitable for etching oxides, nitrides, and oxynitride materials such as sapphire, aluminum oxide, aluminum nitride, boron nitride, silicon nitride, and silicon oxynitride. Furthermore, etching of metal or the like is also possible.

  There is no particular limitation on the shape and configuration of the base body. For example, when the object to be etched includes a semiconductor layer, the base body is the semiconductor substrate itself, the substrate (semiconductor substrate or oxide substrate such as sapphire) and the like. It may be a combination with a formed semiconductor layer, and if necessary, an insulating layer and / or a metal layer. In this case, only the semiconductor layer (including other layers such as an insulating layer as necessary) may be etched, or the substrate underneath may be etched.

  There is no limitation on the method for forming the semiconductor layer, and the method can be applied to a semiconductor layer formed by any method. When the present invention is applied to the manufacture of a light-emitting device, it is preferably a layer formed on a substrate by a thin film crystal growth technique such as epitaxial growth. Here, “thin film crystal growth” is so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), Plasma Assist MBE, PLD (Pulsed Laser Deposition), PED (Pulse Laser Deposition, PED (Pulse Laser Deposition), and PED (Pulse Laser Deposition). In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth apparatuses such as sputtering deposition (VPE), Vapor Phase Epitaxy (VPE), and Liquid Phase Epitaxy (LPE). Then, carrier activity by heat treatment, plasma treatment, etc. of thin film layer Treatment such as also described as the thin-film crystal growth, including.

  As a semiconductor layer material that is highly useful and generally difficult to dry etch, that is, a semiconductor to which the etching method of the present invention is preferably applied, the constituent elements are In, Ga, Al, B, and combinations of two or more thereof. The semiconductor layer preferably contains a nitrogen atom as a group V atom, and most preferably the semiconductor layer contains only a nitrogen atom as a group V atom. Specifically, the semiconductor layer is a group III-V nitride semiconductor such as GaN, InN, AlN, BN, InGaN, AlGaN, InAlN, InAlGaN, or InAlBGaN (hereinafter sometimes referred to as a GaN-based semiconductor for simplicity). Is mentioned. These may contain elements such as Si and Mg as dopants if necessary.

  In addition, this invention can be utilized suitably also for etching of semiconductors other than a III-V group nitride semiconductor, for example, GaAs type | system | group, GaP type | system | group, InP type | system | group, Si type | system | group.

The semiconductor layer may have a multi-layer structure. When a III-V nitride semiconductor (GaN-based) light emitting device is manufactured using the present invention, the semiconductor layer is thin film crystal grown (typically epitaxial growth). It is desirable to include a buffer layer, a first conductivity type cladding layer, a first conductivity type contact layer, an active layer structure, a second conductivity type cladding layer, a second conductivity type contact layer, and the like. Preferred substrates applicable to the present invention include GaN-based epitaxial layers on sapphire substrates and GaN-based epitaxial layers on GaN substrates.

  In the following description, as shown in FIG. 1, the case where the base to be etched has the substrate 1 and the semiconductor layer 2 formed thereon, and the etched portion is only the semiconductor layer 2 as a representative example. To do. However, the present invention can also be applied to the case where the semiconductor layer 2 does not exist and the substrate itself is a substrate subject to dry etching, and the substrate 1 and the semiconductor layer 2 are both subject to dry etching. As a preferable substrate in this case, a GaN-based epitaxial layer on a sapphire substrate and a GaN-based epitaxial layer on a GaN substrate can be exemplified as described above.

  The substrate in the case where the semiconductor layer is formed on the substrate is not particularly limited as long as the target semiconductor layer can be formed. The semiconductor substrate and the ceramic substrate, the insulating substrate and the conductive substrate, and the transparent substrate In addition, an opaque substrate or the like can be used. It is preferable to select appropriately considering the target semiconductor device, semiconductor manufacturing process, and the like.

For example, when a GaN-based light emitting device structure intended to extract light from the substrate side is used, it is desirable to use a substrate that is optically approximately transparent to the light emission wavelength of the device. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if absorption exists, the light output is not reduced by 50% or more due to absorption of the substrate. Further, an electrically insulating substrate is preferable for the production of the GaN-based light emitting device. This is because assuming that so-called flip chip mounting is used, even if a solder material or the like adheres to the periphery of the substrate, current injection into the semiconductor light emitting device is not affected. Specific materials in this case are selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO _3, and MgO, for example, in order to epitaxially grow an InAlGaN-based light emitting material or InAlBGaN-based material thereon. In particular, sapphire, GaN, and ZnO substrates are preferable. In particular, when a GaN substrate is used, the Si doping concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less, more preferably 8 × 10 ¹⁷ cm ⁻³ when an undoped substrate is intentionally used. The following is desirable from the viewpoint of electrical resistance and crystallinity.

  The substrate used in the present invention is preferably not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during epitaxial growth. When the semiconductor layer formed on the off-substrate is an epitaxial layer, the off-substrate has an effect of promoting good crystal growth in the step flow mode. Therefore, the off-substrate is also effective in improving the morphology of the semiconductor layer. Widely used as. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of a GaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As the off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in the GaN-based material formed on sapphire, it is a light emitting point in the active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching or heat treatment in advance in order to manufacture a semiconductor layer using a crystal growth technique such as MOCVD or MBE. In addition, it is possible to intentionally make the substrate growth surface of the substrate uneven, thereby preventing the threading transition that occurs at the interface between the epitaxial layer and the substrate from being introduced near the active layer of the light emitting device. It is. In this case, an etching mask layer is formed on the uneven surface, but in the present invention, a good etching mask layer can be formed also in that case.

The thickness of the substrate is selected in consideration of the target semiconductor device and semiconductor process. However, in the initial stage of device fabrication, for example, the thickness is set to about 250 to 700 μm, and the mechanical strength in the crystal growth of the semiconductor device and the element fabrication process is high. It is usually preferred to ensure that it is secured. After using this method to form the semiconductor layer by a method such as sputtering, vapor deposition, or epitaxial growth, it may be thinned during the process by a polishing step in order to facilitate separation into each element as appropriate.

<Solid layer>
In the etching method of the present invention, a solid layer made of a metal fluoride or a solid layer having a space between fine particles is formed on the surface of a substrate as at least a part of an etching mask. Metal fluoride is used as a preferable material from the viewpoint that it has a good film quality and can be used for subsequent etching of the metal fluoride layer and etching of the substrate. On the other hand, independent of the material viewpoint, when the solid layer is viewed from a structural viewpoint at the electron microscope level, a solid layer having voids between fine particles is used as a preferred structure.

  First, the case where a solid layer made of a metal fluoride is formed will be described in detail.

That is, the etching method of the first invention is
(A) forming a solid layer made of a metal fluoride on at least a part of the etching mask on the surface of the substrate;
(B) treating the solid layer with a polymer solution;
(E) using the solid layer treated with the polymer solution as a mask, and etching the substrate.

<Deposition of metal fluoride layer>
FIG. 2 shows a state in which the etching mask layer 3 is formed on the semiconductor layer 2. The etching mask layer includes at least one metal fluoride layer. In this example, the etching mask layer 3 has a single layer structure of a metal fluoride layer.

Examples of the material constituting the metal fluoride layer include divalent or trivalent metal fluorides, and in particular, Group 2 (Group 2A), Group 3 (Group 3A), Group 12 (Group 2B) and Long Periodic Table A fluoride of a metal element selected from Group 13 (Group 3B) is preferred. Specifically, SrF ₂ , CaF ₂ , MgF ₂ , BaF ₂ , AlF _{3 and the} like can be mentioned, and considering the balance between dry etching resistance and wet etching property, SrF ₂ , CaF ₂ and MgF ₂ are preferable. CaF ₂ and SrF ₂ are preferred, and SrF ₂ is most preferred.

As described above, there have been proposals for using a metal fluoride such as SrF ₂ as an etching mask, but the mask pattern is formed by a lift-off method using a photoresist. In order to form a mask pattern by the lift-off method, since the photoresist cannot be exposed to a high temperature, a metal fluoride such as SrF ₂ cannot be formed at a high temperature. A metal fluoride layer formed near room temperature generally has poor film quality. In a preferred embodiment of the present invention, the metal fluoride layer is patterned by an etching method, preferably a wet etching method. For this reason, the setting range of the film formation temperature is widened, film formation at a higher temperature is possible, and a metal fluoride patterning mask with better film quality can be formed.

  The metal fluoride layer is preferably formed at a temperature of 150 ° C. or higher. Those formed at 150 ° C. or higher are particularly excellent in adhesion to the base and form a dense film. At the same time, by etching the metal fluoride layer, the planar shape of the resist pattern can be accurately transferred to the planar shape of the metal fluoride layer. For example, when a linear opening is formed or a stripe pattern is formed, the metal fluoride layer is excellent in the linearity of the side wall and the transfer accuracy of the planar shape from the resist pattern. However, depending on the type of polymer solution used in the polymer solution treatment described later, even if the metal fluoride layer is formed in the range from near room temperature to less than 150 ° C., it can be used because of excellent transfer accuracy.

  In general, the film forming temperature is preferably a relatively high temperature. That is, it is more preferably 250 ° C. or higher, further preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, and becomes a dense film compared to those formed at a relatively low temperature, and exhibits high dry etching resistance. . When the metal fluoride is etched using a different material such as a resist mask or a metal mask as an etching mask, the patterning shape of the metal fluoride itself is also very high in transfer accuracy (the linearity of the side wall when the pattern is a straight line). Excellent controllability of the width of the opening. Such a metal fluoride layer is most preferred as an etching mask for the substrate. In the present invention, combined with the effect of the polymer solution treatment described later, the controllability and shape controllability of the opening width during patterning are extremely excellent. In the following description, film formation at a temperature of 150 ° C. or higher is sometimes referred to as “high temperature film formation” for short.

As described above, in order to form an etching mask with excellent adhesion to the substrate and a dense film, exhibiting high dry etching resistance, and having a patterning shape with excellent transfer accuracy, it can be formed at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to the etchant of wet etching described later becomes more than necessary, and patterning using a photoresist or its removal becomes difficult. In particular, as will be described later, when a mask such as SrF ₂ is exposed to plasma of chlorine or the like during dry etching of the semiconductor layer, the etching rate at the subsequent removal of the mask layer is reduced before exposure to plasma of chlorine or the like. It has a tendency to decrease in comparison. For this reason, the film formation of the metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride layer, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, in the metal fluoride layer after being exposed to the plasma at the time of dry etching of the semiconductor layer, the wet etching rate with respect to hydrochloric acid or the like at the time of removal has a property of decreasing, and film formation at an excessively high temperature is It becomes difficult to remove the metal fluoride layer that is no longer necessary after etching the semiconductor layer.

  Furthermore, if the metal fluoride film is formed at an excessively high temperature, an excessive thermal history is given to the substrate, the semiconductor layer, or a metal layer formed on the semiconductor layer as will be described later. In fabrication, the mask fabrication process can adversely affect the device.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

  Under the etching conditions of the semiconductor layer, the etching selectivity between the substrate such as the semiconductor layer and the metal fluoride layer is 40 or more, preferably 200 or more, more preferably 400 or more, which is a group III-V nitride semiconductor. But it is possible.

  As a method for forming the metal fluoride layer, a normal film forming method such as a sputtering method, an electron beam evaporation method, or a vacuum evaporation method can be employed. However, an etching mask having a low selectivity may be obtained by a method such as sputtering or electron beam evaporation. This is probably because electrons, ions, and the like directly collide with the fluoride, and depending on the conditions, the fluoride is probably dissociated into metal and fluorine. Therefore, in these film forming methods, it is necessary to appropriately select the film forming conditions, and the manufacturing conditions are limited. On the other hand, for example, the vacuum evaporation method by resistance heating is most desirable because there is no such problem. Note that even in the case of vapor deposition using an electron beam, resistance heating is used if it is an indirect heating such as heating the crucible containing the material with an electron beam, instead of direct application of the electron beam to the fluoride material. As good as the law. When a film is formed by these vapor deposition methods, a metal fluoride layer having excellent dry etching resistance can be easily formed.

Furthermore, the film formation rate of the metal fluoride layer such as SrF ₂ is preferably in the range of about 0.03 nm / sec to 3 nm / sec, more preferably about 0.07 nm / sec to 2.0 nm / sec, Is most preferably about 0.10 nm / sec to 1.0 nm / sec. A metal fluoride layer formed in this range is more desirable because it is a film having high adhesion to the base and ensuring resistance to plasma.

<Characteristics of solid layers from a structural perspective>
As described above, in the etching method of the present invention, the solid layer formed as at least a part of the etching mask has been described in detail from the viewpoint of material called metal fluoride. On the other hand, the present inventors have found that the solid layer can be viewed from a structural viewpoint at the electron microscope level independently of the material viewpoint.

That is, the etching method of the second invention is
(A) forming a solid layer having inter-microparticle voids as at least part of the etching mask on the surface of the substrate;
(B) treating the solid layer with a polymer solution;
(E) using the solid layer treated with the polymer solution as a mask, and etching the substrate.

  Here, the inter-fine particle voids refer to relatively macro voids that are spontaneously formed by selecting materials, formation conditions, and the like by a single film formation. The relatively macro voids exist between the fine particles constituting the solid layer as seen in FIGS. 21 and 22, and more specifically, for example, a size of about several nm to several tens of nm (usually 1 to 50 nm). ). A relatively macro void does not mean a void formed by, for example, artificially drilling and patterning a SiNx film by a normal photolithography process. Further, it does not mean a connecting portion having no gap between the individual crystals constituting the so-called polycrystal, such as a simple grain boundary found in the so-called polycrystal.

  Such voids between the fine particles can be confirmed when enlarged by SEM or the like as seen in FIG. 21 or FIG. 22 (surface photograph).

  In addition, the amount of voids between the fine particles existing on the upper surface of the solid layer can be estimated by the surface porosity measured by the following.

Here, the surface porosity of the solid layer used in the second etching method of the present invention is usually 0.5% or more, usually 15% or less, preferably 8% or less. If the surface porosity is too large, the denseness of the solid layer may be inferior and the dry etching resistance may be reduced. If the surface porosity is too small, the treatment effect of the liquid in the present invention may be insufficient. For example, the surface porosity of the SrF ₂ layer in FIG. 21 and the CaF ₂ in FIG. 22 is about 2.7% and about 0.9%, respectively.

<Measurement method of surface porosity>
(I) A solid layer film is photographed with an electron microscope such as SEM, and the sum of the areas of the voids in the photographed part is measured and calculated. At this time, on the surface of the solid layer formed into an image such as a photograph, the fine particle portion and the void portion between the fine particles can be recognized as image contrast. Based on this, the sum of the areas of the gaps is obtained.
(Ii) Measure and calculate the area of the photographed part (the entire solid layer including the void part).
(Iii) The surface porosity is calculated by the following formula.

Surface porosity = sum of the area of the void portion / area of the photographed portion It is known that there is generally an error of 10% when measuring using an SEM or the like. Further, there are errors when the SEM image is out of focus due to surface irregularities, and errors that appear to change the position of the edge of the gap due to image contrast processing. As a result, there is a possibility that the measured value of the surface porosity has an error within about ± 50%.

  There are no particular limitations on the material that constitutes the solid layer having the interparticle space, but as described above, from the viewpoint of ensuring good film quality and performing good etching of the solid layer and the subsequent substrate. A fluoride is preferable.

The solid layer having voids between fine particles needs to be formed with a dense film in order to ensure high dry etching resistance. For example, even a solid layer with high etching resistance such as SrF ₂ can be formed as shown in FIG. Or there are voids between the grown fine particles as described in FIG. The details of the mechanism of the side etching suppression effect are unknown and are not speculative, but the resistance to the etchant is improved, the effect of repelling the etchant (hydrophobicity), the affinity for the photoresist (for solid layer etching) and / or Alternatively, it is considered that the improvement in permeability, the effect of suppressing fine particle dropout or the like is caused singly or in combination, and the effect is particularly caused by the presence of voids between the fine particles, and the contact of the polymer solution with these voids. It is considered that this is achieved by a physical change.

  Hereinafter, an embodiment common to the case of forming a solid layer made of a metal fluoride (first etching method of the present invention) and the case of forming a solid layer having a fine particle gap (second etching method of the present invention) Will be described in detail. The “solid layer” described below means both a solid layer made of a metal fluoride and a solid layer having voids between fine particles, unless otherwise specified.

In the present invention, the etching mask layer may be a single layer film of a solid layer, a multilayer film thereof, or a multilayer structure with a second mask layer other than a substance constituting the solid layer. In the present invention, it is only necessary that the solid layer is exposed to the surface when the semiconductor layer is etched so that the underlying structure can be protected. Therefore, another layer may be formed on the semiconductor layer side in order to protect the semiconductor or a component formed on the semiconductor or for other purposes. In one embodiment of the present invention, for example, as described later, the second mask is used to prevent the metal layer formed on the surface of the semiconductor layer from being removed when the solid layer is finally removed. It is also preferable to use a multilayer film in which a film such as SiN _x or SiO _x is formed below the solid layer as a layer. In addition to the second mask layer formed below the solid layer, a third mask layer or the like may be provided above the solid layer. These can be appropriately selected according to the purpose.

<Polymer solution treatment of solid layer>
Next, the formed solid layer is treated with a polymer solution. This polymer solution treatment step has an effect of suppressing side etching during patterning of a solid layer using another mask material described later, and is an essential step for improving transfer accuracy.

  Any method may be employed as the method for bringing the polymer solution into contact with the solid layer. For example, the method in which the substrate on which the solid layer is formed is immersed in the polymer solution, or the surface of the substrate on which the solid layer is formed. And a method in which only the surface of the solid layer is brought into contact with the polymer solution by surface tension, and a method in which the polymer solution is applied to the surface of the solid layer by spraying. In order to form a polymer layer once on a substrate, more specifically, spin coating, screen printing, dip coating, spray coating, curtain coating, slit coating, roll coating, dispenser coating, etc. The coating method can be used. When the polymer solution is applied, vibration may be applied so that the surface of the solid layer (including the surface of the space between the fine particles) is sufficiently in contact. The temperature of the solution application is not particularly limited as long as the polymer solution can be applied, and may be determined in consideration of the melting point, boiling point, etc. of the solvent contained, but generally room temperature (about 10 ° C. to 35 ° C.) is adopted. do it.

  After contacting the polymer solution, depending on the type of solvent contained, various states of polymer exist on the solid layer, from a flowable solution state to a solid state where the solvent evaporates and almost no solvent exists. Yes. Thereafter, the process may be immediately transferred to the polymer removal step, or the solvent may be dried to form a solid polymer layer once.

  When performing this drying, it may be set as appropriate depending on the type of solvent and polymer. For example, the drying may be performed by heating in the range of room temperature (15-30 ° C.) to 200 ° C., preferably in the range of room temperature to 150 ° C. Good. The heating time may be appropriately selected, and is, for example, 10 seconds to 1 hour, preferably about 20 seconds to 30 minutes. Further, the heating may be performed in multiple stages.

  The polymer is then removed at least partially from on the solid layer or from the entire surface on the solid layer. As a removal method, a method and conditions that do not hinder at least a subsequent step ((c) formation of a resist mask (for solid layer etching), (d) solid layer etching) and can exhibit the effect of the polymer solution treatment. May be selected. Examples thereof include solvent cleaning, plasma ashing, and combinations thereof. In particular, it is preferable to use a solvent in which the polymer can be dissolved. As the solvent, any solvent can be used as long as it can dissolve the remaining polymer without affecting the substrate or the like. In the case of a polymer capable of organic solvent, specifically, for example, lower alcohols such as methanol, ethanol and isopropyl alcohol (preferably having a carbon number of 4 or less), ketones such as acetone and methyl ethyl ketone, and the like can be used. Two or more organic solvents may be used in combination, and in this case, they can be mixed and / or used sequentially. It is also preferable to wash with water after removing the polymer residue with an organic solvent. Then, after drying appropriately, it progresses to the formation process of the next resist mask (for the etching of a solid layer). Drying may be performed by spin drying, blowing dry air, or the like.

  The polymer solution that can be used for the polymer solution treatment of the present invention as described above contains at least a polymer and a solvent that dissolves the polymer. Here, the term “polymer” includes thermoplastic resins and thermosetting resins, as well as water-soluble resins such as cellulose derivatives and polysaccharides.

  As the polymer, preferably phenol resin, urea resin, melamine resin, epoxy resin, polyurethane, polyvinyl chloride, polystyrene resin, polyamide, polyimide, acrylic resin, polyester resin, ABS resin, polyvinyl alcohol, polyoxyethylene, cellulose derivative (Methyl cellulose, hydroxymethyl cellulose, carboxymethyl cellulose) and the like.

  Preferably, a polymer used as a base resin of the resist material is used, and includes, for example, phenol resins such as phenol novolac and cresol novolac; polymethyl methacrylate, hydroxyethyl methacrylate, other poly (meth) acrylic acid ester derivatives, etc. ) Acrylic resins such as polymers; and polystyrene resins such as (co) polymers including polystyrene, polyhydroxystyrene, and other polystyrene derivatives.

  What is necessary is just to use an organic solvent and / or water suitably as a solvent which melt | dissolves a polymer. As the organic solvent, alcohols, ketones, esters, ethers, non-aqueous polar solvents and the like are preferable.

  Examples of alcohols include aliphatic monoalcohols such as methanol, ethanol, n-propyl alcohol, iso-propyl alcohol, octanol, decanol, etc., preferably about 20 carbon atoms, ethylene glycol, propylene glycol, butanediol, glycerin, polyoxy Examples thereof include polyhydric alcohols such as ethylene. The alcohol is preferably a polyhydric alcohol and a derivative in which some OH groups are etherified or esterified. The etherified compounds include ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol mono-n-propyl ether, ethylene glycol mono-n-butyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, diethylene glycol mono-n. -Propyl ether, diethylene glycol mono-n-butyl ether, triethylene glycol monomethyl ether, triethylene glycol monoethyl ether, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol mono-n-propyl ether, propylene glycol mono-n- Butyl ether, dipropylene glycol monomethyl (Poly) alkylene glycol monoalkyl ethers such as ether, dipropylene glycol monoethyl ether, dipropylene glycol mono-n-propyl ether, dipropylene glycol mono-n-butyl ether, tripropylene glycol monomethyl ether, tripropylene glycol monoethyl ether There can be mentioned. Moreover, as aromatic alcohol, benzyl alcohol, methylbenzyl alcohol, p-isopropylbenzyl alcohol, 1-phenylethanol, phenethyl alcohol, 1-phenyl-1-propanol, cinnamyl alcohol, xylene-α, α′diol, salicyl alcohol , P-hydroxybenzyl alcohol, anisyl alcohol and the like.

  Examples of the ketones include ketones having 20 or less carbon atoms, more preferably 10 or less, such as acetone, methyl ethyl ketone, diethyl ketone, cyclohexanone, methyl isoamyl ketone, and 2-heptanone.

  Esters include ethyl acetate, n-propyl acetate, i-propyl acetate, n-butyl acetate, i-butyl acetate, n-pentyl formate, i-pentyl acetate, n-butyl propionate, ethyl butyrate, n-butyrate Alkyl esters such as propyl, i-propyl butyrate and n-butyl butyrate (preferably having 20 or less carbon atoms, more preferably 12 or less carbon atoms); methyl 2-hydroxypropionate, ethyl 2-hydroxypropionate, 2 -Lactic acid alkyl esters such as butyl hydroxypropionate; ethyl 2-hydroxy-2-methylpropionate, methyl 3-methoxypropionate, ethyl 3-methoxypropionate, methyl 3-ethoxypropionate, ethyl 3-ethoxypropionate , Ethyl ethoxyacetate, ethyl hydroxyacetate, 2-hydroxy Substituted alkyl esters having an alkoxy or oxaalkyl group such as methyl 3-methylbutanoate, 3-methyl-3-methoxybutyl acetate, 3-methyl-3-methoxybutylpropionate (preferably having 20 or less carbon atoms, Preferably 12 or less carbon atoms); other esters such as methyl pyruvate, ethyl pyruvate, n-propyl pyruvate, methyl acetoacetate, ethyl acetoacetate, ethyl 2-oxobutanoate; ethylene glycol monomethyl ether acetate, ethylene glycol Monoethyl ether acetate, diethylene glycol monomethyl ether acetate, diethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether (Poly) alkylene glycol monoalkyl ether acetates such as acetate can be mentioned.

  Examples of ethers include linear or branched dialkyl ethers such as dimethyl ether and diethyl ether; and cyclic ethers such as tetrahydrofuran, tetrahydropyran, oxetane and dioxane.

  Non-aqueous polar solvents include sulfur-containing compounds such as dimethyl sulfoxide (DMSO) and sulfolane; nitrogen-containing compounds such as N, N-dimethylacetamide, N, N-dimethylformamide (DMF) and N-methyl-2-pyrrolidone A compound etc. can be mentioned.

  The details of the mechanism of the side etching suppression effect that can be achieved by performing the characteristic polymer solution treatment in the present invention is not clear and is not speculative, but the resistance to the etchant is improved and the effect of repelling the etchant (hydrophobic) It is considered that the improvement, the affinity to the photoresist (for solid layer etching) and / or the permeability, the effect of suppressing the drop-off of the fine particles, etc. are produced singly or in combination.

<Patterning of solid layer>
As described above, the polymer solution-treated solid layer is patterned into a desired shape, preferably by etching. For the etching of the solid layer, conditions that allow the solid layer to be etched and that are different from the etching conditions of the semiconductor layer are selected, and wet etching using an acid or alkali is particularly preferable. In this invention, the side etching of a solid layer is suppressed by performing said polymer solution process.

  The patterning of the etching mask layer including the solid layer is preferably performed using another mask. For example, as shown in FIG. 3, a resist mask layer 4 made of a photoresist material is formed on the etching mask layer 3, and the resist mask layer 4 is patterned as shown in FIG. 4 by a normal photolithography method such as exposure and development. To do. The photoresist used may be either a positive type or a negative type.

  Thereafter, as shown in FIG. 5A, the etching mask layer 3 including the solid layer is etched using the patterned resist mask layer 4 as a mask.

As an etchant for wet etching, an aqueous solution containing an acid such as hydrochloric acid, hydrofluoric acid, sulfuric acid, phosphoric acid or nitric acid is preferable, and an etchant containing an oxidizing agent such as hydrogen peroxide or a diluent such as ethylene glycol, if necessary. Can be mentioned. The etchant is selected in consideration of the material of the solid layer and the film forming conditions, but preferably contains at least hydrochloric acid, concentrated sulfuric acid, hydrofluoric acid and the like. For example, when patterning SrF ₂ , hydrochloric acid is desirable, to pattern the CaF ₂ is concentrated sulfuric acid, hydrochloric acid is desirable, in particular concentrated sulfuric acid is preferable. Etching with alkali is also possible, and in any etching, light irradiation, heating, etc. may be used in combination.

  Since wet etching is generally isotropic etching, it is usually accompanied by undesirable side etching. As schematically shown in FIG. 5B, the end of the etching mask layer 3 including the solid layer recedes from the mask end of the resist mask layer 4 for side etching. The backward distance is defined as a side etch amount L. As the side etch amount L is smaller, the pattern of the resist mask layer 4 is faithfully transferred, so that a precise pattern can be formed.

  In the present invention, by treating the solid layer with a polymer solution, the amount of side etching becomes extremely small, and as a result, the etching mask layer 3 including the solid layer can be precisely patterned with high fidelity to the resist pattern. Therefore, the shape of the semiconductor layer 2 (= substrate) patterned by etching using the etching mask layer 3 as a mask also improves the transfer accuracy with respect to the resist pattern.

  In the present invention, when etching a solid layer of about 400 nm, the side etch amount L can be made 6 μm or less, preferably 4 μm or less, more preferably 3 μm or less. is there. For this reason, since it is relatively difficult to etch, such as a group III-V nitride semiconductor, it is possible to form a fine pattern even with a substrate that has been difficult to pattern with a fine shape.

  Furthermore, since the pattern boundary of the solid layer appears very sharply after patterning by the polymer solution treatment, the transfer accuracy becomes higher in the dry etching of the substrate using the solid layer as a mask.

  In this way, after the wet etching of the etching mask layer 3 is completed and the structure of FIG. 5A is formed, the resist mask layer 4 which is normally unnecessary is removed, and the semiconductor layer is formed on the semiconductor layer as shown in FIG. A structure in which the patterned etching mask layer 3 is formed is obtained.

<Semiconductor layer etching>
In the step of etching the semiconductor layer, as shown in FIG. 7, the semiconductor layer 2 is etched using the etching mask layer 3 as a mask.

A dry etching method is preferably used for etching the semiconductor layer. In the dry etching method, conditions such as gas type, bias power, and degree of vacuum can be appropriately selected based on the material, crystallinity, and other properties of the semiconductor layer. When the semiconductor layer is a group III-V nitride semiconductor, the dry etching gas type is preferably a chlorine-based gas containing Cl element as a molecule constituting the gas, and Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof are desirable. The chlorine-based plasma generated by these gas species can achieve a large selectivity between the GaN-based material and the material forming the high-temperature solid layer during dry etching. The nitride semiconductor layer can be etched with little etching of the solid layer forming material formed at a high temperature. As a result, etching of the semiconductor layer with excellent shape controllability can be realized. In the dry etching, the thickness of the solid layer is hardly reduced, but the film characteristics, particularly the resistance during wet etching, change, and the wet etching rate tends to decrease.

Here, the plasma generation method at the time of dry etching may be any of capacitively coupled plasma generation (CCP type), inductively coupled plasma generation (ICP type), plasma generation based on electron cyclotron resonance (ECR type), etc. Such a method can also be applied. However, in the present invention, it is desirable to generate chlorine-based plasma by inductively coupled plasma generation. This is because the plasma density can be increased as compared with other methods, which is advantageous when etching a group III-V nitride semiconductor material or the like. Here, the plasma density during dry etching is preferably 0.05 × 10 ¹¹ (cm ⁻³ ) to 10.0 × 10 ¹¹ (cm ⁻³ ), and more preferably 1 × 10 ¹¹ (cm ³ ). ⁻³ ) to 7.0 × 10 ¹¹ (cm ⁻³ ). And since the solid layer formed into a high temperature by this invention has high etching tolerance, even the high plasma density plasma formed by the inductive coupling system shows sufficient tolerance.

For example, when a nitride such as SiN _x or SiO _x , an oxide, or a metal such as Ni is used as a mask, the selection ratio between the nitride semiconductor layer and the mask is about 5 to 20, but the solid layer mask of the present invention. Then, a selectivity of 100 or more can be realized with respect to the nitride semiconductor layer. Therefore, the method of the present invention is particularly preferably used when the III-V nitride semiconductor layer is etched deeply. Even in the case of a III-V nitride semiconductor layer, the etching depth can be applied even if it exceeds 1 μm, preferably 2 μm or more, more preferably 3 μm or more, most preferably 5 μm or more, and even more than 10 μm. . Furthermore, although depending on the material and thickness of the solid layer mask and the material of the semiconductor layer, when a sufficiently thick SrF ₂ mask is formed and the semiconductor layer is etched, a very thick layer can be etched. The thickness of the semiconductor layer to be etched is generally 50 mm or less, preferably 35 mm or less, more preferably 5 mm or less, still more preferably 1 mm or less, and most preferably 500 μm or less. When etching an extremely thick semiconductor layer, using a SrF ₂ mask, when etching a GaN substrate having a thickness of about 3 mm to 35 mm, further, a GaN epitaxial layer grown on the substrate is used as a substrate. For example, most of the thickness and the thin film crystal growth layer are etched at the same time. Of course, it is possible to etch only the thin film crystal growth layer of about 7 μm without etching the substrate. At that time, since the selection ratio is large, the width of the groove by etching can be shortened as appropriate. For example, the width can be 100 μm or less, preferably 10 μm or less, and further 3 μm or less. The aspect ratio (depth / width) of the groove depth and the groove opening width can be selected as appropriate. In the case of a III-V nitride semiconductor layer, it can be 0.1 or more, preferably 2 or more. Yes, up to about 50, for example about 30 is possible.

  In addition, the depth of etching the semiconductor layer in the present invention can be selected as appropriate, and FIG. 7 shows the case where the semiconductor layer is completely etched up to the substrate, but it is also possible to etch halfway through the semiconductor layer. Moreover, it is also possible to continuously etch a part of the substrate (which may be a non-semiconductor material such as sapphire) by changing the etching gas type or the like. It is possible to appropriately select the degree of etching or the layer constituting the semiconductor layer.

After the etching of the semiconductor layer shown in FIG. 7 is completed, the etching mask layer may be removed as necessary, or a different process may be performed while leaving the etching mask layer. In general, it is preferable to remove the etching mask layer.

  FIG. 8 shows the structure after the etching mask layer 3 is removed. The solid layer constituting the etching mask layer 3 may be removed by any method. For example, the solid layer can be removed with an etchant containing an acid or an alkali. In the patterning process of the solid layer described above, the conditions that the solid layer is easily etched and the semiconductor layer is difficult to be etched are selected. However, the same conditions as the patterning can be adopted in the process of removing the solid layer.

Accordingly, as an etchant for wet etching, an aqueous solution containing an acid such as hydrochloric acid, hydrofluoric acid, sulfuric acid, phosphoric acid, or nitric acid is preferable. If necessary, an oxidizing agent such as hydrogen peroxide, a diluent such as ethylene glycol, and the like are further contained. Things can be mentioned. The material is selected in consideration of the material of the solid layer and the film forming conditions, but it is particularly preferable to contain at least hydrochloric acid, concentrated sulfuric acid, hydrofluoric acid and the like. For example when removing SrF _2, the hydrochloric acid is preferable. Further, in order to remove the CaF ₂ is concentrated sulfuric acid, hydrochloric acid is desirable, in particular concentrated sulfuric acid is preferable. Further, it can be removed by alkali, and in any etching, light irradiation, heating, or the like may be used in combination as appropriate for promoting the reaction or improving the selectivity.

  In addition, since the solid layer tends to decrease the wet etching rate after being used as a mask layer during dry etching of the semiconductor layer, that is, the solubility to the etchant, the process is considered in consideration of this point. It is preferable to determine the overall conditions.

Although the etching mask layer that has become unnecessary is removed as described above, it is also possible to use the etching mask layer as a mask for selective growth and further form a semiconductor layer without removing the etching mask layer. is there. In particular, when epitaxial growth is performed, a metal fluoride material such as SrF ₂ can be used as a selective growth mask.

[Description of different embodiments]
One particular embodiment of the invention will be described. In this embodiment, as shown in FIG. 9, the etching method of the present invention is such that the semiconductor layer 2 on the substrate 1 already has a step, and the electrodes 7 and 8 formed of metal layers are formed on the semiconductor layer. It is an example applied to the structure formed.

For example, when a semiconductor layer in which a metal layer such as an electrode or wiring is formed by aluminum or the like is etched by the etching method of the present invention, when the solid layer is removed after the etching is completed, an etchant containing an acid or alkali is used. Metal layers such as electrodes and wiring may be attacked and removed. In such a case, it is preferable that the etching mask layer has a multi-layer structure including a solid layer and a second mask layer made of a substance other than the substance constituting the solid layer. Here, as described above, it is preferable that the second mask layer is a layer composed of a substance other than the substance constituting the solid layer and is a substance resistant to the etchant for etching the solid layer. The second mask layer needs to be removed under conditions that do not attack the metal layer. Examples of the second mask layer include oxides such as SiO _x , AlO _x , TiO _x , TaO _x , HfO _x, and ZrO _x , nitrides such as SiN _x , AlN _x , and combinations thereof. These are very preferable because they have wet etching resistance and can be removed at the same time by a dry etching method that does not etch metal or the like. Particularly preferred are SiN _x and SiO _x because production is relatively easy, and SiN _x is particularly preferred.

  For example, the case where the solid layer is a layer made of a metal fluoride will be described below.

In FIG. 10, an etching mask layer 9 having a multilayer structure of a non-metal fluoride layer such as SiN _x and a metal fluoride layer is formed on the semiconductor layer 2 having the metal layers (electrodes 7 and 8) from the semiconductor layer side. State.

  Usually, the polymer solution treatment is performed in this state. The processing conditions and the like can be carried out according to the case where the etching mask layer is a single layer of a metal fluoride layer. Since side etching is suppressed by treating the metal fluoride layer with the polymer solution, the pattern accuracy is improved when the opening 10 shown in FIG. 11 is formed. When the semiconductor layer 2 is dry-etched, the surface metal fluoride layer functions as a mask as shown in FIGS.

Thereafter, in order to remove the etching mask layer 9, the metal fluoride layer is first removed with acid or alkali. At this time, the second mask layer that is not a metal fluoride such as SiN _x is used as an electrode 7 made of aluminum or the like. , 8 are protected. Next, the non-metal fluoride layer such as SiN _{x is} removed by dry etching without eroding the metal layer, and the structure of FIG. 13 can be obtained.

  Note that only a part of the etching mask layer, for example, the upper part of the metal layer (for example, the electrodes 7 and 8) may be formed as a multilayer structure, and the upper part of the part other than the metal layer may be formed as a single layer. Furthermore, the multi-layered etching mask layer can be used in any scene during the manufacture of a semiconductor device, but it is desirable to use it in consideration of the consistency of the entire process.

  Therefore, in consideration of process consistency, an example in which etching is performed using an etching mask partially having a multilayer structure will be described. First, FIG. 14 is a view showing a state in which the recess 25 is formed by forming the second etching mask 21 formed of a mask material other than the metal fluoride and etching the semiconductor layer 2 formed on the substrate 1. It is. The second etching mask 21 is formed of SiNx, for example, and masks a region including the metal layer (electrode 7). A region not covered with the second etching mask 21 is etched to form a recess 25. Even if the semiconductor layer 2 is a material that is difficult to be etched such as GaN, if the depth of the recess 25 is shallow, it can be etched sufficiently with a known mask material such as SiNx.

  Next, when performing deep etching using the metal fluoride layer as a mask, the metal fluoride mask 22 is formed as shown in FIG. 15 without removing the second etching mask 21. Therefore, the surface of the semiconductor layer on and near the metal layer (electrode 7) has a two-layer structure of a metal fluoride mask and a second etching mask. The metal fluoride mask 22 is treated with a polymer solution before being patterned by etching, and then patterned with an etching mask patterned according to a normal photoresist process.

Next, as shown in FIG. 16A, using the metal fluoride mask 22 as a mask, the semiconductor layer 2 is deeply etched to form a groove 26. As described above, since the metal fluoride layer has high dry etching resistance, deep etching is possible. At this time, as shown in FIG. 16B, the etching may be performed including the substrate 1, which is also one of preferable modes (the same applies to other embodiments and examples). Next, when the metal fluoride mask 22 is removed by, for example, acid, the second etching mask 21 remains as shown in FIG. For this reason, the metal layer is not eroded when the metal fluoride mask 22 is removed by wet etching. Finally, the second etching mask 21 is removed by a method in which neither the metal layer (electrode 7) nor the semiconductor layer is damaged, and a shallow recess 25 and a deep groove 26 are formed in the semiconductor layer 2 as shown in FIG. The resulting structure is obtained. Such a method can be selected depending on the material of the semiconductor layer, the material of the metal layer, and the like. For example, when the surface of the metal layer is Al or the like, and the semiconductor layer is a GaN layer or the like, When the etching mask is SiN _x or the like, dry etching such as reactive ion etching using a fluorine-based gas as a reactive gas is preferably performed. As described above, when the semiconductor device manufacturing process includes the first etching process for etching the semiconductor layer shallowly and the second etching process for etching the semiconductor layer deeply, other than metal fluoride as a mask in the first etching process. The second mask is used to form a metal fluoride layer mask layer on the second etching step without removing the mask after the etching, and partially or entirely to have a multilayer structure. The manufacturing method can be simplified while effectively protecting the metal layer.

  Furthermore, in the present invention, the formation of the metal fluoride layer is performed by a vacuum evaporation method, particularly by a method of heating without directly applying charged particles such as electrons and plasma, such as a resistance heating method, to the material. Although it is preferable to suppress the divergence, it is also preferable to apply a multilayer structure similar to the above as the etching mask layer in order to further improve the step coverage, particularly the side wall coverage.

For example, an oxide layer and a nitride layer formed by plasma CVD are excellent in the coverage of the side wall of the stepped substrate. Such layers include oxides such as SiO _x , AlO _x , TiO _x , TaO _x , HfO _x and ZrO _x , nitrides such as SiN _x , AlN _x and combinations thereof. Particularly preferred are SiN _x and SiO _X because production is relatively easy, and SiN _x is particularly preferred.

  Thus, it is preferable that the etching mask layer has a multilayer structure of a metal fluoride layer and a layer other than the metal fluoride layer in terms of both protection of the metal layer and step coverage. In particular, the manufacturing process can be simplified while protecting the metal layer by adopting a partial multiple mask in consideration of process consistency.

  The etching method of the present invention described above can be applied to the manufacture of various semiconductor devices and can be used in the etching process of the semiconductor manufacturing process.

  Further, as described above, the etching mask of the present invention is very suitable for the etching method and the semiconductor manufacturing process.

  The features of the present invention will be described more specifically with reference to experimental examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following experiments and examples and reference examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In addition, in the drawings referred to in the following examples and reference examples, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text. .

<< Reference Experiment 1 >>
SrF ₂ layers were vacuum-deposited by resistance heating at different substrate temperatures on the Si-doped GaN semiconductor layer grown on the sapphire substrate by MOCVD. The formed SrF ₂ layer was examined in detail for patterning characteristics as an etching mask for dry etching of the GaN layer, resistance during dry etching, wet etching characteristics during the subsequent removal process, and the like.

For the patterning of the SrF ₂ layer after film formation, wet etching was performed at room temperature using an etchant in which hydrochloric acid (containing 36% hydrogen chloride) and water were mixed at a volume ratio of 1:10 using a resist as a mask. The etching rate, the linearity of the side wall of the formed SrF _two- layer pattern, and the controllability of the absolute value of the opening width were evaluated. The pattern used here is striped, and the pattern transferability from the resist planar shape to the SrF ₂ planar shape is evaluated by the linearity of the side wall. Further, dry etching of the Si-doped GaN layer using the SrF ₂ mask patterned as described above was performed using Cl ₂ plasma, and the suitability of the SrF ₂ mask during dry etching was evaluated. Further, etching at room temperature during removal of the Si-doped GaN semiconductor layer from the etchant of hydrochloric acid (containing 36% hydrogen chloride) and water (1:10 by volume) of the SrF ₂ layer that has undergone the history of dry etching by chlorine plasma. The rate was also measured.

In addition, when forming SrF ₂ , a sample in which a Ti / Al / Au metal and a SiN _x layer are further formed on the Si-doped GaN semiconductor layer is set in the same chamber, and the heat history during the formation of the SrF ₂ mask is set. The resistance of the metal electrode part and the change of the surface state were also confirmed. The confirmation of the surface state of the metal was observed after the SrF ₂ layer was removed and the SiN _x layer was also removed after the SrF ₂ layer was formed.

  Table 1 shows the etching rate measurement and evaluation results.

From Table 1, it is clear that the SrF ₂ layer formed at a substrate temperature of 150 ° C. or higher is suitable as an etching mask used for dry etching. In addition, considering that the SrF ₂ layer is removed at a practical rate after dry etching and the case where a metal layer is present in the lower layer, an SrF ₂ layer formed at a substrate temperature of 480 ° C. or lower is preferable. I understand.

<< Experiment 1 >>
<Example 1>
In the same manner as in Reference Experiment 1, a 400 nm thick SrF ₂ layer was formed on a Si-doped GaN semiconductor layer grown by MOCVD on a sapphire substrate by vacuum deposition using a resistance heating method at a substrate temperature of 450 ° C. The surface state of the SrF ₂ layer at this time was observed with a scanning electron microscope (SEM). The result is shown in FIG. As can be seen in FIG. 21, voids between fine particles were observed in the SrF ₂ layer, which is a solid layer, and the surface porosity was about 2.7%. Next, the substrate on which the SrF ₂ layer other than the part where the SEM was observed was placed on a spin coater, and a cresol novolak resin solution (manufactured by Gunei Chemical Industry Co., Ltd., trade name: Resitop) was placed on the formed SrF ₂ layer. PSF-2808, propylene glycol monomethyl ether 70 wt% and propylene glycol monomethyl ether acetate 30 wt% mixed solvent, viscosity 100 cps) was added dropwise and spin coated. Thereafter, the mixture was heated at 85 ° C. for 15 minutes and then at 120 ° C. for 15 minutes. After cooling, acetone washing, isopropanol washing and water washing were sequentially performed for 3 minutes each to remove the polymer.

After drying at room temperature, for patterning of the SrF ₂ layer, a positive photoresist composition (MCPR2200X, manufactured by Rohm and Haas) is spin-coated on the SrF ₂ layer, pre-baked, and a photomask having a predetermined pattern Exposed through. After post-exposure baking, after development / cleaning, post-baking was performed to complete the patterning of the photoresist. Next, the same etchant as in Reference Experiment 1 was used, and the SrF ₂ layer was wet etched at room temperature for 3 minutes.

After wet etching, the side etch amount L was observed by optical microscope observation. As shown in the microscopic image in FIG. 19, the boundary X2 of the SrF ₂ layer 3 slightly receded from the boundary X1 of the photoresist film 4, and the side etch amount L was 1.7 μm.

<Reference Example 1>
In Example 1, Example 1 was repeated except that the polymer solution treatment was not performed. As shown in the microscopic image in FIG. 20, the boundary X2 of the SrF ₂ layer 3 recedes from the boundary X1 of the photoresist film 4, and the side etch amount L was 7.1 μm.

<Example 2>
The polymer solution treatment shown in Table 2 was performed. The results of Example 1 and Reference Example 1 are also shown.

<< Experiment 2 >>
<Reference Example 2, Example 3>
In this experiment, an experiment was performed in accordance with Experiment 1 except that the substrate temperature during the deposition of the SrF ₂ layer was changed to 350 ° C. in Experiment 1. The treatment was performed using the polymer solution shown in Table 3. Reference Example 2 is an example in which the polymer solution treatment is not performed. Table 3 shows the results.

<Reference Example 3>
A reference example in which an element isolation groove is formed by etching in a semiconductor layer constituting a semiconductor light emitting device will be described with reference to FIGS. In this reference example, the present invention can be applied by treating the polymer solution after forming the SrF ₂ layer and washing it if necessary.

A c + plane sapphire substrate 1 having a thickness of 430 μm was prepared, and a semiconductor layer 2 was formed thereon as follows. First, an MOCVD method was used to form an undoped GaN layer grown at a low temperature of 10 nm as a first buffer layer, and then an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C. as a second buffer layer. Further, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm as the first conductivity type (n-type) second cladding layer, and Si as the first conductivity type (n-type) contact layer. A doped (Si concentration 1 × 10 ¹⁹ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si doped (Si concentration 5.0 × 10 ¹⁸ cm) as a first conductivity type (n-type) first cladding layer. ^-3 ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Further, as an active layer structure, an undoped GaN layer formed as a barrier layer with a thickness of 13 nm at 850 ° C. and an undoped In _0.1 Ga _0.9 N formed as a quantum well layer with a thickness of 2 nm at 720 ° C. The layers were alternately formed so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and a Mg-doped (Mg concentration 1 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is formed to a thickness of 0.1 μm as the second conductivity type (p-type) first cladding layer. Formed to a thickness. Further, an Mg-doped (Mg concentration: 1 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as a second conductivity type (p-type) second cladding layer. Finally, an Mg-doped (Mg concentration 1 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as a second conductivity type (p-type) contact layer.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, epitaxial growth was completed, and the structure up to the formation of the semiconductor layer in FIG. 1 was produced.

Next, as shown in FIG. 2, a single layer of SrF ₂ was formed as an etching mask layer 3 at 450 ° C. at a deposition rate of 0.2 nm / sec by vacuum deposition at 450 nm. Next, as shown in FIG. 3, a resist mask layer 4 was formed by spin coating, and then a striped resist pattern was formed by photolithography. Next, in order to pattern the etching mask layer 3 (SrF ₂ single layer) using the resist pattern 4, hydrochloric acid (containing 36% hydrogen chloride) and water are immersed in an etchant having a volume ratio of 1:10 for 240 seconds to form an SrF ₂ layer. Was etched as shown in FIG. 5A. The etched SrF ₂ layer reflected the photomask pattern, was excellent in linearity, did not cause unintended peeling, and maintained high adhesion. Next, the resist layer was removed by acetone and oxygen plasma ashing as shown in FIG. 6, and the etching mask for the SrF ₂ layer was exposed on the surface. Next, all the semiconductor epitaxial layers corresponding to the trenches for separating the elements were etched using inductively coupled chlorine plasma as shown in FIG. During the dry etching process, the SrF ₂ layer was hardly etched despite the dry etching of a GaN-based material having a thickness of more than 5.8 μm (average 5.868 μm). Finally, as shown in FIG. 8, it is immersed in an etchant having a volume ratio of hydrochloric acid and water of 1:10 for 300 seconds to completely remove the unnecessary SrF ₂ layer, and to form a groove for separation between elements of the semiconductor light emitting device. Completed formation. The width of the manufactured groove for element separation was 100 μm.

<Reference Example 4>
Different reference examples will be described with reference to FIGS. 1 and 9 to 12. Also in this reference example, the present invention can be applied by treating the polymer solution after forming the SrF ₂ layer and washing it if necessary.

A c + plane sapphire substrate 1 having a thickness of 430 μm was prepared, and a semiconductor layer 2 was formed thereon as follows. First, undoped GaN having a low-temperature growth having a thickness of 20 nm was formed as the first buffer layer by MOCVD, and then undoped GaN having a thickness of 1 μm was formed at 1040 ° C. as the second buffer layer 2. Subsequently, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer of 5 μm is formed as the first conductivity type (n-type) second cladding layer, and Si as the first conductivity type (n-type) contact layer. A doped (Si concentration 1 × 10 ¹⁹ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si doped (Si concentration 1.0 × 10 10) as a first conductivity type (n-type) first cladding layer. ^{A 19} cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Further, as the active layer structure, an undoped GaN layer formed at 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.06 Ga _0.94 N layer formed at 3 nm at 715 ° C. as a quantum well layer, Were formed alternately so that there were 6 layers in total and both sides would be barrier layers. Further, the growth temperature is set to 1025 ° C., and a Mg-doped (Mg concentration 1 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is formed to a thickness of 0.1 μm as the second conductivity type (p-type) first cladding layer. Formed to a thickness. Further, an Mg-doped (Mg concentration: 1 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as a second conductivity type (p-type) second cladding layer. Finally, an Mg-doped (Mg concentration 1 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as a second conductivity type (p-type) contact layer.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the epitaxial growth was completed (structure of FIG. 1).

In order to perform the first etching process for exposing the first conductivity type (n-type) contact layer, the etching mask was formed on the semiconductor laminated structure after the epitaxial growth. Here, an SrF ₂ layer was formed over the entire surface of the semiconductor layer using a vacuum deposition method at a substrate temperature of 200 ° C. and a deposition rate of 0.5 nm / sec. Then by a photolithographic Gufi step, a photoresist pattern is formed SrF ₂ layer on and patterned to partially etch the SrF ₂ layer with hydrochloric acid, to prepare a mask for the first etching. Then, as a first etching step, a p-GaN contact layer, a p-GaN second cladding layer, a p-AlGaN first cladding layer, an active layer structure comprising an InGaN quantum well layer and a GaN barrier layer, and an n-AlGaN first cladding layer Etching by inductively coupled plasma using BCl ₃ gas was performed partway through the n-GaN contact layer to expose the n-type contact layer serving as an n-type carrier injection portion.

After the plasma etching by inductively coupled plasma was completed, the SrF ₂ mask layer was completely removed with hydrochloric acid. Here, the SrF ₂ mask formed at a substrate temperature of 200 ° C. is formed with a mask having excellent linearity reflecting the photomask pattern at the time of patterning, and is hardly etched even by plasma etching. Etching resistance to plasma was also good.

  Next, in order to pattern the p-side electrode 7 by the lift-off method on the formed step, a resist pattern was formed by a photolithography method. As the metal layer A for forming the p-side electrode 7, Pd 20 nm and Au 1000 nm were laminated by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, the p-side electrode was completed by heat treatment (formation of the p-side electrode 7 in FIG. 9). Thus, since the p-side electrode 7 was formed without being exposed to a plasma process or the like, the p-side current injection region was not damaged.

  Then, in order to further pattern the n-side electrode 8 by a lift-off method, a resist pattern was formed by a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as a metal layer for forming the n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode 8 (formation of the n-side electrode 8 in FIG. 9).

  The structure up to FIG. 9 was formed by the steps up to here.

Subsequently, in order to form the etching mask layer 9 with the multilayer film of the SiN _x film and the SrF ₂ film, first, the SiN _x film was formed to a thickness of 200 nm by using the p-CVD method at the film forming temperature of 400 ° C. . Then, at a high temperature of 400 ° C., to form the SrF ₂ layer mask to a thickness of 400 nm. At this time, the SrF ₂ mask was formed while revolving the dome on which the sample was mounted at a deposition rate of 0.5 nm / sec, and the shape of FIG. 10 was obtained.

Further, in order to separate the light emitting elements, a photoresist pattern having an opening in the separation groove forming portion is formed by using a photolithography method, and an etching mask having a laminated structure of SrF ₂ and SiN _x is formed using this resist mask. Layer 9 was wet etched to form openings 10. Etching of the SrF ₂ layer was carried out selectively using an etchant mixed at a volume ratio of hydrochloric acid (containing 36% hydrogen chloride): water = 1: 10 for 240 seconds, followed by etching of the SiN _x layer, Etching was selectively performed for 3 minutes using an etchant having a volume ratio of 1: 5 for hydrofluoric acid and ammonium fluoride. At this time, a patterned etching mask layer excellent in linearity and adhesiveness reflecting the photomask pattern in both the SrF ₂ part and the SiN _x part was obtained (FIG. 11).

Next, in the structure of FIG. 11, the semiconductor layer 2 was dry etched by inductive coupling plasma excitation using Cl ₂ gas from the opening 10 of the etching mask layer 9 to form the separation groove 11. During the etching, the multilayer mask used as an etching mask was hardly etched (FIG. 12).

Finally, all SrF ₂ parts were removed by soaking in hydrochloric acid for 5 minutes. At this time, the SiN _x mask portion was not etched at all. Therefore, the electrode layer was not attacked by hydrochloric acid. Then, in order to remove the unnecessary SiN _x mask, reactive etching using SF ₆ gas was performed for 1 minute, and the SiN _x mask was removed to obtain the shape of FIG.

  Next, the elements were cut out along the separation grooves between the formed elements, and the light emitting device was completed.

It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is a figure explaining side etching. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining the etching method of one Embodiment. It is process sectional drawing explaining one Embodiment which applied the etching method of this invention to the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining one Embodiment which applied the etching method of this invention to the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining one Embodiment which applied the etching method of this invention to the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining one Embodiment which applied the etching method of this invention to the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining one Embodiment which applied the etching method of this invention to the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is process sectional drawing explaining 1 simplified embodiment of the etching of the semiconductor layer in which the metal layer is formed in the surface. It is the microscope image of Example 1, and its cross-sectional schematic diagram. It is the microscope image of the reference example 1, and its cross-sectional schematic diagram. It is a SEM photograph image of SrF ₂ layer surface. It is a SEM photograph image of CaF ₂ layer surface.

Explanation of symbols

1 Substrate 2 Semiconductor layer 3 Etching mask layer (solid layer)
4 resist mask layer 7 electrode 8 electrode 9 etching mask layer (solid layer)
10 Opening 11 Groove 21 Second etching mask (SiNx, etc.)
22 Metal fluoride mask 25 Recess 26 Groove

Claims (17)

Forming a solid layer made of metal fluoride on at least a part of the etching mask on the surface of the substrate;
Treating the solid layer with a polymer solution;
And etching the substrate using the solid layer treated with the polymer solution as a mask. The polymer solution treatment step includes
2. The etching method according to claim 1, further comprising: a sub-step: an application step of applying a polymer solution to the solid layer; and a sub-step: a step of removing the polymer on the solid layer.   The etching method according to claim 2, wherein the step of removing the polymer includes solvent washing. After the polymer solution treatment step,
Forming a patterned resist mask on the solid layer;
Etching the solid layer using the resist mask as an etching mask;
The etching method according to claim 1, comprising:   The etching method according to claim 4, wherein the resist mask is formed of a photoresist.   6. The etching method according to claim 4, wherein the step of etching the solid layer is performed by wet etching.   The etching method according to claim 6, wherein the etchant used for the wet etching contains at least one selected from the group consisting of hydrochloric acid, hydrofluoric acid and concentrated sulfuric acid.   The etching method according to claim 1, wherein the solid layer is formed at a temperature of 150 ° C. to 480 ° C. The etching method according to claim 1, wherein the solid layer is selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof.   The etching method according to claim 1, wherein the step of etching the substrate is performed by dry etching.   The etching method according to claim 10, wherein the dry etching is plasma-excited dry etching using a gas species containing at least chlorine atoms.   The etching method according to claim 1, further comprising a step of removing the solid layer with an etchant containing an acid or an alkali after the step of etching the substrate.   The etching mask formed on the substrate has a multilayer structure portion of the solid layer and a second mask layer other than a substance constituting the solid layer. The etching method as described in 4. above.   The etching method according to claim 1, wherein the substrate includes a group III-V nitride layer.   The etching method according to claim 4, wherein a side etch amount measured from an end of the patterned resist mask generated when the solid layer is etched is 6 μm or less. Forming a solid layer having voids between fine particles as at least part of an etching mask on the surface of the substrate;
Treating the solid layer with a polymer solution;
And etching the substrate using the solid layer treated with the polymer solution as a mask.   The manufacturing method of the optical / electronic device which has the etching method in any one of Claims 1-16 as 1 process.