CN113782603B

CN113782603B - Semiconductor structure and forming method thereof

Info

Publication number: CN113782603B
Application number: CN202010525512.5A
Authority: CN
Inventors: 周飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2023-08-01
Anticipated expiration: 2040-06-10
Also published as: CN113782603A

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a gate structure on the substrate of the device region; the source region is positioned in the substrate of the device region at one side of the grid structure; the drain region is positioned in the substrate of the device region at the other side of the grid structure; the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source region and the drain region; the top dielectric layer is positioned on the bottom dielectric layer and covers the gate structure; the heat dissipation structure is positioned in the top dielectric layer of the isolation region; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more heat conducting layers connected with each other. When the device works, heat generated by the device can be conducted out through the heat dissipation structure, so that the heat dissipation efficiency of the device is improved, the self-heating effect of the device is correspondingly improved, and further the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.

Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, improves the self-heating effect of a device and is further beneficial to improving the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising discrete device regions and isolation regions between the device regions; the grid structure is positioned on the substrate of the device region; the source region is positioned in the substrate of the device region at one side of the grid structure; the drain region is positioned in the substrate of the device region at the other side of the grid structure; the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source region and the drain region; a top dielectric layer overlying the bottom dielectric layer and covering the gate structure; the heat dissipation structure is positioned in the top dielectric layer of the isolation region; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more layers of connected heat conduction layers.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of discrete device regions and isolation regions positioned between the device regions, a grid structure is formed on the substrate of the device regions, an active region is formed in the substrate of the device regions on one side of the grid structure, a drain region is formed in the substrate of the device regions on the other side of the grid structure, and a bottom dielectric layer covering the source region and the drain region is formed on the substrate on the side of the grid structure; forming a top dielectric layer covering the gate structure and a heat dissipation structure in the top dielectric layer of the isolation region on the bottom dielectric layer; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more layers of connected heat conduction layers.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure of the embodiment of the invention, a heat dissipation structure positioned in the top dielectric layer of the isolation region is also arranged; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more heat conduction layers connected with each other; through setting up heat radiation structure, at the device during operation, the heat that the device produced can be through heat radiation structure conduction goes out to be favorable to improving the radiating efficiency of device, correspondingly improve Self-Heating Effect (SHE) of device, and then be favorable to promoting the performance of semiconductor structure.

Drawings

Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background, the current semiconductor process gradually starts to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In a FinFET, the gate structure may control the ultra-thin body (fin) from at least two sides.

However, the fin portion of the FinFET device has a smaller width, and heat generated during operation of the device is difficult to dissipate through the fin portion, which easily results in poor heat dissipation performance of the device, and thus poor performance of the device.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising discrete device regions and isolation regions between the device regions; the grid structure is positioned on the substrate of the device region; the source region is positioned in the substrate of the device region at one side of the grid structure; the drain region is positioned in the substrate of the device region at the other side of the grid structure; the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source region and the drain region; a top dielectric layer overlying the bottom dielectric layer and covering the gate structure; the heat dissipation structure is positioned in the top dielectric layer of the isolation region; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more layers of connected heat conduction layers.

In the semiconductor structure of the embodiment of the invention, a heat dissipation structure positioned in the top dielectric layer of the isolation region is also formed; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more heat conduction layers connected with each other; through setting up heat radiation structure, at the device during operation, the heat that the device produced can be through heat radiation structure conduction goes out to be favorable to improving the radiating efficiency of device, correspondingly improve Self-Heating Effect (SHE) of device, and then be favorable to promoting the performance of semiconductor structure.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 9 and 10 in combination, a schematic structural diagram of one embodiment of a semiconductor structure of the present invention is shown. Wherein fig. 9 is a top view, and fig. 10 is a cross-sectional view of fig. 9 at a position B-B1.

The semiconductor structure includes: a substrate comprising discrete device regions I and isolation regions II located between the device regions I; a gate structure 120 (shown in fig. 6) on the substrate of the device region I; a source region 130 (shown in fig. 6) located in the substrate of the device region I on one side of the gate structure 120; drain region 140 (shown in fig. 6) located in the substrate of device region I on the other side of the gate structure 120; a bottom dielectric layer 150 (shown in fig. 6) on the substrate on the sides of the gate structure 120 and covering the source region 130 and the drain region 140; a top dielectric layer 185 on the bottom dielectric layer 150 and covering the gate structure 120; a heat dissipation structure 180 located in a top dielectric layer 185 of the isolation region II; the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, or on a side of the drain region 140 facing away from the gate structure 120, or on a side of the source region 130 facing away from the gate structure 120 and a side of the drain region 140 facing away from the gate structure 120; the heat dissipating structure 180 includes one or more thermally conductive layers 80 that are coupled.

In the semiconductor structure provided by the embodiment of the invention, a heat dissipation structure 180 is further arranged in the top dielectric layer 185 of the isolation region II; the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, or on a side of the drain region 140 facing away from the gate structure 120, or on a side of the source region 130 facing away from the gate structure 120, and on a side of the drain region 140 facing away from the gate structure 120; the heat dissipation structure 180 includes one or more thermally conductive layers 80 connected; by arranging the heat dissipation structure 80, heat generated by the device can be conducted out through the heat dissipation structure 180 when the device works, so that the heat dissipation efficiency of the device is improved, and the Self-Heating Effect (SHE) of the device is correspondingly improved, so that the performance of the semiconductor structure is improved.

The substrate is used for providing a platform for a process. In this embodiment, the substrate is a three-dimensional substrate. Specifically, in this embodiment, a base is used to form a fin field effect transistor (FinFET), and the base includes a substrate 100 and a fin 110 that is separated from the device region I substrate 100. In other embodiments, the substrate can also be a planar substrate.

In particular, in this embodiment, the base includes the substrate 100 (as shown in fig. 6) and the fin portion 110 (as shown in fig. 6) located on the substrate 100, where the width of the fin portion 110 is generally smaller, and by forming the heat dissipation structure 180, the heat dissipation capability of the FinFET device is advantageously improved, so that the self-heating effect of the device can be significantly improved.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

The fin 110 is used to provide a conductive channel during device operation.

In this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may be different from the material of the substrate.

In this embodiment, the semiconductor structure further includes: isolation structures 111 (shown in fig. 6) are located on the substrate 100 and cover portions of the sidewalls of the fins 110. The isolation structure 111 is used to isolate the adjacent fin 110, and the isolation structure 111 is also used to isolate the substrate 100 from the gate structure 120.

The material of the isolation structure 111 is an insulating material, and the heat conduction capability of the insulating material is lower than that of silicon, that is, the heat conduction capability of the isolation structure 111 is lower than that of the substrate 100 and the fin portion 110, the width and the volume of the fin portion 110 are smaller, the volume of the isolation structure 111 is larger, and the heat generated by the device is difficult to be dissipated through the isolation structure 111. Therefore, by disposing the heat dissipation structure 180 in the semiconductor structure, heat generated by the device can be conducted away, which is beneficial to significantly improving the heat dissipation capability of the FinFET device, and further improving the heat dissipation effect of the device.

In this embodiment, the material of the isolation structure 111 is an insulating material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The gate structure 120 is used to control the turn-on or turn-off of the conduction channel during device operation.

The gate structure 120 is located on the isolation structure 111, the gate structure 120 spans across the plurality of fins 110 and covers part of the top and part of the sidewalls of the fins 110.

In this embodiment, the gate structure 120 is a metal gate structure. The gate structure 120 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

The high-k gate dielectric layer is used to electrically isolate fin 110 from gate structure 120. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide, for example: hfO (HfO) ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ Etc.

When the NMOS transistor is formed, the work function layer is made of N-type work function materials, including one or more of TiAl, taAlN, tiAlN, moN, taCN and AlN; when forming a PMOS transistor, the material of the work function layer is a P-type work function material, including one or more of Ta, tiN, taN, taSiN and TiSiN.

The gate electrode layer serves as an electrode to electrically connect the gate structure 120 to other interconnect structures or external circuitry. The material of the gate electrode layer is a conductive material, for example: w, al, cu, ag, au, pt, ni or Ti, etc.

The source region 130 and the drain region 140 serve to provide stress to the channel, thereby improving mobility of carriers.

In this embodiment, the source region 130 is located in the fin 110 on one side of the gate structure 120, and the drain region 140 is located in the fin 110 on the other side of the gate structure 120.

When forming an NMOS transistor, the source region 130 or the drain region 140 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to be beneficial to improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming a PMOS transistor, the source region 130 or the drain region 140 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.

The bottom dielectric layer 150 is used to isolate adjacent devices, and the bottom dielectric layer 150 is also used to electrically isolate the gate structure 120 from subsequent source and drain contact layers.

The bottom dielectric layer 150 is an inter-level dielectric layer (ILD). The material of the bottom dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the bottom dielectric layer 150 has a single-layer structure, and the material of the bottom dielectric layer 150 is silicon oxide.

In this embodiment, the semiconductor structure further includes: a source contact layer 135 (shown in fig. 6) extending through the bottom dielectric layer 150 above the source region 130 and contacting the source region 130; a drain contact layer 145 (shown in FIG. 6) extending through the bottom dielectric layer 150 over the drain region 140 and contacting the drain region 140

Source contact layer 135 is used to make electrical connection between source 130 and external circuitry or other interconnect structures. The drain contact layer 145 is used to make electrical connection between the drain region 140 and an external circuit or other interconnect structure. The material of the source contact layer 135 and the drain contact layer 145 is a conductive material. The materials of the source and drain contact layers 135 and 145 include one or more of cobalt, tungsten, copper, nickel, and aluminum.

In this embodiment, the source contact layer 135 and the drain contact layer 145 are made of the same material.

In this embodiment, the semiconductor structure further includes: a third dielectric layer 155 is located between the top dielectric layer 185 and the bottom dielectric layer 150. Accordingly, the source contact layer 135 extends through the bottom dielectric layer 150 and the third dielectric layer 155 above the source region 130, and the drain contact layer 145 extends through the bottom dielectric layer 150 and the third dielectric layer 155 above the drain region 140.

The third dielectric layer 155 is used to electrically isolate the source contact layer 135 from the drain contact layer 145.

In this embodiment, the third dielectric layer 155 is an inter-metal dielectric (Inter metal dielectric, IMD) layer. In this embodiment, the material of the third dielectric layer 155 is silicon oxide.

In this embodiment, the semiconductor structure further includes: a gate contact layer 125 (shown in fig. 5) extends through the third dielectric layer 155 over the gate structure 120 and contacts the top of the gate structure 120.

The gate contact layer 125 is used to make electrical connection between the gate structure 120 and an external circuit or other interconnect structure. The material of the gate contact layer 125 is the same as that of the source contact layer 135 and the drain contact layer 145, and will not be described again here.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 160 located between the top dielectric layer 185 and the bottom dielectric layer 150; source interconnect 136 in second dielectric layer 160 of device region I and in contact with the top surface of source contact layer 135; a drain interconnect structure 146 is located in the second dielectric layer 160 of the device region II and is in contact with the top surface of the drain contact layer 145.

The second dielectric layer 160 is used to make electrical connection between the source interconnect structure 136 and the drain interconnect structure 146. Specifically, second dielectric layer 160 is located between third dielectric layer 155 and top dielectric layer 185.

In this embodiment, the second dielectric layer 160 is an inter-metal dielectric layer (IMD). For the description of the second dielectric layer 160, reference may be made to the foregoing description of the third dielectric layer 155, which is not repeated herein.

The source interconnect 136 is electrically connected to the source region 130 through the source contact layer 135, thereby electrically connecting the source region 130 to an external circuit or other interconnect structure.

The drain interconnect 146 is electrically connected to the drain region 140 through the drain contact layer 145, thereby electrically connecting the drain region 140 to an external circuit or other interconnect.

In this embodiment, the source interconnect structure 136 and the drain interconnect structure 146 each include an interconnect line 162 on the conductive plug 161 and on the conductive plug 161.

In this embodiment, the semiconductor structure further includes: a gate interconnect structure 126 (shown in fig. 5) extends through the second dielectric layer 160 over the gate contact layer 125.

The gate interconnect structure 126 is electrically connected to the gate structure 120 through the gate contact layer 125, thereby enabling electrical connection between the gate structure 125 and an external circuit or other interconnect structure.

The gate interconnect structure 126 is the same as the source interconnect structure 136 or the drain interconnect structure 146 in material and structure, and will not be described again here.

When the device works, heat generated by the device can be conducted out through the heat dissipation structure 180, so that the heat dissipation efficiency of the device is improved, and the Self-Heating Effect (SHE) of the device is correspondingly improved, so that the performance of the semiconductor structure is improved. In particular, in this embodiment, the base includes the substrate 100 and the fin portion 110 located on the substrate 100, where the width of the fin portion 110 is smaller, and by providing the heat dissipation structure 180, it is beneficial to significantly improve the heat dissipation capability of the FinFET device and improve the self-heating effect of the device.

For this reason, the thermal conductivity of the material of the heat conducting layer 80 is not too low, which is advantageous for improving the heat dissipation capability of the heat dissipation structure 180, and thus for improving the self-heating effect of the heat dissipation structure 180 for improving the device. For this reason, in the present embodiment, the thermal conductivity of the material of the heat conductive layer 80 is at least 150W/mK. As one example, the thermal conductivity of the material of the thermally conductive layer 80 is 150W/mK to 1500W/mK.

In this embodiment, the material of the heat conducting layer 80 is a metal material. The metal material has higher heat conductivity, so that the heat dissipation structure 180 is favorable for ensuring higher heat conduction capacity, and the effect of the heat dissipation structure 180 for improving the self-heating effect of the device is further improved; in addition, the metal material is a conductive material, and the metal material is selected, so that the heat dissipation structure 180 can be formed in the process of forming the back-end interconnection structure, the heat dissipation structure 180 and the back-end interconnection structure are made of the same material, and the process for forming the heat dissipation structure 180 is compatible with the back-end interconnection process, and the process compatibility and the process integration degree are improved. Specifically, the metallic material includes one or more of cobalt, tungsten, copper, nickel, and aluminum.

When the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, the distance between the heat dissipation structure 180 and the source region 130 cannot be too small due to the limitation of Design Rule. However, the distance between the heat dissipating structure 180 and the source region 130 is not too large, which would easily reduce the efficiency of heat dissipation from the device to the heat dissipating structure 180, and thus, the effect of improving the self-heating effect of the heat dissipating structure 180 on the device is easily reduced, and the semiconductor structure occupies too large area, which is not beneficial to miniaturization of the device. For this reason, in the present embodiment, when the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120, the distance between the heat dissipation structure 180 and the source region 130 is 2nm to 8nm.

Also, when the heat dissipation structure 180 is located at a side of the drain region 140 facing away from the gate structure 120, a distance between the heat dissipation structure 180 and the drain region 140 is 2nm to 8nm.

As one example, the top dielectric layer 185 includes a first dielectric layer 85 that is a multi-layer stack; the heat dissipation structure 180 includes a plurality of heat conductive layers 80, the heat conductive layers 80 being located in a first dielectric layer 85; wherein, one of the heat conductive layers 80 closest to the substrate is a bottom heat conductive layer 80a, and each of the heat conductive layers 80 located above the bottom heat conductive layer 80a is a top heat conductive layer 80b.

By providing a plurality of heat conductive layers 80, the heat dissipation efficiency of the heat dissipation structure 180 is further improved.

In this embodiment, the number of layers of the first dielectric layer 85 and the heat conductive layer 80 is two as an example. In other embodiments, the number of first dielectric layers and thermally conductive layers may be other numbers.

Accordingly, in the present embodiment, the heat dissipation structure 180 further includes: a first plug structure 81 located in the first dielectric layer 85 under each top conductive layer 80b and connected to the top conductive layer 81 b; the first plug structure 81 is in contact with the top of one of the heat conductive layers 80 located therebelow.

The first plug structure 81 is used for connecting the lower heat conductive layer 80 and the upper heat conductive layer 80, so as to facilitate improving the heat dissipation efficiency of the heat dissipation structure 180.

The material of the first plug structure 81 is also a metal material, which is not only advantageous for improving the heat conduction capability of the first plug structure 81, but also for enabling the process of forming the first plug structure 81 to be compatible with the back-end interconnect process. The material of the first plug structure 81 includes one or more of cobalt, tungsten, nickel, copper, and aluminum. In this embodiment, the material of the first plug structure 81 is the same as that of the heat conductive layer 80,

Accordingly, the first dielectric layer 85 is used to electrically isolate the thermally conductive layer 80 from the back-end interconnect structure. In this embodiment, the first dielectric layer 85 is an inter-metal dielectric layer. For this purpose, the material of the first dielectric layer 85 is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the material of the first dielectric layer 85 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end interconnection structures, and further reduce back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.

In other embodiments, the top dielectric layer includes a first dielectric layer; the heat dissipation structure comprises a heat conduction layer, and the heat conduction layer is located in the first medium layer.

In this embodiment, the heat dissipation structure 180 includes a plurality of heat conductive layers 80 stacked in sequence, and one heat conductive layer 80 closest to the substrate is used as the bottom heat conductive layer 80a. In other embodiments, when the heat dissipating structure includes a layer of thermally conductive layer, the thermally conductive layer acts as a bottom thermally conductive layer.

As an example, the heat sink structure 180 is located only on a side of the source region 130 facing away from the gate structure 120. In other embodiments, the heat dissipation structure may also be located only on the side of the drain region facing away from the gate structure. In other embodiments, the heat spreading structure may also be located on a side of the drain region facing away from the gate structure and a side of the source region facing away from the gate structure.

In this embodiment, the semiconductor structure further includes: the source electrode connection layer 170 is located in the second dielectric layer 160 on the side, facing away from the gate structure 120, of the source electrode interconnection structure 136, the side wall of the source electrode connection layer 170 is in contact with the source electrode interconnection structure 135, and the source electrode connection layer 170 also extends into the second dielectric layer 160 below the bottom heat conduction layer 80 a; the heat dissipation structure 180 further includes: the second plug structure 82 is located in the first dielectric layer 85 between the source connection layer 170 and the bottom heat conduction layer 80a and connected to the bottom heat conduction layer 80a, and the bottom of the second plug structure 82 contacts the top surface of the source connection layer 170.

By providing the source connection layer 170, the heat dissipation structure 180 is connected between the source connection layer 170 and the source interconnection structure 170; compared with the heat emitted by the device is conducted to the heat dissipation structure through the dielectric material, in this embodiment, by forming the source connection layer 170, the material of the source connection layer 170 is the same as the material of the source interconnection structure 136, and the thermal conductivity of the material of the source connection layer 170 is greater than that of the dielectric material, so that the heat emitted by the device during operation is conducted to the heat dissipation structure 180 more quickly, and further the heat dissipation capability of the device can be improved through the heat dissipation structure 180.

Furthermore, when the device is in operation, the source region 130 is normally connected to zero potential, so that the heat dissipation structure 180 is connected to the source interconnection structure 136 through the source connection layer 170, which is beneficial to reduce the influence of the heat dissipation structure 180 on the electrical connection performance of the device.

The material of the source connection layer 170 is the same as that of the source interconnection 136 and the drain interconnection 146, and will not be described here again.

Through setting up the second plug structure 82 in heat radiation structure 180 to through second plug structure 82, make bottom heat conduction layer 80a link to each other with source electrode tie layer 170, correspondingly, make heat radiation structure 180 link to each other with source area contact layer 135, the heat that the device during operation produced can be conducted to heat radiation structure 180 through source electrode tie layer 170, is favorable to improving heat dissipation efficiency and the heat dissipation ability of heat radiation structure 180, and then is favorable to improving the effect that heat radiation structure 180 is used for improving the self-heating effect of device.

The material of the second plug structure 82 is a metal material, which is not only beneficial to improving the heat conduction capability of the second plug structure 82, but also beneficial to making the process of forming the second plug structure 82 compatible with the back-end interconnection process, thereby being beneficial to improving the process integration.

In this embodiment, the material of the second plug structure 82 is the same as the material of the source interconnect structure 136 or the drain interconnect structure 146, and includes one or more of cobalt, tungsten, copper, nickel, and aluminum.

In this embodiment, the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 110, and the source connection layer 170 for connecting the source region contact layer 135 and the heat dissipation structure 180 is taken as an example. In other embodiments, when the heat dissipation structure is located at a side of the source region opposite to the gate structure, the source connection layer may not be disposed on the contact layer between the heat dissipation structure and the source region, and accordingly, when the device works, heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then dissipated through the heat dissipation structure.

In other embodiments, when the heat dissipating structure is located on a side of the drain region facing away from the gate electrode, the semiconductor structure further includes: the drain electrode connecting layer is positioned in the second dielectric layer at one side of the drain electrode interconnection structure, which is opposite to the gate electrode structure, the side wall of the drain electrode connecting layer is contacted with the drain electrode interconnection structure, and the drain electrode connecting layer also extends into the second dielectric layer below the bottom heat conducting layer; the heat dissipation structure further includes: and the third plug structure is positioned in the first dielectric layer between the drain electrode connecting layer and the bottom heat conducting layer and is connected with the bottom heat conducting layer, and the bottom of the third plug structure is contacted with the top surface of the drain electrode connecting layer.

The drain electrode connecting layer is used for connecting the drain electrode interconnection structure and the heat dissipation structure, so that heat generated during operation of the device can be conducted to the heat dissipation structure through the drain electrode connecting layer, and accordingly the heat dissipation capability of the device is further improved.

Likewise, the heat dissipation structure is connected with the drain electrode connecting layer through the third plug structure, so that the heat dissipation effect of the heat dissipation structure is improved. For a detailed description of the material of the third plug structure, reference may be made to the related description of the second plug structure, which is not repeated here.

In still other embodiments, when the heat dissipation structure is located on a side of the drain region facing away from the gate structure, the drain connection layer may not be further disposed between the heat dissipation structure and the drain connection layer. When the device works, heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then the heat is dissipated through the heat dissipation structure.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1 and 2, fig. 1 is a top view, and fig. 2 is a cross-sectional view of fig. 1 at the AA1 position, providing a substrate including a plurality of discrete device regions I and isolation regions II between the device regions I, the substrate of the device regions I having a gate structure 120 formed thereon, the substrate of the device regions on one side of the gate structure 120 having an active region 130 formed therein, the substrate of the device regions on the other side of the gate structure 120 having a drain region 140 formed therein, and the substrate on the side of the gate structure 120 having a bottom dielectric layer 150 formed thereon covering the source region 130 and the drain region 140.

The substrate is used for providing a platform for a process. In this embodiment, in the step of providing the substrate, the substrate is a three-dimensional substrate. Specifically, in this embodiment, the base is used to form a fin field effect transistor (FinFET), and the base includes a substrate 100 and a fin 110 that is separated from the device region I substrate 100. In other embodiments, the substrate can also be a planar substrate.

In this embodiment, the substrate 100 is a silicon substrate.

The fin 110 is used to provide a conductive channel during device operation. In this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon.

In this embodiment, an isolation structure 111 is further formed on the substrate 100 to cover a portion of the sidewall of the fin 110.

The isolation structure 111 is used to isolate the adjacent fin 110, and the isolation structure 111 is also used to isolate the substrate 100 from the gate structure 120. In this embodiment, the material of the isolation structure 111 is silicon oxide.

The gate structure 120 is located on the isolation structure 111, and the gate structure 120 spans the plurality of fins 110 and covers a portion of the top and a portion of the sidewalls of the fins 110.

In this embodiment, the gate structure 120 is a metal gate structure, and includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

When forming an NMOS transistor, the source region 130 or the drain region 140 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source region 130 or the drain region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

The bottom dielectric layer 150 is used to isolate adjacent devices, and the bottom dielectric layer 150 is further used to electrically isolate the gate structure 120 from subsequent source and drain contact layers.

The bottom dielectric layer 150 is an interlayer dielectric layer. The material of the bottom dielectric layer 150 is an insulating material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Referring to fig. 3 and 4 in combination, fig. 3 is a top view, fig. 4 is a cross-sectional view of fig. 3 at an AA position, after providing a substrate, before forming the top dielectric layer and the heat spreader structure, the method of forming the semiconductor structure further includes: a source contact layer 135 is formed through the bottom dielectric layer 150 above the source region 130 and in contact with the source region 130, and a drain contact layer 145 is formed through the bottom dielectric layer 150 above the drain region 140 and in contact with the drain region 140.

Source contact layer 135 is used to make electrical connection between source 130 and external circuitry or other interconnect structures. The drain contact layer 145 is used to make electrical connection between the drain region 140 and an external circuit or other interconnect structure. The source contact layer 135 and the drain contact layer 145 are made of conductive materials, and include: one or more of cobalt, tungsten, copper, nickel, and aluminum.

In this embodiment, before forming the source contact layer 135 and the drain contact layer 145, a third dielectric layer 155 is formed on the bottom dielectric layer 150 to cover the gate structure 120.

In this embodiment, the third dielectric layer 155 is an inter-metal dielectric layer. In this embodiment, the material of the third dielectric layer 155 is silicon oxide.

In this embodiment, the third dielectric layer 155 is taken as an example of a single-layer structure. In other embodiments, the third dielectric layer may also be a multi-layer structure.

Accordingly, the step of forming the source contact layer 135 and the drain contact layer 145 includes: forming a source contact hole (not shown) penetrating the bottom dielectric layer 150 and the third dielectric layer 155 above the source region 130, and forming a drain contact hole (not shown) penetrating the bottom dielectric layer 150 and the third dielectric layer 155 above the drain region 140; a source contact layer 135 filled in the source contact hole and a drain contact layer 145 filled in the drain contact hole are formed.

In this embodiment, in the step of forming the source contact layer 135 and the drain contact layer 145, a gate contact layer 125 penetrating the third dielectric layer 155 above the gate structure 120 and contacting the top of the gate structure 120 is further formed.

The present embodiment takes the formation of the source and drain contact layers 135 and 145, and the gate contact layer 125 in the same step as an example. In other embodiments, the source and drain contact layers, and the gate contact layer can also be formed in different steps, respectively.

Referring to fig. 5 and 6 in combination, fig. 5 is a top view, fig. 6 is a cross-sectional view of fig. 5 at the AA1 position, and a second dielectric layer 160 is formed on the bottom dielectric layer 150 to cover the gate structure 120, the source contact layer 135, and the drain contact layer 145; a source interconnect 136 in contact with the top surface of the source contact layer 135 and a drain interconnect 146 in contact with the top surface of the drain contact layer 145 are formed in the second dielectric layer 160 of the device region I.

The second dielectric layer 160 is used to make electrical connection between the source interconnect structure 136 and the drain interconnect structure 146. In this embodiment, the second dielectric layer 160 is an inter-metal dielectric layer. For a description of the material of the second dielectric layer 160, reference may be made to the foregoing description of the third dielectric layer 155, which is not repeated herein.

In this embodiment, after the second dielectric layer 160 is formed, the source interconnect structure 136 and the drain interconnect structure 146 are formed in the second dielectric layer 160.

In this embodiment, the step of forming the source interconnect structure 136 and the drain interconnect structure 146 includes: forming a first conductive via (not shown) through the second dielectric layer 160 above the source contact layer 135 and a second conductive via (not shown) through the second dielectric layer 160 above the drain contact layer 145, the first and second conductive vias each including an interconnect trench (not shown) in a portion of the thickness of the second dielectric layer 160 and a conductive via (not shown) through a portion of the second dielectric layer 160 below the interconnect trench; the first conductive trench and the second conductive trench are filled with a conductive material to form the source interconnection 136 in the first conductive trench and the drain interconnection 146 in the second conductive trench, and the source interconnection 136 and the drain interconnection 146 each include a conductive plug 161 in the conductive via and an interconnection line 162 on the conductive plug 161.

The conductive plugs 161 and the interconnect 162 are made of a metal material including one or more of cobalt, tungsten, copper, nickel, and aluminum.

In this embodiment, in the step of forming the first conductive trench and the second conductive trench, a third conductive trench (not shown) penetrating the second dielectric layer 160 above the gate contact layer 125 is further formed, and the third conductive trench also includes an interconnection trench and a conductive via.

Accordingly, in the step of filling the first conductive trench and the second conductive trench with a conductive material, the third conductive trench is further filled with a conductive material, and a gate interconnection structure 126 located in the third conductive trench is formed, and the gate interconnection structure 126 also includes a conductive plug 161 and an interconnection line 162 located on the conductive plug 161.

As an example, a heat dissipation structure formed later is located in the top dielectric layer of the isolation region II, and the heat dissipation structure is located on a side of the source region 130 facing away from the gate structure 120.

It should be further noted that, in the step of forming the source interconnection structure 136, in this embodiment, the method for forming a semiconductor structure further includes: a source connection layer 170 is formed in the second dielectric layer 160 on the side of the source interconnection structure 136 facing away from the gate structure 120, the source connection layer 170 is located on the sidewall of the device region I and contacts the source interconnection structure 136, and the source connection layer 170 further extends to the isolation region II on the side of the source region 130 facing away from the gate structure 120.

Forming a source connection layer 170, so that a subsequently formed heat dissipation structure is connected with the source interconnection structure 170 through the source connection layer 170; compared with the heat emitted from the semiconductor structure is conducted to the heat dissipation structure through the dielectric material, in this embodiment, the source connection layer 170 is formed, the material of the source connection layer 170 is the same as the material of the source interconnection structure 136, the source connection layer 170 is made of a metal material, and the thermal conductivity of the material of the metal material is greater than that of the dielectric material, so that the heat emitted from the device during operation can be conducted into the heat dissipation structure more quickly, and then the heat is dissipated through the heat dissipation structure, so that the heat dissipation capability of the device is further improved.

Moreover, during operation of the device, the source region 145 is typically connected to zero potential, which is advantageous for reducing the effect of the heat sink structure on the electrical connection performance of the device by connecting the subsequent heat sink structure to the source interconnect structure 136 via the source connection layer 170.

In this embodiment, the source connection layer 170 is formed during the process of forming the source interconnect structure 136 and the drain interconnect structure 146. Specifically, during the process of forming the interconnection trench, the second dielectric layer 160 located on the side of the source interconnection structure 136 facing away from the gate structure 120 is further etched to form a connection trench (not shown); in the process of filling the first conductive groove and the second conductive groove with conductive material, the connection groove is further filled with conductive material, and the source connection layer 170 is formed in the connection groove.

By forming the source connection layer 170 during the formation of the source and drain interconnect structures 136 and 146, process compatibility and process integration are advantageously improved.

In this embodiment, the source connection layer 170 is formed as an example. In other embodiments, the source connection layer can also be omitted, and accordingly, heat generated during operation of the device is conducted through the top dielectric layer to the heat spreading structure.

In other embodiments, when the heat dissipation structure formed later is located at a side of the drain region facing away from the gate, in the step of forming the drain interconnection structure, the method for forming the semiconductor structure further includes: and forming a drain electrode connecting layer in the second dielectric layer at one side of the drain electrode interconnection structure, which is opposite to the gate electrode structure, wherein the drain electrode connecting layer is positioned on the side wall of the device region and is contacted with the drain electrode interconnection structure, and the drain electrode connecting layer also extends to an isolation region at one side of the drain region, which is opposite to the gate electrode.

Referring to fig. 7 to 10, a top dielectric layer 185 covering the gate structure 120 and a heat dissipation structure 180 located in the top dielectric layer 185 of the isolation region II are formed on the bottom dielectric layer 150; the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, or on a side of the drain region 140 facing away from the gate structure 120, or on a side of the source region 130 facing away from the gate structure 120, and on a side of the drain region 140 facing away from the gate structure 120; the heat dissipating structure 180 includes one or more thermally conductive layers 80 that are coupled.

In the method for forming a semiconductor structure provided by the embodiment of the invention, a heat dissipation structure 180 located in the top dielectric layer 185 of the isolation region II is also formed; the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, or on a side of the drain region 140 facing away from the gate structure 120, or on a side of the source region 130 facing away from the gate structure 120, and on a side of the drain region 140 facing away from the gate structure 120; the heat dissipating structure 180 includes one or more connected thermally conductive layers 80; by forming the heat dissipation structure 180, when the device works, heat generated by the device can be conducted out through the heat dissipation structure 180, so that the heat dissipation efficiency of the device is improved, and the Self-Heating Effect (SHE) of the device is correspondingly improved, so that the performance of the semiconductor structure is improved.

In particular, in this embodiment, the base includes the substrate 100 and the fin portion 110 located on the substrate 100, where the width of the fin portion 110 is generally smaller, and by forming the heat dissipation structure 180, the heat dissipation capability of the FinFET device is improved, so that the self-heating effect of the device can be significantly improved.

For this reason, the thermal conductivity of the material of the heat conducting layer 80 is not too low, which is advantageous for improving the heat dissipation capability of the heat dissipation structure 180, and thus for improving the self-heating effect of the heat dissipation structure 180 for improving the device. For this reason, in the present embodiment, the thermal conductivity of the material of the heat conductive layer 80 is at least 150W/mK. As an example, the thermal conductivity of the material of the thermally conductive layer 80 is 150W/mK to 1500W/mK

In this embodiment, the material of the heat conducting layer 80 is a metal material. The metal material has higher heat conductivity, so that the heat dissipation structure 180 is favorable to ensure higher heat conduction capacity, and the effect of the heat dissipation structure 180 on improving the self-heating effect of the device is further improved; in addition, the metal material is a material capable of conducting electricity, and the heat dissipation structure 180 can be formed in the process of forming the back-end interconnection structure by selecting the metal material, and the heat dissipation structure 180 is the same as the material of the back-end interconnection structure, so that the process for forming the heat dissipation structure 180 is integrated with the back-end interconnection process, and the process compatibility and the process integration degree are improved.

Specifically, the metallic material includes one or more of cobalt, tungsten, copper, nickel, and aluminum.

The present embodiment takes the heat dissipation structure 180 located on only one side of the source region 130 facing away from the gate structure 120 as an example. In other embodiments, the heat dissipation structure may also be located only on the side of the drain region facing away from the gate structure. In other embodiments, the heat spreading structure may also be located on a side of the drain region facing away from the gate structure and a side of the source region facing away from the gate structure.

When the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, the distance between the heat dissipation structure 180 and the source region 130 cannot be too small due to the limitation of design rules. However, the distance between the heat dissipating structure 180 and the source region 130 is not too large, which would easily reduce the efficiency of heat dissipation from the device to the heat dissipating structure 180, and thus, the effect of improving the self-heating effect of the heat dissipating structure 180 on the device is easily reduced, and the semiconductor structure occupies too large area. For this reason, in the present embodiment, when the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120, the distance between the heat dissipation structure 180 and the source region 130 is 2nm to 8nm.

As one example, the step of forming the top dielectric layer 185 includes sequentially forming a first dielectric layer 85 of a multi-layer stack; the step of forming the heat dissipation structure 180 includes forming a heat conductive layer 80 in each of the first dielectric layers 85, the heat dissipation structure including a plurality of layers of the heat conductive layer 80; one of the thermally conductive layers 80 closest to the substrate is a bottom thermally conductive layer 80a, and each of the thermally conductive layers 80 located above the bottom thermally conductive layer 80a is a top thermally conductive layer 80b.

By forming the heat conductive layer 80 in multiple layers, the heat dissipation efficiency of the heat dissipation structure 180 is advantageously improved.

Accordingly, the first dielectric layer 85 is used to electrically isolate the thermally conductive layer from the back-end interconnect structure. In this embodiment, the first dielectric layer 85 is an inter-metal dielectric layer. The material of the first dielectric layer 85 is a low-k dielectric material, an ultra-low k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or the like.

In this embodiment, the step of forming the heat dissipation structure 180 further includes: in the step of forming the top heat conductive layer 80b, a first plug structure 81 and the top heat conductive layer 80b on the first plug structure 81 are formed in the first dielectric layer 85; wherein the first plug structure 81 is in contact with the top of one of the heat conductive layers 80 located therebelow.

The material of the first plug structure 81 is also a metal material, which is not only advantageous for improving the heat conduction capability of the first plug structure 81, but also for enabling the process of forming the first plug structure 81 to be compatible with the back-end interconnect process. In this embodiment, the material of the first plug structure 81 is the same as that of the heat conductive layer 80.

In other embodiments, the step of forming a top dielectric layer includes forming a first dielectric layer; the step of forming the heat dissipation structure comprises forming a heat conduction layer in the first dielectric layer, wherein the heat dissipation structure comprises a layer of heat conduction layer.

In this embodiment, the heat dissipation structure 180 includes multiple heat conductive layers 80, and one heat conductive layer 80 closest to the substrate is used as the bottom heat conductive layer 80a. In other embodiments, the heat dissipating structure includes a layer of thermally conductive layer that acts as a bottom thermally conductive layer.

In this embodiment, the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, and the source connection layer 170 is further formed in the second dielectric layer 160 on a side of the source interconnection structure 136 facing away from the gate structure 120.

To this end, the step of forming the heat dissipation structure 180 further includes: in the step of forming the bottom thermal conductive layer 80a, the second plug structure 82 and the bottom thermal conductive layer 80a on the second plug structure 82 are formed, and the second plug structure 82 is in contact with the source connection layer 170 at the top of the isolation region II.

By forming the second plug structure 82, the bottom heat conducting layer 80a is connected to the source connection layer 170, and accordingly, the heat dissipating structure 180 is connected to the source contact layer 135, and heat generated during operation of the device can be conducted to the heat dissipating structure 180 through the source connection layer 170, which is beneficial to improving heat dissipating efficiency and heat dissipating capacity of the heat dissipating structure 180, and further is beneficial to improving the effect of the heat dissipating structure 190 for improving self-heating effect of the device.

The material of the second plug structure 82 is a metal material, which is not only beneficial to improving the heat conduction capability of the second plug structure 82, but also beneficial to making the process of forming the second plug structure 82 compatible with the back-end interconnection process, thereby improving the process integration and the process compatibility. In this embodiment, the material of the second plug structure 82 is the same as the material of the source interconnect structure 136 or the drain interconnect structure 146, and includes one or more of cobalt, tungsten, copper, nickel, and aluminum.

Accordingly, in this embodiment, the step of forming the top dielectric layer 185 and the heat dissipation structure 180 includes: as shown in fig. 7 and 8, fig. 7 is a top view, fig. 8 is a schematic partial cross-sectional view of fig. 7 at the BB1 position, and a first dielectric layer 85a is formed on the second dielectric layer 160; forming a second plug structure 82 in the first dielectric layer 85a and a bottom thermally conductive layer 80a on the second plug structure 82; as shown in fig. 9 and 10, fig. 9 is a top view, and fig. 10 is a schematic partial cross-sectional view of fig. 9 at the BB1 position, a first dielectric layer 85b is formed on the first dielectric layer 85a; a first plug structure 81 and a top thermally conductive layer 80b on the first plug structure 81 are formed in the first dielectric layer 85 b.

In this embodiment, the heat dissipation structure 180 is located on a side of the source region 130 facing away from the gate structure 120, and the source connection layer 170 for connecting the source region contact layer 135 and the heat dissipation structure 180 is formed as an example. In other embodiments, when the heat dissipation structure is located on a side of the source region opposite to the gate structure, the source connection layer may not be formed on the contact layer between the heat dissipation structure and the source region, and accordingly, when the device works, heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then is dissipated through the heat dissipation structure.

In other embodiments, when the heat dissipation structure is located on a side of the drain region facing away from the gate structure, the step of forming the heat dissipation structure further includes: in the step of forming the bottom heat conducting layer, a third plug structure and the bottom heat conducting layer positioned on the third plug structure are formed, and the third plug structure is in contact with the top of the isolation region at the position of the drain electrode connecting layer. Likewise, the heat dissipation structure is connected with the drain electrode connecting layer through the third plug structure, so that the heat dissipation effect of the heat dissipation structure is improved. For a detailed description of the material of the third plug structure, reference may be made to the related description of the second plug structure, which is not repeated here.

Alternatively, when the heat dissipation structure is located at a side of the drain region facing away from the gate structure, the drain connection layer may not be formed between the heat dissipation structure and the drain connection layer. Accordingly, when the device works, heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then the heat is dissipated through the heat dissipation structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising discrete device regions and isolation regions between the device regions;

the grid structure is positioned on the substrate of the device region;

the source region is positioned in the substrate of the device region at one side of the grid structure;

the drain region is positioned in the substrate of the device region at the other side of the grid structure;

the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source region and the drain region;

a top dielectric layer overlying the bottom dielectric layer and covering the gate structure;

the heat dissipation structure is positioned in the top dielectric layer of the isolation region; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more layers of connected heat conduction layers.

2. The semiconductor structure of claim 1, wherein the base comprises a substrate and a plurality of fins discrete on the device region substrate;

the grid structure spans across the fin parts and covers part of the top and part of the side wall of the fin part; the source region is located in the fin portion on one side of the gate structure, and the drain region is located in the fin portion on the other side of the gate structure.

3. The semiconductor structure of claim 1, wherein the top dielectric layer comprises a first dielectric layer; the heat dissipation structure comprises a heat conduction layer, and the heat conduction layer is positioned in the first medium layer;

alternatively, the top dielectric layer comprises a first dielectric layer of a multi-layer stack; the heat dissipation structure comprises a plurality of heat conduction layers, and the heat conduction layers are positioned in the first medium layer; wherein, one heat conducting layer closest to the substrate is a bottom heat conducting layer, and each heat conducting layer above the bottom heat conducting layer is a top heat conducting layer;

the heat dissipation structure further includes: the first plug structure is positioned in the first dielectric layer below each top heat conduction layer and connected with the top heat conduction layer; the first plug structure is in contact with the top of a thermally conductive layer located therebelow.

4. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the source region contact layer penetrates through the bottom dielectric layer above the source region and is in contact with the source region;

the drain region contact layer penetrates through the bottom dielectric layer above the drain region and is contacted with the drain region;

a second dielectric layer located between the top dielectric layer and the bottom dielectric layer;

the source electrode interconnection structure is positioned in the second dielectric layer of the device region and is contacted with the top surface of the source region contact layer;

and the drain interconnection structure is positioned in the second dielectric layer of the device region and is contacted with the top surface of the drain region contact layer.

5. The semiconductor structure of claim 1, wherein when the heat spreading structure is located on a side of the source region facing away from the gate structure, the heat spreading structure is located at a distance of 2nm to 8nm from the source region;

when the heat dissipation structure is positioned on one side of the drain region, which is away from the gate structure, the distance between the heat dissipation structure and the drain region is 2nm to 8nm.

6. The semiconductor structure of claim 4, wherein the heat spreading structure comprises a layer of thermally conductive layer that acts as a bottom thermally conductive layer; alternatively, the heat dissipation structure includes a plurality of heat conductive layers, and one heat conductive layer closest to the substrate is used as a bottom heat conductive layer;

When the heat dissipation structure is located at a side of the source region facing away from the gate structure, the semiconductor structure further includes: the source electrode connecting layer is positioned in the second dielectric layer at one side of the source electrode interconnection structure, which is opposite to the gate electrode structure, the side wall of the source electrode connecting layer is contacted with the source electrode interconnection structure, and the source electrode connecting layer also extends into the second dielectric layer below the bottom heat conducting layer;

the heat dissipation structure further includes: and the second plug structure is positioned in the first dielectric layer between the source electrode connecting layer and the bottom heat conducting layer and is connected with the bottom heat conducting layer, and the bottom of the second plug structure is contacted with the top surface of the source electrode connecting layer.

7. The semiconductor structure of claim 4, wherein the heat spreading structure comprises a layer of thermally conductive layer that acts as a bottom thermally conductive layer; alternatively, the heat dissipation structure includes a plurality of heat conductive layers, and one heat conductive layer closest to the substrate is used as a bottom heat conductive layer;

when the heat dissipation structure is located at one side of the drain region, which is away from the gate electrode, the semiconductor structure further comprises: the drain electrode connecting layer is positioned in the second dielectric layer at one side of the drain electrode interconnection structure, which is opposite to the gate electrode structure, the side wall of the drain electrode connecting layer is contacted with the drain electrode interconnection structure, and the drain electrode connecting layer also extends into the second dielectric layer below the bottom heat conducting layer;

The heat dissipation structure further includes: and the third plug structure is positioned in the first dielectric layer between the drain electrode connecting layer and the bottom heat conducting layer and is connected with the bottom heat conducting layer, and the bottom of the third plug structure is contacted with the top surface of the drain electrode connecting layer.

8. The semiconductor structure of claim 1, wherein a thermal conductivity of a material of the thermally conductive layer is at least 150W/mK.

9. The semiconductor structure of claim 3, wherein a material of the first plug structure is a metallic material.

10. The semiconductor structure of claim 6, wherein a material of the second plug structure is a metallic material.

11. The semiconductor structure of claim 7, wherein a material of the third plug structure is a metallic material.

12. The semiconductor structure of claim 1, wherein the thermally conductive layer is a metallic material.

13. The semiconductor structure of any one of claims 9 to 12, wherein the metallic material comprises one or more of cobalt, tungsten, copper, and aluminum, nickel.

14. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein the substrate comprises a plurality of discrete device regions and isolation regions positioned between the device regions, a grid structure is formed on the substrate of the device regions, an active region is formed in the substrate of the device regions on one side of the grid structure, a drain region is formed in the substrate of the device regions on the other side of the grid structure, and a bottom dielectric layer covering the source region and the drain region is formed on the substrate on the side of the grid structure;

forming a top dielectric layer covering the gate structure and a heat dissipation structure in the top dielectric layer of the isolation region on the bottom dielectric layer; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more layers of connected heat conduction layers.

15. The method of forming a semiconductor structure of claim 14, wherein in the step of providing a base, the base includes a substrate and a fin separate from the device region substrate;

16. The method of forming a semiconductor structure of claim 14, wherein the step of forming the top dielectric layer comprises forming a first dielectric layer; the step of forming the heat dissipation structure comprises the steps of forming the heat conduction layer in the first dielectric layer, wherein the heat dissipation structure comprises a layer of heat conduction layer;

or alternatively, the process may be performed,

the step of forming the top dielectric layer comprises sequentially forming a first dielectric layer of a multi-layer stack; the step of forming the heat dissipation structure comprises the steps of forming the heat conduction layers in each first dielectric layer, wherein the heat dissipation structure comprises a plurality of heat conduction layers; one heat conducting layer closest to the substrate is a bottom heat conducting layer, and each heat conducting layer above the bottom heat conducting layer is a top heat conducting layer;

the step of forming the heat dissipation structure further comprises: forming a first plug structure and the top heat conducting layer on the first plug structure in the first dielectric layer in the step of forming the top heat conducting layer; wherein the first plug structure is in contact with the top of a thermally conductive layer located therebelow.

17. The method of forming a semiconductor structure as claimed in any one of claims 14 to 16, wherein after providing the substrate, prior to forming the top dielectric layer and the heat sink structure, the method of forming a semiconductor structure further comprises: forming a source region contact layer penetrating through the bottom dielectric layer above the source region and contacting the source region, and forming a drain region contact layer penetrating through the bottom dielectric layer above the drain region and contacting the drain region;

Forming a second dielectric layer covering the gate structure, the source region contact layer and the drain region contact layer on the bottom dielectric layer;

and forming a source electrode interconnection structure contacted with the top surface of the source region contact layer and a drain electrode interconnection structure contacted with the top surface of the drain region contact layer in the second dielectric layer of the device region.

18. The method of forming a semiconductor structure of claim 17, wherein in the step of forming a source interconnect structure, the method of forming a semiconductor structure further comprises: forming a source electrode connecting layer in the second dielectric layer at one side of the source electrode interconnection structure, which is opposite to the gate electrode structure, wherein the source electrode connecting layer is positioned on the side wall of the device region and is contacted with the source electrode interconnection structure, and the source electrode connecting layer also extends to an isolation region at one side of the source region, which is opposite to the gate electrode;

the heat dissipation structure comprises a heat conduction layer, wherein the heat conduction layer is used as a bottom heat conduction layer; alternatively, the heat dissipation structure includes a plurality of heat conductive layers, and one heat conductive layer closest to the substrate is used as a bottom heat conductive layer;

the step of forming the heat dissipation structure further comprises: in the step of forming the bottom heat conduction layer, a second plug structure and the bottom heat conduction layer positioned on the second plug structure are formed, and the second plug structure is contacted with the source electrode connecting layer at the top of the isolation region.

19. The method of forming a semiconductor structure of claim 17, wherein in the step of forming a drain interconnect structure, the method of forming a semiconductor structure further comprises: forming a drain electrode connecting layer in a second dielectric layer at one side of the drain electrode interconnection structure, which is opposite to the gate electrode structure, wherein the drain electrode connecting layer is positioned on the side wall of the device region and is contacted with the drain electrode interconnection structure, and the drain electrode connecting layer also extends to an isolation region at one side of the drain region, which is opposite to the gate electrode;

the step of forming the heat dissipation structure further comprises: in the step of forming the bottom heat conduction layer, a third plug structure and the bottom heat conduction layer positioned on the third plug structure are formed, and the third plug structure is contacted with the top of the drain electrode connecting layer positioned in the isolation region.

20. The method of claim 14, wherein the thermally conductive layer is a metallic material.