CN113764363A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN113764363A
CN113764363A CN202110257151.5A CN202110257151A CN113764363A CN 113764363 A CN113764363 A CN 113764363A CN 202110257151 A CN202110257151 A CN 202110257151A CN 113764363 A CN113764363 A CN 113764363A
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China
Prior art keywords
chip structure
chip
trench
substrate
heat dissipation
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Pending
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CN202110257151.5A
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English (en)
Inventor
柳孝昌
金喆禹
柳周铉
李相贤
崔允硕
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN113764363A publication Critical patent/CN113764363A/zh
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Abstract

一种半导体封装，包括：第一基板；在第一基板上彼此间隔开的第一芯片结构和第二芯片结构，在第一芯片结构和第二芯片结构之间限定有间隙区域；以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件，该散热构件在该散热构件的内顶表面中包括第一沟槽，其中，第一沟槽与间隙区域竖直地重叠并且宽度大于间隙区域的宽度，并且其中第一沟槽至少与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分竖直地重叠。

Description

半导体封装
相关申请的交叉引用
本申请要求于2020年6月3日在韩国知识产权局提交的题为“半导体封装”的韩国专利申请No.10-2020-0067277的优先权，其通过引用整体并入本文。
技术领域
实施例涉及半导体封装。
背景技术
集成电路芯片可以以半导体封装的形式实现，以便适当地应用于电子产品。在典型的半导体封装中，半导体芯片可以安装在印刷电路板(PCB)上，并且可以通过接合线或凸块电连接到PCB。随着电子产业的发展，已经研究了用于提高半导体封装的可靠性和耐用性的各种技术。
发明内容
在一方面，一种半导体封装可以包括：第一基板；在第一基板上彼此间隔开的第一芯片结构和第二芯片结构，在第一芯片结构和第二芯片结构之间设置有间隙区域；以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件。散热构件可以包括设置在散热构件的内顶表面中的第一沟槽，第一沟槽可以与间隙区域竖直地重叠并且宽度可以大于间隙区域的宽度。第一沟槽可以与第一芯片结构的顶表面的一部分或第二芯片结构的顶表面的一部分中的至少一个竖直地重叠。
在另一方面，一种半导体封装可以包括：封装基板；设置在封装基板上的中介层基板；安装在中介层基板上并且彼此间隔开的第一芯片结构和第二芯片结构，在第一芯片结构和第二芯片结构之间设置有间隙区域；以及覆盖第一芯片结构、第二芯片结构、中介层基板和封装基板并且粘附到封装基板的顶表面的散热构件。散热构件可以包括设置在散热构件的内顶表面中的第一沟槽，第一沟槽可以与间隙区域重叠并且宽度可以大于间隙区域的宽度。第一沟槽可以与第一芯片结构的顶表面的一部分和第二芯片结构的顶表面的一部分竖直地重叠。散热构件可以在与第一沟槽间隔开的部分处具有第一厚度，并且第一沟槽的深度可以在第一厚度的1/3至2/3的范围内。
在另一方面，一种半导体封装可以包括：第一基板；在第一基板上彼此间隔开的第一芯片结构和第二芯片结构，在第一芯片结构和第二芯片结构之间设置有间隙区域；以及覆盖第一芯片结构、第二芯片结构和第一基板的散热构件。散热构件可以包括与间隙区域重叠并且宽度大于间隙区域的宽度的第一沟槽。散热构件可以包括三个第一外角和一个第二外角，并且第二外角的形状可以与第一外角的形状不同。
附图说明
通过参考附图详细描述示例性实施例，特征对于本领域技术人员将变得显而易见，在附图中：
图1是示出了根据一些实施例的半导体封装的平面图。
图2是根据一些实施例的沿图1的线A-A’的截面图。
图3A，图3B和图3C是根据一些实施例的图2的部分P1的放大视图。
图4A，图4B和图4C是根据一些实施例的图2的部分P1的放大视图。
图5是示出了根据一些实施例的在第一芯片结构和第二芯片结构之间的结构的透视图。
图6是示出了制造具有图2的截面的半导体封装的过程的截面图。
图7是示出了根据一些实施例的半导体封装的截面图。
图8是示出了根据一些实施例的半导体封装的平面图。
图9是根据一些实施例的沿图8的线A-A’的截面图。
图10是根据一些实施例的沿图8的线A-A’的截面图。
图11是示出了根据一些实施例的半导体封装的平面图。
图12是示出了根据一些实施例的半导体封装的截面图。
图13是示出了根据一些实施例的半导体封装的截面图。
图14是示出了根据一些实施例的半导体封装的平面图。
图15是根据一些实施例的沿图14的线A-A’的截面图。
具体实施方式
图1是示出了根据一些实施例的半导体封装的平面图。图2是沿图1的线A-A’的截面图，并且图3A至图3C是根据一些实施例的图2的部分P1的放大图。
参照图1和图2，根据本示例实施例的半导体封装100可以包括第一基板10。第二基板30可以安装在第一基板10上。第一芯片结构50和至少一个第二芯片结构60可以安装在第二基板30上，并且可以沿第一方向X布置，例如，第一芯片结构50和至少一个第二芯片结构60可以沿第一方向X彼此相邻(图1和图2)。如果设置多于一个的第二芯片60，例如，当设置两个第二芯片结构60时，则第二芯片结构60可以沿第二方向Y布置，例如，两个第二芯片结构60可以沿第二方向Y彼此相邻(图1)。
如图1和图2进一步所示，散热构件80可以覆盖第一芯片结构50、第二芯片结构60、第二基板30和第一基板10。可以在散热构件80的底表面和第一基板10之间插入粘合层82。第一热界面材料层70a可以插入在散热构件80和第一芯片结构50之间，并且第二热界面材料层70b可以插入在散热构件80和每个第二芯片结构60之间。
例如，第一基板10可以是印刷电路板(PCB)。第一基板10可以被称为封装基板。第一基板10可以包括：第一芯部11；设置在第一芯部11的顶表面上的第一基板上部导电图案13；覆盖第一芯部11的顶表面的第一基板上部保护层17；设置在第一芯部11的底表面上的第一基板下部导电图案15；以及覆盖第一芯部11的底表面的第一基板下部保护层19。第一基板上部导电图案13可以电连接到第一基板下部导电图案15。外部连接端子22可以结合到第一基板下部导电图案15。外部连接端子22可以是焊球。外部连接端子22可以包括锡或铅中的至少一种。
第一芯部11可以包括但不限于以下至少一种：热固性树脂(例如，环氧树脂)、热塑性树脂(例如，聚酰亚胺)、通过用增强材料(例如，玻璃纤维和/或无机填料)浸渍热固性树脂或热塑性树脂而获得的树脂(例如，预浸料)或光固化树脂。第一基板上部保护层17和第一基板下部保护层19可以是光敏阻焊(PSR)层。光敏阻焊剂(PSR)可以包括光敏聚合物。光敏聚合物可以包括例如光敏聚酰亚胺(PSPI)、聚苯并恶唑(PBO)、酚聚合物或苯并环丁烯基聚合物(BCB)中的至少一种。光敏阻焊剂(PSR)还可以包括无机填料。第一基板上部导电图案13和第一基板下部导电图案15可以包括例如铜、铝或金中的至少一种。
第二基板30可以被称为中介层基板。第二基板30可以包括：第二芯部31；设置在第二芯部31的顶表面上的第二基板上部导电图案37；覆盖第二芯部31的顶表面的第二基板上部保护层33；设置在第二芯部31的底表面上的第二基板下部导电图案39；以及覆盖第二芯部31的底表面的第二基板下部保护层35。例如，贯穿通孔可以设置在第二基板30中。
第二芯部31可以包括例如硅。第二基板上部保护层33和第二基板下部保护层35可以是光敏阻焊(PSR)层。光敏阻焊剂(PSR)可以包括光敏聚合物。光敏聚合物可以包括例如光敏聚酰亚胺(PSPI)、聚苯并恶唑(PBO)、酚聚合物或苯并环丁烯基聚合物(BCB)中的至少一种。光敏阻焊剂(PSR)还可以包括无机填料。第二基板上部导电图案37和第二基板下部导电图案39可以包括例如铜、铝或金中的至少一种。
第一基板10和第二基板30可以通过第一内部连接端子26彼此电连接。第一内部连接端子26可以将第一基板上部导电图案13电连接到第二基板下部导电图案39。第一内部连接端子26中的每一个可以包括例如焊球、导电凸块或导电柱中的至少一种。第一内部连接端子26可以包括例如铜、锡或铅中的至少一种。第一底部填充层24可以插入在第一基板10和第二基板30之间。
例如，第一芯片结构50和/或第二芯片结构60可以是单个半导体芯片或单个半导体管芯。单个半导体芯片或单个半导体管芯可以包括半导体基板、以及包括布置在半导体基板上的多个晶体管、电阻元件、电容器和互连结构在内的电路结构。在另一示例中，第一芯片结构50和/或第二芯片结构60可以是具有半导体封装结构的芯片，在该半导体封装结构中半导体芯片/管芯并排地堆叠或布置。第一芯片结构50和第二芯片结构60可以被称为半导体芯片、半导体管芯或亚半导体封装。
例如，第一芯片结构50和第二芯片结构60可以各自独立地为系统大规模集成(LSI)芯片、逻辑电路芯片、图像传感器芯片(例如，互补金属氧化物半导体(CMOS)或成像传感器(CIS))、存储器件芯片(例如，闪存芯片、动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁阻随机存取存储器(MRAM)芯片、电阻随机存取存储器(ReRAM)芯片、高带宽存储器(HBM)芯片或混合存储器立方(HMC)芯片)、微机电系统(MEMS)器件芯片或专用集成电路(ASIC)芯片。具体地，第一芯片结构50可以是ASIC芯片，并且第二芯片结构60可以是HBM芯片。
第一芯片导电焊盘53和第一芯片保护层55可以设置在第一芯片结构50的底表面上。第一芯片导电焊盘53可以包括金属，例如，铝或铜。第一芯片保护层55可以由例如氮化硅或聚酰亚胺形成。第一芯片导电焊盘53可以通过第二内部连接端子40电连接到第二基板上部导电图案37中的一些。第二内部连接端子40中的每一个可以包括例如焊球、导电凸块或导电柱中的至少一种。第二内部连接端子40可以包括例如铜、锡或铅中的至少一种。第二底部填充层42可以插入在第一芯片结构50和第二基板30之间。第一芯片结构50可以包括与第二芯片结构60相邻的第一芯片右侧壁50sr，以及与第一芯片右侧壁50sr相对的第一芯片左侧壁50s1。
第二芯片导电焊盘63和第二芯片保护层65可以设置在第二芯片结构60的底表面上。第二芯片导电焊盘63可以包括金属，例如，铝或铜。第二芯片保护层65可以由氮化硅或聚酰亚胺形成。第二芯片导电焊盘63可以通过第三内部连接端子44电连接到第二基板上部导电图案37中的另一些。第三内部连接端子44中的每一个可以包括例如焊球、导电凸块或导电柱中的至少一种。第三内部连接端子44可以包括例如铜、锡或铅中的至少一种。第三底部填充层46可以插入在第二芯片结构60和第二基板30之间。第二芯片结构60可以包括与第一芯片结构50相邻的第二芯片左侧壁60s1，以及与第二芯片左侧壁60s1相对的第二芯片右侧壁60sr。
第一底部填充层至第三底部填充层24、42和46可以包括热固性树脂或光固化树脂。另外，第一底部填充层至第三底部填充层24、42和46还可以包括有机填料或无机填料。第二底部填充层42可以沿第一方向X与第三底部填充层46间隔开。
散热构件80可以包括具有优异导热性的材料，例如，金属。散热构件80可以包括由散热构件80的内顶表面80at和内侧壁80as限定的空腔CV，并且第一芯片结构50和第二芯片结构60以及第二基板30可以插入在空腔CV中，例如，散热构件80可以在第一基板10上具有Π形截面，以在第一基板10和Π形截面之间限定空腔CV。第一热界面材料层70a和第二热界面材料层70b中的每一个可以包括热固性树脂层。第一热界面材料层70a和第二热界面材料层70b中的每一个还可以包括分散在热固性树脂层中的填料颗粒。填料颗粒可以包括例如氧化硅、氧化铝、氧化锌或硼化氮中的至少一种。粘合层82可以包括与第一热界面材料层70a和第二热界面材料层70b相同的材料。
参照图2，第二基板30可以例如沿第一方向X和/或第二方向Y与散热构件80的内侧壁80as间隔开第一距离DS1。第一芯片结构50可以例如沿第一方向X和/或第二方向Y与散热构件80的内侧壁80as间隔开第二距离DS2。第二芯片结构60也可以与散热构件80的内侧壁80as间隔开第二距离DS2。第二距离DS2可以大于第一距离DS1。例如，第一距离DS1可以是600μm或更大，例如，第一距离DS1可以在约700μm至约1400μm的范围内。例如，第二距离DS2可以是1000μm或更大，例如，第二距离DS1可以在约2000μm至约3000μm的范围内。
参照图1至图3A，第一芯片结构50和第二芯片结构60可以彼此间隔开，因此可以在第一芯片结构50和第二芯片结构60之间形成间隙区域GP。第一芯片右侧壁50sr和第二芯片左侧壁60s1可以通过间隙区域GP而暴露。第一芯片右侧壁50sr可以例如沿第一方向X(图3A)与第二芯片左侧壁60s1间隔开第三距离DS3，并且第三距离DS3可以对应于间隙区域GP的宽度。第二芯片结构60之间例如沿第二方向Y的距离可以等于第三距离DS3，或者可以在第三距离DS3的约0.8倍至约1.2倍的范围内。例如，第三距离DS3可以在约500μm至约700μm的范围内。
参照图1，散热构件80可以具有沿顺时针方向布置的四个外侧壁80bs，以及外侧壁80bs彼此相遇处的外角80R和80FC。外角80R和80FC可以包括三个第一外角80R和一个第二外角80FC。第二外角80FC的形状可以与第一外角80R的形状不同，因此可以用作方向/位置的参考。例如，当在平面图中观察时，第一外角80R可以具有圆形的(例如，弯曲的)形状。当在平面图中观察时，第二外角80FC可以具有带刻面的刻面(例如，线性)形状，例如，第二外角80FC可以具有相对于散热构件80的每个邻接的外侧壁80bs以倾斜角倾斜的平坦表面。第二外角80FC可以代表散热构件80或半导体封装100的安装方向。
如图1和图2进一步所示，可以在散热构件80的内顶表面80at中设置例如在竖直方向上与间隙区域GP重叠的沟槽TR。可以根据间隙区域GP的平面形状来改变沟槽TR的平面形状。在本实施例中，如图1所示，当在平面图中观察时，沟槽TR可以具有T形，例如以与第一芯片结构50和第二芯片结构60之间的间隙区域GP的形状重叠。沟槽TR可以形成为从散热构件80的内顶表面80at朝向外顶表面80bt凹陷，如图2所示。
参照图3A，第一芯片结构50的第一芯片顶表面50t的一部分或第二芯片结构60的第二芯片顶表面60t的一部分中的至少一个可以与沟槽TR竖直地重叠。沟槽TR可以具有沟槽顶表面TRt、以及彼此相对的第一沟槽侧壁TRs1和第二沟槽侧壁TRs2，例如，第一沟槽侧壁TRs1和第二沟槽侧壁TRs2可以沿第一方向X彼此间隔开。第一沟槽侧壁TRs1可以与第一芯片右侧壁50sr相邻，同时例如沿第一方向X与第一芯片右侧壁50sr间隔开第四距离DS4。因此，第一芯片结构50的第一芯片顶表面50t的至少一部分可以被暴露。第四距离DS4可以对应于第一芯片顶表面50t与沟槽TR重叠的部分在第一方向X上的宽度。第四距离DS4可以在第三距离DS3的约0.8倍至约1.2倍的范围内。
第二沟槽侧壁TRs2可以与第二芯片左侧壁60s1相邻，同时与第二芯片左侧壁60s1间隔开第五距离DS5。因此，第二芯片结构60的第二芯片顶表面60t的至少一部分可以被暴露。第五距离DS5可以对应于第二芯片顶表面60t与沟槽TR重叠的部分在第一方向X上的宽度。第五距离DS5可以在第三距离DS3的约0.8倍至约1.2倍的范围内。
第一沟槽侧壁TRs1和第二沟槽侧壁TRs2之间的第六距离DS6可以大于第三距离DS3，第六距离DS6对应于沟槽TR的宽度。第六距离DS6可以对应于第三距离到第五距离DS3、DS4和DS5之和。第一芯片顶表面50t的一部分和第二芯片顶表面60t的一部分可以与沟槽TR重叠。
散热构件80可以具有从内顶表面80at到外顶表面80bt的第一厚度T1，如图2所示。为了实质上最小化或防止半导体封装100的翘曲现象，第一厚度T1可以在约700μm至约2000μm的范围内。如果第一厚度T1小于700μm，则半导体封装100的翘曲现象可能增加。如果第一厚度T1大于2000μm，则半导体封装100的高集成度可能是困难的。
从散热构件80的内顶表面80at到沟槽顶表面TRt的距离(即，沟槽TR的深度DT1)可以例如沿方向Z小于第一厚度T1。在制造半导体封装100的过程中，当分别位于第一芯片结构50和第二芯片结构60上的热界面材料层70a和70b被散热构件80挤压时，散热构件80的该特定结构可以防止从沟槽侧壁TRs1和TRs2横向突出的热界面材料层70a和70b由于散热构件80的挤压而进入间隙区域GP。例如，参照图2，由于沟槽TR的深度以及第一芯片结构50和第二芯片结构60的上表面的暴露部分，当热界面材料层70a和70b被散热构件80挤压靠在第一芯片结构50和第二芯片结构60上时，热界面材料层70a和70b可以沿第一芯片结构50和第二芯片结构60的上表面的暴露部分延伸以及沿沟槽TR的侧壁延伸进沟槽TR(而不是超出第一芯片结构50和第二芯片结构60进入间隙区域GP)。换句话说，此时，热界面材料层70a和70b可以在进入间隙区域GP之前首先进入沟槽TR。如果沟槽TR的深度DT1太小，则热界面材料层70a和70b可能无法充分进入沟槽TR，并且可能进入间隙区域GP。
在一些实施例中，沟槽TR的深度DT1可以等于或大于第四距离DS4和第五距离DS5中的较大者。因此，伸出(或突出)到与沟槽TR重叠的第一芯片顶表面50t上的第一热界面材料层70a可以充分地进入沟槽TR。第一热界面材料层70a可以与第一沟槽侧壁TRs1接触。另外，伸出(或突出)到与沟槽TR重叠的第二芯片顶表面60t上的第二热界面材料层70b可以充分地进入沟槽TR。第二热界面材料层70b可以与第二沟槽侧壁TRs2接触。
在一些实施例中，沟槽TR的深度DT1可以小于第一厚度T1的2/3。如果沟槽TR的深度DT1大于第一厚度T1的2/3，则散热构件80在沟槽TR上的部分可能太薄，因此半导体封装100的翘曲特性可能劣化。在一些实施例中，第三距离到第五距离DS3、DS4和DS5可以彼此相等。沟槽TR的深度DT1可以在第四距离DS4或第五距离DS5的约1倍至约1.3倍的范围内。沟槽TR的深度DT1可以在第一厚度T1的约1/3到约2/3的范围内。第三距离到第五距离DS3、DS4和DS5中的每一个可以为例如约600μm。沟槽TR的深度DT1可以为例如约700μm。第一厚度T1可以为例如约1500μm。
如果第一沟槽侧壁TRs1与第一芯片右侧壁50sr对齐或与间隙区域GP重叠，则第一热界面材料层70a会更有可能由于重力而进入间隙区域GP，而不是进入沟槽TR。另外，如果第二沟槽侧壁TRs2与第二芯片左侧壁60s1对齐或与间隙区域GP重叠，则第二热界面材料层70b会更有可能由于重力而进入间隙区域GP，而不是进入沟槽TR。如果沟槽TR的宽度DS6等于或小于间隙区域GP的宽度DS3，则热界面材料层70a和70b会更有可能由于重力而进入间隙区域GP，而不是进入沟槽TR。在这些情况下，半导体封装的可靠性会劣化。
第一芯片结构50的第一芯片左侧壁50s1的顶端可以与第一热界面材料层70a接触。第二芯片结构60的第二芯片右侧壁60sr的顶端可以与第二热界面材料层70b接触。
参照图3A至图3C，第一沟槽侧壁TRs1或第二沟槽侧壁TRs2可以在入口部分TRC处与散热构件80的内顶表面80at相遇。例如，入口部分TRC的截面可以成约90度角度，如图3A所示。在另一示例中，入口部分TRC的截面可以是圆形的，如图3B所示。在又一示例中，入口部分TRC的截面可以具有阶梯形状，如图3C所示。图3B或图3C中的入口部分TRC的结构可以更容易实现。第一热界面材料层70a和第二热界面材料层70b可以与沟槽顶表面TRt间隔开。
图4A至图4C是根据其他实施例的图2的P1的放大视图。
在一些实施例中，第一热界面材料层70a和第二热界面材料层70b中的至少一个可以与沟槽顶表面TRt接触，如图4A所示。在某些实施例中，第一热界面材料层70a和第二热界面材料层70b可以彼此接触并且可以填充沟槽TR，如图4B所示。另外，第一热界面材料层70a和第二热界面材料层70b的一部分可以例如部分地插入间隙区域GP，如图4C所示。
图5是示出了根据一些实施例的在第一芯片结构50和第二芯片结构60之间的结构的透视图。
参照图2、图4C和图5，间隙区域GP可以设置在第一芯片结构50的第一芯片右侧壁50sr和第二芯片结构60的第二芯片左侧壁60s1之间。间隙区域GP的顶端可以由第一芯片结构50的顶表面50t或第二芯片结构60的顶表面60t的高度限定。间隙区域GP的底端可以由第二基板30的顶表面(即，第二基板上部保护层33的顶表面)限定。间隙区域GP的一侧可以由第一芯片结构50的第一芯片右侧壁50sr限定。间隙区域GP的另一侧可以由第二芯片结构60的第二芯片左侧壁60s1限定。
在间隙区域GP中可以存在未被第一热界面材料层70a和第二热界面材料层70b以及第二底部填充层42和第三底部填充层46占据的空白空间AG。第一热界面材料层70a和第二热界面材料层70b的物理特性(例如，热膨胀系数和弹性模量)可以与第二底部填充层42和第三底部填充层46不同。在制造半导体封装100的过程中，温度可能从室温改变到约200摄氏度。如果热界面材料层70a和70b在间隙区域GP中与第二底部填充层42和第三底部填充层46中的至少一个接触，则可能由于它们之间的物理特性的差异而发生应力，从而可能至少在第二底部填充层42和第三底部填充层46之一中出现裂纹。例如，可能在第二基板30与第二底部填充层42和第三底部填充层46中的至少一个之间的界面处出现裂纹。如果出现这种裂纹，则在后续测试半导体封装的过程中，裂纹程度可能由于快速的温度变化而增加，因此，第二内部连接端子40和第三内部连接端子44中的至少一个或一些可能与第二基板上部导电图案37分离，导致凸块断开现象。因此，为了防止这种情况，热界面材料层70a和70b在间隙区域GP中所占据的体积可以等于或小于间隙区域GP体积的10％。
根据实施例，形成在散热构件80中的沟槽TR的特定结构可以抑制/防止热界面材料层70a和70b进入间隙区域GP。因此，可以提高半导体封装100的可靠性。
图6是示出了制造具有图2截面的半导体封装的过程的截面图。
参照图6，可以制备第一封装基板10。第二基板30可以通过第一内部连接端子26接合到第一基板10上，第一内部连接端子26插入在第一基板10与第二基板30之间。第一底部填充层24可以形成在第一基板10和第二基板30之间。可以在第一基板10和第二基板30之间注入热固性或光固化树脂溶液，然后可以使树脂溶液硬化以形成第一底部填充层24。第一芯片结构50可以安装在第二基板30上，第二内部连接端子40插入在第一芯片结构50和第二基板30之间。第二底部填充层42可以形成在第一芯片结构50和第二基板30之间。可以在第二基板30与第一芯片结构50之间注入热固性或光固化树脂溶液，然后，可以使树脂溶液硬化以形成第二底部填充层42。第二芯片结构60可以安装在第二基板30上，第三内部连接端子44插入在第二芯片结构60和第二基板30之间。第三底部填充层46可以形成在第二芯片结构60和第二基板30之间。
可以制备包括空腔CV的散热构件80。沟槽TR可以形成在散热构件80的空腔CV中。可以使用例如激光钻孔工艺、铣削工艺、冲压工艺或化学蚀刻工艺来形成沟槽TR。、用于形成热界面材料层的树脂溶液70可以涂敷在第一芯片结构50和第二芯片结构60的顶表面50t和60t的每一个上，然后可以由具有沟槽TR的散热构件80覆盖。此后，可以通过例如夹具来挤压散热构件80。此时，可以按照沟槽TR与芯片结构50和60之间的间隙区域GP重叠的方式来定位散热构件80，例如，可以将沟槽TR和间隙区域GP的中心对准。可以在这种状态下施加约200摄氏度的热量以使树脂溶液硬化，从而可以形成图2的第一热界面材料层70a和第二热界面材料层70b。
参照图2、图3A和图6，可以通过挤压散热构件80将树脂溶液70朝向沟槽TR的沟槽侧壁TRs1和TRs2推出。散热构件80可以具有沟槽TR，沟槽TR具有上述结构和位置，因此间隙区域GP可以与沟槽侧壁TRs1和TRs2间隔开第四距离DS4和第五距离DS5。由此，被推出的树脂溶液70可以在进入间隙区域GP之前先进入沟槽TR。因此，第一热界面材料层70a和第二热界面材料层70b可以如图2和图3A那样形成。因此，可以防止上述裂纹现象，从而提高半导体封装100的可靠性和成品率。粘合层82可以与热界面材料层70a和70b同时形成。取决于树脂溶液的量和夹具的重量，沟槽TR中的第一热界面材料层70a和第二热界面材料层70b的形状可以如参照图3A至图4C所描述的那样改变。
图7是示出了根据一些实施例的半导体封装的截面图。
参照图7，在根据本实施例的半导体封装101中，第一芯片结构可以是第一子半导体封装150，并且第二芯片结构可以是第二子半导体封装160。第一子半导体封装150可以包括第一子封装基板151、通过配线152连接到第一子封装基板151的第一子半导体芯片153、以及覆盖第一子半导体芯片153的第一子模制层154。
第二子半导体封装160可以包括第二子半导体芯片162和顺序地堆叠在第二子半导体芯片162上的多个第三子半导体芯片164。例如，第二子半导体芯片162可以是逻辑管芯，并且第三子半导体芯片164可以是存储管芯(例如，DRAM管芯)。第二子半导体芯片162和第三子半导体芯片164可以在其中包括贯穿电极166。第三子半导体芯片164可以通过倒装芯片接合方法堆叠。第二子模制层165可以覆盖第三子半导体芯片164的侧壁和第二子半导体芯片162的顶表面。
例如，第一子模制层154和第二子模制层165可以包括绝缘树脂，例如，环氧模塑化合物(EMC)。第一子模制层154和第二子模制层165还可以包括填料，并且这些填料可以分散在绝缘树脂中。填料可以包括例如氧化硅(SiO2)。
第三子半导体芯片164中最上面一个的顶表面可以与第二子模制层165的顶表面共面。第二热界面材料层70b可以与最上面的第三子半导体芯片164直接接触。因此，从第三子半导体芯片164产生的热量可以通过第二热界面材料层70b迅速耗散或释放到外部。其他组件可以与参照图1至图5所描述的组件相同/相似。
图8是示出了根据一些实施例的半导体封装的平面图。图9是沿图8的线A-A’的截面图。
参照图8和图9，在根据本实施例的半导体封装102中，散热构件80’可以包括第一沟槽TR1、第二沟槽TR2和第三沟槽TR3。第一沟槽TR1可以与参照图1至图7描述的沟槽TR相同，并且可以与第一芯片结构50和第二芯片结构60之间的间隙区域GP重叠。第二沟槽TR2可以与第一芯片结构50的第一芯片左侧壁50s1重叠。第三沟槽TR3可以与第二芯片结构60的第二芯片右侧壁60sr重叠。第一沟槽TR1可以具有与图1的沟槽TR相同的形状。第二沟槽TR2可以具有沿第二方向Y延伸的条形状。第三沟槽TR3可以连接到第一沟槽TR1。
在图9中，散热构件80’在第一沟槽TR1和第二沟槽TR2之间的部分可以被称为第一散热内部突起80up1。另外，散热构件80’在第一沟槽TR1和第三沟槽TR3之间的部分可以被称为第二散热内部突起80up2。第一散热内部突起80up1可以在第一方向X上具有第一宽度W1。第二散热内部突起80up2可以在第一方向X上具有第二宽度W2。第一芯片结构50可以在第一方向X上具有第三宽度W3。第二芯片结构60可以在第一方向X上具有第四宽度W4。
第一宽度W1可以小于第三宽度W3。第二沟槽TR2的深度和宽度以及第二沟槽TR2与第一芯片结构50的第一芯片顶表面50t的重叠程度可以与参照图2至图5描述的沟槽TR相同/相似。因此，第一热界面材料层70a的一部分可以插入到第二沟槽TR2中。另外，第二宽度W2可以小于第四宽度W4。第三沟槽TR3的深度和宽度以及第三沟槽TR3与第二芯片结构60的第二芯片顶表面60t的重叠程度可以与参照图2至图5描述的沟槽TR相同/相似。因此，第二热界面材料层70b的一部分可以插入到第三沟槽TR3中。
图10是根据其他实施例的沿图8的线A-A’的截面图。
参照图10，在根据本实施例的半导体封装103中，散热构件80”可以具有图9的结构，并且还可以包括从外顶表面80bt向上突出的第一鳍部80f1和第二鳍部80f2。第一鳍部80f1可以与第二沟槽TR2重叠。第二沟槽TR2可以在第一方向X上具有第五宽度W5。第一鳍部80f1可以在第一方向X上具有第六宽度W6。第六宽度W6可以大于第五宽度W5。第二鳍部80f2可以与第一沟槽TR1和第三沟槽TR3两者重叠。当整体来看时，可以表示外顶表面80bt具有不平坦的形状。散热构件80”可以在与第一沟槽TR1间隔开的位置处具有第一厚度T1，并且可以在第一沟槽TR1上具有第二厚度T2。第二厚度T2可以等于第一厚度T1。因此，可以最小化/防止半导体封装103的翘曲现象，以提高半导体封装103的可靠性。另外，可以通过第一鳍部80f1和第二鳍部80f2增加散热构件80”的外顶表面80bt的表面积，因此可以改善散热效果。
图11是示出了根据一些实施例的半导体封装的平面图。沿图11的线A-A’截取的截面图可以与图9或图10的截面图相同/相似。
参照图11，在根据本实施例的半导体封装104中，沟槽TR可以与第一芯片结构50的整个圆周(或边缘)重叠。另外，沟槽TR可以与第二芯片结构60的整个圆周(或边缘)重叠。因此，第一散热内部突起80up1和第二散热内部突起80up2中的每一个可以具有孤立岛状的平面结构。其他结构和/或组件可以与参照图8至图10所描述的相同/相似。
图12是示出了根据一些实施例的半导体封装的截面图。
参照图12，根据本实施例的半导体封装105的散热构件80可以具有图2的结构，并且还可以包括从外侧壁80bs的下部向外突出的下侧突起80p。散热构件80可以具有例如帽子形状的截面。由于散热构件80包括下侧突起80p，因此可以增大第一基板10与散热构件80之间的粘合面，以提高第一基板10与散热构件80之间的粘合强度。其他组件可以与参照图1至图5所描述的相同/相似。
图13是示出了根据一些实施例的半导体封装的截面图。
参照图13，在根据本实施例的半导体封装106中，可以省略图2的第二基板30，并且可以通过插入在第一芯片结构50与第一基板10之间的第二内部连接端子40将第一芯片结构50直接安装在第一基板10上。另外，第二芯片结构60可以通过插入在第二芯片结构60和第一基板10之间的第三内部连接端子44直接安装在第一基板10上，而无第二基板30。其他结构和/或组件可以与参照图1至图5所描述的相同/相似。
图14是示出了根据一些实施例的半导体封装的平面图。图15是沿图14的线A-A’截取的截面图。
参照图14和图15，在根据本实施例的半导体封装107中，可以将两个第二芯片结构60设置为与第一芯片结构50的第一芯片右侧壁50sr相邻，并且可以将两个第二芯片结构60设置为与第一芯片结构50的第一芯片左侧壁50s1相邻。第一间隙区域GP1可以存在于第一芯片结构50的第一芯片右侧壁50sr和与之相邻的第二芯片结构60之间。第二间隙区域GP2可以存在于第一芯片结构50的第一芯片左侧壁50s1和与之相邻的第二芯片结构60之间。散热构件80”’可以具有与第一间隙区域GP1重叠的第一沟槽TR1和与第二间隙区域GP2重叠的第二沟槽TR2。第一沟槽TR1和第二沟槽TR2可以彼此间隔开并且可以具有对称的形状。第一沟槽TR1和第二沟槽TR2中每一个的结构可以与参照图1至图5描述的沟槽TR的结构相同/相似。
通过总结和回顾，实施例提供了一种具有改善的可靠性的半导体封装。即，根据实施例的半导体封装包括具有沟槽结构的散热构件，该沟槽结构抑制/防止热界面材料层进入芯片结构之间的间隙区域。因此，底部填充层和热界面材料层可以彼此间隔开，以防止由底部填充层和热界面材料层之间的物理特性的差异而引起的缺陷(例如，裂纹)。由此，可以提高半导体封装的可靠性。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅用于且应被解释为一般的描述性意义，而不是为了限制的目的。在一些情况下，如提交本申请的本领域普通技术人员应认识到，除非另有明确说明，否则结合特定实施例描述的特征、特性和/或元件可以单独使用或与其他实施例描述的特征、特性和/或元件相结合使用。因此，本领域技术人员将理解，在不脱离所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
第一基板；
在所述第一基板上彼此间隔开的第一芯片结构和第二芯片结构，在所述第一芯片结构和所述第二芯片结构之间限定有间隙区域；以及
覆盖所述第一芯片结构、所述第二芯片结构和所述第一基板的散热构件，所述散热构件在所述散热构件的内顶表面中包括第一沟槽，
其中，所述第一沟槽与所述间隙区域竖直地重叠，并具有比所述间隙区域的宽度大的宽度，并且
其中，所述第一沟槽与所述第一芯片结构的顶表面的一部分或所述第二芯片结构的顶表面的一部分中的至少一个竖直地重叠。
2.根据权利要求1所述的半导体封装，还包括：
在所述第一芯片结构和所述散热构件之间的第一热界面材料层，所述第一热界面材料层延伸以与所述第一沟槽的第一内侧壁接触；以及
在所述第二芯片结构和所述散热构件之间的第二热界面材料层，所述第二热界面材料层延伸以与所述第一沟槽的第二内侧壁接触，并且所述第一热界面材料层与所述第二热界面材料层间隔开。
3.根据权利要求2所述的半导体封装，其中，所述第一沟槽的内顶表面的至少一部分不与所述第一热界面材料层和所述第二热界面材料层接触，而是被暴露。
4.根据权利要求1所述的半导体封装，其中，所述散热构件在与所述第一沟槽间隔开的位置处具有第一厚度，所述第一沟槽距所述散热构件的内顶表面具有第一深度，并且所述第一深度在所述第一厚度的1/3至2/3的范围内。
5.根据权利要求1所述的半导体封装，其中，所述第一沟槽距所述散热构件的内顶表面具有第一深度，与所述第一沟槽重叠的所述第一芯片结构的顶表面具有比所述第一沟槽的第一深度小的第一宽度。
6.根据权利要求1所述的半导体封装，其中，所述第一沟槽包括：
第一沟槽侧壁；以及
入口部分，在所述入口部分处所述第一沟槽侧壁与所述散热构件的内顶表面相遇，所述入口部分的截面为直角的、圆形的或阶梯形的。
7.根据权利要求1所述的半导体封装，其中，当在平面图中观察时，所述散热构件包括三个圆角和一个具有刻面的刻面角。
8.根据权利要求1所述的半导体封装，其中：
所述第一芯片结构包括：
与所述第二芯片结构相邻的第一芯片侧壁，所述第一沟槽与所述第一芯片侧壁重叠，以及
与所述第一芯片侧壁相对的第二芯片侧壁，并且
所述散热构件还包括在所述散热构件的内顶表面中的第二沟槽，所述第二沟槽与所述第二芯片侧壁重叠。
9.根据权利要求8所述的半导体封装，其中：
所述散热构件包括在所述第一沟槽和所述第二沟槽之间的第一内部突起，所述第一内部突起在第一方向上具有第一宽度，并且
所述第一芯片结构在所述第一方向上具有第二宽度，所述第一宽度小于所述第二宽度。
10.根据权利要求1所述的半导体封装，其中，所述散热构件还包括从与所述内顶表面相对的外顶表面向上突出的第一鳍部，所述第一鳍部与所述第一沟槽重叠。
11.根据权利要求1所述的半导体封装，其中：
所述散热构件的外顶表面是不平坦的，
所述散热构件在与所述第一沟槽间隔开的位置处具有第一厚度，并且在所述第一沟槽上具有第二厚度，所述第一厚度等于所述第二厚度。
12.根据权利要求1所述的半导体封装，还包括：在所述第一芯片结构和所述第一基板之间并且在所述第二芯片结构和所述第一基板之间的第二基板，从所述散热构件的内侧壁到所述第二基板的第一距离小于从所述散热构件的内侧壁到所述第一芯片结构的第二距离。
13.一种半导体封装，包括：
封装基板；
中介层基板，在所述封装基板上；
所述中介层基板上的第一芯片结构和第二芯片结构，所述第一芯片结构和所述第二芯片结构通过之间的间隙区域彼此间隔开；以及
覆盖所述第一芯片结构、所述第二芯片结构、所述中介层基板和所述封装基板的散热构件，所述散热构件粘附到所述封装基板的顶表面；
其中，所述散热构件包括在所述散热构件的内顶表面中的第一沟槽，所述第一沟槽与所述间隙区域重叠并且具有比所述间隙区域的宽度大的宽度，
其中，所述第一沟槽与所述第一芯片结构的顶表面的一部分和所述第二芯片结构的顶表面的一部分中的至少一个竖直地重叠，并且
其中，所述散热构件在与所述第一沟槽间隔开的部分处具有第一厚度，并且所述第一沟槽的深度在所述第一厚度的1/3至2/3的范围内。
14.根据权利要求13所述的半导体封装，还包括：
在所述第一芯片结构和所述散热构件之间的第一热界面材料层，所述第一热界面材料层延伸以与所述第一沟槽的第一内侧壁接触；以及
在所述第二芯片结构和所述散热构件之间的第二热界面材料层，所述第二热界面材料层延伸以与所述第一沟槽的第二内侧壁接触，并且所述第一沟槽的内顶表面的至少一部分不与所述第一热界面材料层和所述第二热界面材料层接触，而是被暴露。
15.根据权利要求13所述的半导体封装，其中，与所述第一沟槽重叠的所述第一芯片结构的顶表面具有比所述第一沟槽的深度小的第一宽度。
16.根据权利要求13所述的半导体封装，其中，所述散热构件的外顶表面是不平坦的。
17.根据权利要求13所述的半导体封装，其中，当在平面图中观察时，所述散热构件包括三个圆角和一个具有刻面的刻面角。
18.一种半导体封装，包括：
第一基板；
在所述第一基板上彼此间隔开的第一芯片结构和第二芯片结构，在所述第一芯片结构和所述第二芯片结构之间限定有间隙区域；以及
覆盖所述第一芯片结构、所述第二芯片结构和所述第一基板的散热构件，所述散热构件包括第一沟槽，所述第一沟槽与所述间隙区域重叠并且具有比所述间隙区域的宽度大的宽度，
其中，所述散热构件包括三个第一外角和一个第二外角，所述第二外角的形状与所述第一外角的形状不同。
19.根据权利要求18所述的半导体封装，其中，所述第一芯片结构包括与所述第二芯片结构相邻的第一芯片侧壁和与所述第一芯片侧壁相对的第二芯片侧壁，所述第一沟槽与所述第一芯片侧壁重叠，并且所述散热构件还包括与所述第二芯片侧壁重叠的第二沟槽。
20.根据权利要求18所述的半导体封装，其中，所述散热构件还包括从所述散热构件的外顶表面向上突出并与所述第一沟槽重叠的第一鳍部。
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