CN113720477A

CN113720477A - Infrared detector mirror image element based on CMOS (complementary metal oxide semiconductor) process and infrared detector

Info

Publication number: CN113720477A
Application number: CN202110324051.XA
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2021-11-30
Anticipated expiration: 2041-03-26
Also published as: CN113720477B

Abstract

The present disclosure relates to an infrared detector mirror image element and an infrared detector based on CMOS process, the mirror image element includes: the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared above the CMOS measuring circuit system; the infrared conversion structure is electrically connected with the CMOS measuring circuit system through the columnar structure and the supporting base; the CMOS infrared sensing structure further comprises a closed release isolation layer positioned on the reflection layer, the material for forming the closed release isolation layer comprises at least one of amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, and the thickness of the closed release isolation layer is larger than or equal to 1 micrometer and smaller than or equal to 2 micrometers. Through the technical scheme, the problems of low performance, low pixel scale, low yield and the like of the traditional MEMS process infrared detector are solved.

Description

Infrared detector mirror image element based on CMOS (complementary metal oxide semiconductor) process and infrared detector

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an infrared detector mirror image pixel based on a CMOS (complementary metal oxide semiconductor) process and an infrared detector.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) the infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

The infrared detector has the working principle that infrared radiation signals are absorbed, the absorption of the infrared radiation signals causes the change of temperature, the change of the resistance value of the infrared detector is caused by the change of the temperature, and the size of the infrared radiation signals is detected by measuring the change of the resistance value. During the operation of the infrared detector, substrate noise, background noise, noise generated by self-heating, and the like may be introduced, which affects the accuracy of the detection result of the infrared detector.

In the prior art, a mirror image pixel is arranged in an infrared detector, and a noise signal of the infrared detector is acquired through the mirror image pixel, so that a detection signal after noise reduction is obtained, and the accuracy of a detection result is improved. However, a pixel structure capable of acquiring a noise signal is not disclosed at present.

Disclosure of Invention

In order to solve the technical problem or at least partially solve the technical problem, the disclosure provides an infrared detector mirror image pixel and an infrared detector.

In a first aspect, an embodiment of the present disclosure provides an infrared detector mirror image pixel based on a CMOS process, including:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared above the CMOS measuring circuit system;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the columnar structures are positioned on the CMOS measuring circuit system;

the CMOS infrared sensing structure further comprises at least one closed release isolation layer located on the reflection layer, the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of the CMOS infrared sensing structure, the closed release isolation layer covers the columnar structure, the material forming the closed release isolation layer comprises at least one of amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, and the thickness of the closed release isolation layer is larger than or equal to 1 micrometer and smaller than or equal to 2 micrometers.

Optionally, the infrared conversion structure includes an absorption plate and a plurality of beam structures, the absorption plate is used for converting an infrared signal into an electrical signal and is electrically connected with the corresponding columnar structure through the corresponding beam structure;

the absorber plate and the beam structure are located in the same layer or in different layers.

Optionally, the absorber plate and the beam structure are located in different layers, the beam structure comprising a first electrode layer, the absorber plate comprising a second electrode layer and a heat sensitive layer, the second electrode layer being electrically connected to the columnar structure through the first electrode layer.

Optionally, the beam structures are respectively connected to a middle support structure and the columnar structure, and in the beam structures, two parallel beam structures meeting at the same node in a beam path from the middle support structure to the corresponding columnar structure are respectively a first half-bridge structure and a second half-bridge structure, and the first half-bridge structure and the second half-bridge structure form a thermally symmetric structure; wherein the length of the first half-bridge structure is greater than the length of the second half-bridge structure, and the thickness of the first half-bridge structure is greater than the thickness of the second half-bridge structure in a direction perpendicular to the CMOS measurement circuitry.

Optionally, the CMOS infrared sensing structure further includes: and the surface of the flat layer, which is far away from the CMOS measuring circuit system, is flush with the surface of the reflection layer, which is far away from the CMOS measuring circuit system, by adopting a CMP process.

Optionally, the columnar structure includes a plurality of independent columnar structures, the independent columnar structures are located on different layers, and the independent columnar structures are arranged corresponding to one or more layers of the closed release insulation layer.

Optionally, the reflector plate is in electrical contact with the grounded support base.

Optionally, a material constituting the sacrificial layer in the mirror image element includes silicon oxide.

Optionally, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, and the sacrificial layer is etched by using at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane.

Optionally, the side length of the supporting base is less than or equal to 3 micrometers and greater than or equal to 0.5 micrometer.

In a second aspect, embodiments of the present disclosure provide an infrared detector based on a CMOS process, which includes a plurality of mirror image pixels of any one of the infrared detectors based on a CMOS process as provided in the first aspect.

Compared with the prior art, the technical scheme provided by the disclosure has the following advantages:

(1) the CMOS infrared sensing structure comprises at least one layer of closed release isolation layer positioned on a reflecting layer, the closed release isolation layer is used for protecting a CMOS measuring circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure, the closed release isolation layer coats a columnar structure, the material forming the closed release isolation layer comprises at least one of amorphous carbon, silicon carbide, aluminum oxide or silicon nitride, the thickness of the closed release isolation layer is more than or equal to 1 micrometer and less than or equal to 2 micrometers, so that a resonant cavity formed between a reflecting plate and an infrared conversion structure does not meet the resonance condition of infrared light any more, resonant light cannot be generated in the resonant cavity, at the moment, an electric signal generated by the infrared conversion structure is originated from temperature noise, therefore, a noise signal of the infrared detector can be acquired through a mirror image element, and a more accurate detection signal can be acquired accordingly, thereby improving the accuracy of the detection result. In addition, the closed release isolation layer is positioned in the resonant cavity, so that the thickness of the sacrificial layer can be reduced, and the difficulty of release of the sacrificial layer is reduced; meanwhile, the airtight release isolation layer is used as a supporting structure of the columnar structure, the mechanical strength of the columnar structure can be improved, and therefore the structural stability and the impact resistance of the infrared detector are improved.

(2) The embodiment of the invention realizes the integrated preparation of the CMOS measuring circuit system and the CMOS infrared sensing structure on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS has no process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the problems of transportation and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective view of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a three-dimensional decomposition structure of an infrared detector mirror image pixel based on a CMOS process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 5 is a schematic perspective view of another imaging pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 6 is a schematic perspective view of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a CMOS measurement circuitry according to an embodiment of the present invention;

fig. 8 is a schematic perspective exploded view of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

fig. 9 is a schematic perspective exploded view of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

fig. 10 is a schematic perspective exploded view of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

fig. 11 is a schematic perspective exploded view of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

fig. 12 is a schematic perspective exploded view of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a beam structure according to an embodiment of the present invention;

fig. 14 is a schematic perspective view of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

fig. 15 is a schematic perspective view of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

fig. 17 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention;

FIG. 18 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to an embodiment of the present invention;

FIG. 20 is a schematic structural diagram of a reflective layer according to an embodiment of the present invention;

fig. 21 is a schematic perspective view of an infrared detector based on a CMOS process according to an embodiment of the present invention.

Detailed Description

In order that the above objects, features and advantages of the present invention may be more clearly understood, a solution of the present invention will be further described below. It should be noted that the embodiments of the present invention and features of the embodiments may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein; it is to be understood that the embodiments described in this specification are only some embodiments of the invention, and not all embodiments.

Fig. 1 is a schematic diagram of a three-dimensional structure of an infrared detector mirror image element based on a CMOS process according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a three-dimensional exploded structure of an infrared detector mirror image element based on a CMOS process according to an embodiment of the present invention, and as shown in fig. 1 and fig. 2, an infrared detector mirror image element 100 based on a CMOS process includes a CMOS measurement circuit system 101 and a CMOS infrared sensing structure, both the CMOS measurement circuit system 101 and the CMOS infrared sensing structure are manufactured by using a CMOS process, and the CMOS infrared sensing structure is directly manufactured on the CMOS measurement circuit system 101.

Specifically, the CMOS infrared sensing structure is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 101, and the CMOS measurement circuit system 101 reflects temperature information corresponding to the infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measuring circuit system 101 and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system 101, namely, the CMOS measuring circuit system 101 is prepared by adopting the CMOS process, and then the CMOS infrared sensing structure is continuously prepared by utilizing the CMOS process by utilizing the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS process is utilized to realize the integrated preparation of the CMOS measuring circuit system 101 and the CMOS infrared sensing structure on the CMOS production line, compared with the MEMS process, the CMOS process has no process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

With reference to fig. 1 and fig. 2, the CMOS infrared sensing structure includes a reflective layer 110, an infrared conversion structure 120, and a plurality of pillar structures 130 on the CMOS measurement circuitry 101, the pillar structures 130 are located between the reflective layer 110 and the infrared conversion structure 120, the reflective layer 110 includes a reflective plate 112 and a supporting base 111, and the infrared conversion structure 120 is electrically connected to the CMOS measurement circuitry 101 through the pillar structures 130 and the supporting base 111.

Specifically, the pillar structure 130 is located between the reflective layer 110 and the infrared conversion structure 120, and is configured to support the infrared conversion structure 120 after a sacrificial layer on the CMOS measurement circuit system 101 is released, the sacrificial layer is located between the reflective layer 110 and the infrared conversion structure 120, the pillar structure 130 is a metal structure, an electrical signal converted by an infrared signal of the infrared conversion structure 120 is transmitted to the CMOS measurement circuit system 101 through the corresponding pillar structure 130 and the corresponding support base 111, and the CMOS measurement circuit system 101 processes the electrical signal to reflect temperature information, thereby implementing non-contact infrared temperature detection of the infrared detector. The CMOS infrared sensing structure 102 outputs a positive electrical signal and a ground electrical signal through different electrode structures, and the positive electrical signal and the ground electrical signal are transmitted to the supporting base 111 electrically connected to the columnar structures 130 through different columnar structures 130, fig. 1 and 2 schematically illustrate the direction parallel to the CMOS measurement circuit system 101, the CMOS infrared sensing structure includes four columnar structures 130, two of the columnar structures 130 may be configured to transmit the positive electrical signal, the other two columnar structures 130 are configured to transmit the ground electrical signal, and the CMOS infrared sensing structure may also include two columnar structures 130 configured to transmit the positive electrical signal and the ground electrical signal, respectively. In addition, the reflective layer 110 includes a reflective plate 112 and a supporting base 111, a portion of the reflective layer 110 is used as a dielectric for electrically connecting the pillar structure 130 with the CMOS measurement circuitry 101, i.e., the supporting base 111, and the reflective plate 112 is used for reflecting the infrared rays to the infrared conversion structure 120, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflective layer 110 and the infrared conversion structure 120, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

With reference to fig. 1 and fig. 2, the CMOS infrared sensing structure further includes at least one hermetic release insulating layer 140 located on the reflective layer 110, the hermetic release insulating layer 140 is used for protecting the CMOS measurement circuit system 101 from process influence during an etching process for manufacturing the CMOS infrared sensing structure, the hermetic release insulating layer 140 covers the columnar structure 130, a material constituting the hermetic release insulating layer 140 includes at least one of amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, and a thickness of the hermetic release insulating layer 140 is greater than or equal to 1 micron and less than or equal to 2 microns.

Illustratively, the CMOS infrared sensing structure includes at least one hermetic release isolation layer 140 on the reflection layer 110, the support base 111 is used as a structure for electrically connecting the readout circuit and the CMOS infrared sensing structure 102, and the hermetic release isolation layer 140 covers the dielectric layer under the hermetic release isolation layer 140 and the support base 111, and plays a role in protecting the dielectric layer under and the CMOS measurement circuitry. Meanwhile, the airtight release insulating layer 140 covers the columnar structure 130, and can serve as a supporting structure of the columnar structure 130, so that the mechanical strength of the columnar structure 130 is enhanced, the structural stability of the mirror image pixel 100 is improved, and the structural stability and the impact resistance of the infrared detector can be improved.

Fig. 3 is a schematic diagram of a film structure of an infrared detector mirror image pixel based on a CMOS process according to an embodiment of the present invention, where the hermetic release insulating layer 140 may also be located at an interface between the CMOS measurement circuitry 101 and the CMOS infrared sensing structure 102, for example, the hermetic release insulating layer 140 is located between the reflective layer 110 and the CMOS measurement circuitry 101, that is, the hermetic release insulating layer 140 is located below a metal interconnection layer of the reflective layer 110, and the supporting base 111 is electrically connected to the CMOS measurement circuitry 101 through a through hole penetrating through the hermetic release insulating layer 140. Specifically, since the CMOS measurement circuit system 101 and the CMOS infrared sensing structure 102 are both formed by using a CMOS process, after the CMOS measurement circuit system 101 is formed, a wafer including the CMOS measurement circuit system 101 is transferred to a next process to form the CMOS infrared sensing structure 102, and since silicon oxide is a most commonly used dielectric material in the CMOS process and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, so that a hermetic release insulating layer 140 is provided to release the silicon oxide on the sacrificial layer without corroding the silicon oxide on the CMOS measurement circuit system. After the CMOS measurement circuit system 101 is prepared and formed, a closed release isolation layer 140 is prepared and formed on the CMOS measurement circuit system 101, the CMOS measurement circuit system 101 is protected by the closed release isolation layer 140, and in order to ensure the electrical connection between the support base 111 and the CMOS measurement circuit system 101, after the closed release isolation layer 140 is prepared and formed, a through hole is formed in a region of the closed release isolation layer 140 corresponding to the support base 111 by using an etching process, and the support base 111 is electrically connected with the CMOS measurement circuit system 101 through the through hole. In addition, the hermetic release isolation layer 140 and the support base 111 are arranged to form a hermetic structure, so as to completely separate the CMOS measurement circuit system 101 from the sacrificial layer, thereby protecting the CMOS measurement circuit system 101.

Fig. 4 is a schematic diagram of a film structure of another infrared detector mirror image pixel based on a CMOS process according to an embodiment of the present invention, an interface between the CMOS measurement circuit system 101 and the CMOS infrared sensing structure 102 is provided with at least one closed release isolation layer 140, that is, at least one closed release isolation layer 140 is provided between the reflection layer 110 and the CMOS measurement circuit system 101, and at least one closed release isolation layer 140 is provided on the reflection layer 110, which has the same effects as above and is not described herein again.

The hermetic release isolation layer 140, which may be made of at least one material of amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, is located on a side of the reflection layer 110 away from the CMOS measurement circuitry 101, and covers the reflection layer 110. The refractive index of the amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride material is greater than that of vacuum, the optical path in the resonant cavity is changed by the closed release insulating layer 140, and meanwhile, the thickness of the closed release insulating layer 140 is set to be greater than or equal to 1 micrometer and less than or equal to 2 micrometers, so that the condition that the resonant cavity generates resonance is destroyed, that is, the resonant cavity is not formed between the CMOS measurement circuit system 101 and the infrared conversion structure 120.

In addition, amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride and silicon nitride are all commonly used corrosion resistant materials for CMOS processes, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 140 can be used to protect the CMOS measurement circuitry 101 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer 140 covers the CMOS measurement circuit system 101, and the closed release isolation layer 140 can also be used for protecting the CMOS measurement circuit system 101 from process influence during an etching process for manufacturing a CMOS infrared sensing structure.

The infrared conversion structure 120 can absorb infrared radiation energy of a target object and convert a temperature signal into an electrical signal, and since no resonant light is generated between the reflective layer 110 and the infrared conversion structure 120, the infrared conversion structure 120 can absorb little infrared radiation energy, and it can be considered that the infrared conversion structure 120 does not respond to the infrared radiation signal. At this time, the electrical signal generated by the infrared conversion structure 120 is originated from temperature noise such as thermal radiation of the CMOS measurement circuit system 101 and thermal radiation of the external environment, that is, the signal generated by the infrared conversion structure 120 is a noise signal, and the electrical signal generated by the image element is a noise signal, so that the noise signal of the infrared detector can be acquired by the image element.

The infrared detector comprises an effective pixel and a mirror image pixel, wherein the effective pixel and the mirror image pixel are changed in resistance value due to heat radiation, when the mirror image pixel and the effective pixel are subjected to the same fixed radiation, the resistance values of the mirror image pixel and the effective pixel are the same, the temperature coefficients of the mirror image pixel and the effective pixel are also the same, the temperature drift amounts of the mirror image pixel and the effective pixel are the same under the same environment temperature, and the change of the mirror image pixel and the effective pixel is synchronous. Therefore, the difference between the image element and the effective element is that the image element does not respond to the infrared radiation signal, and the effective element responds to the infrared radiation signal, that is, the signal generated by the effective element is the superposition of the infrared radiation signal and the noise signal, and after the noise of the signal generated by the effective element is reduced, the infrared radiation signal of the target object can be obtained, so that the accuracy of the detection result is improved.

For a detector full CMOS process, a closed release isolation layer can be formed in both the effective pixel and the mirror image pixel by using the same process. For the effective pixel, the closed release isolation layer 140 is located in the resonant cavity, and the refractive index of the closed release isolation layer 140 is greater than that of vacuum, so that the optical path of the resonant cavity can be increased through the closed release isolation layer 140, the actual height of the resonant cavity can be reduced, the thickness of the sacrificial layer is reduced, and the release difficulty of the sacrificial layer is reduced.

In summary, in the embodiment of the present invention, the CMOS infrared sensing structure includes at least one closed release isolation layer located on the reflection layer, the closed release isolation layer is used to protect the CMOS measurement circuit system from process influence during the etching process for manufacturing the CMOS infrared sensing structure, the closed release isolation layer covers the columnar structure, the material forming the closed release isolation layer includes at least one of amorphous carbon, silicon carbide, aluminum oxide or silicon nitride, the thickness of the closed release isolation layer is greater than or equal to 1 micrometer and less than or equal to 2 micrometers, so that the resonant cavity formed between the reflection plate and the infrared conversion structure no longer satisfies the resonance condition of infrared light, and therefore no resonant light is generated in the resonant cavity, at this time, the electrical signal generated by the infrared conversion structure is derived from temperature noise, and therefore, the noise signal of the infrared detector can be obtained by the mirror image element, and accordingly a more accurate detection signal can be obtained, thereby improving the accuracy of the detection result. In addition, the closed release isolation layer is positioned in the resonant cavity, so that the thickness of the sacrificial layer can be reduced, and the difficulty of release of the sacrificial layer is reduced; meanwhile, the airtight release isolation layer is used as a supporting structure of the columnar structure, the mechanical strength of the columnar structure can be improved, and therefore the structural stability and the impact resistance of the infrared detector are improved.

The CMOS fabrication process of the CMOS infrared sensing structure 102 includes a metal interconnection process, a via process, and an RDL process, and the CMOS infrared sensing structure 102 includes at least two metal interconnection layers, at least two dielectric layers, and a plurality of interconnection vias. The dielectric layer at least comprises a sacrificial layer and a heat sensitive dielectric layer, the heat sensitive dielectric layer at least comprises a heat sensitive layer, a supporting layer and/or a passivation layer, and the metal interconnection layer at least comprises a reflecting layer 110 and an electrode layer; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and then an infrared target signal is converted into a signal capable of being read electrically through the CMOS measurement circuit system 101.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a redistribution layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the reflection layer 110 in the infrared detector can be prepared on the top metal of the CMOS measurement circuit system 101 by adopting the RDL process, and the support base 111 on the reflection layer 110 is electrically connected with the top metal of the CMOS measurement circuit system 101. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

In addition, the CMOS manufacturing process of the CMOS measurement circuit system 101 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 101 includes metal interconnection layers arranged at intervals, a dielectric layer, and a silicon substrate located at the bottom, and the upper and lower metal interconnection layers are electrically connected through vias.

It should be noted that the infrared conversion structure 120 may be a single-layer structure, and the infrared conversion structure 120 is electrically connected to the CMOS measurement circuitry 101 sequentially through the pillar structure 130 and the supporting base 111, as shown in fig. 1 and fig. 2. In other embodiments, the infrared conversion structure 120 may also be a double-layer structure, and the pillar structure 130 is located between the structure near the side of the CMOS measurement circuitry 101 and the reflective layer 110 in the double-layer structure, as shown in fig. 5.

In addition, fig. 5 only illustrates that the CMOS infrared sensing structure includes a hermetic release isolation layer 140, and a single hermetic release isolation layer requires a smaller number of process steps, which is beneficial to saving process time, thereby improving the production efficiency of the infrared detector. In other embodiments, the CMOS infrared sensing structure may further include two closed release isolation layers 140 as shown in fig. 6, or more closed release isolation layers 140, where in the multi-layer closed release isolation layer structure, the thickness of each closed release isolation layer is smaller, and the thickness of the film layer is easier to control in the process, thereby reducing the process difficulty. In practical applications, the number of the hermetic release insulating layers 140 is set according to specific requirements, which is not specifically limited in the embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present invention. With reference to fig. 1 to 7, the CMOS measurement circuit system 101 includes a bias voltage generation circuit 7, a column-level analog front-end circuit 8 and a row-level circuit 9, an input end of the bias voltage generation circuit 7 is connected to an output end of the row-level circuit 9, an input end of the column-level analog front-end circuit 8 is connected to an output end of the bias voltage generation circuit 7, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 8 includes a blind image element RD; the row-level circuit 9 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit 8 under the action of the bias generating circuit 7 to perform current-voltage conversion output; the row stage circuit 9 outputs a third bias voltage VRsm to the bias generation circuit 7 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 7 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 8 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on the difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 9 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a light-shielding process such that the row-level image elements Rsm are subjected to a fixed radiation by a light-shielding sheet having a temperature constantly equal to a substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 7, that is, the row-level circuit 9 outputs the third bias voltage VRsm to the bias generation circuit 7 when being gated by the row selection switch K1. The bias generation circuit 7 may include a first bias generation circuit 71 and a second bias generation circuit 72, the first bias generation circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 8 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed in correspondence with the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed in one-to-one correspondence with the gate driving sub-circuits 722, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 8 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value of the first current I1 and the second current I2, and outputting the difference value, and the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 101 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade having a temperature that is constantly equal to the substrate temperature. The absorption plate 121 of the effective pixel RS is thermally insulated from the CMOS measurement circuitry 101, and the effective pixel RS receives external radiation. The absorbing plates 121 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measurement circuitry 101, and thus both the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated through the row selection switch K1, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective element RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective element RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective element RS are the same at the same ambient temperature, the change of the row-level mirror image element Rsm and the temperature drift amounts of the effective element RS at the same ambient temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective element RS due to the self-heating effect is effectively compensated, and the stable output of the reading circuit is achieved.

In addition, by arranging the second bias generating circuit 7 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2 respectively according to the row control signals, so that each row of pixels has one path to drive the whole columns of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 7 is improved, and the readout circuit is advantageously used to drive a larger-scale infrared detector pixel array. In addition, the specific details of the CMOS measurement circuitry 101 are well known to those skilled in the art and will not be described herein.

Alternatively, with continued reference to fig. 1, 5, and 6, the infrared conversion structure 120 includes an absorbing plate 121 and a plurality of beam structures 122, the absorbing plate 121 for converting an infrared signal into an electrical signal and electrically connecting with the corresponding pillar structures 130 through the corresponding beam structures 122.

The absorber plate 121 and the beam structure 122 are located at the same layer or at different layers.

Specifically, as shown in fig. 1, 5, and 6, the infrared conversion structure 120 includes a plurality of beam structures 122, and each beam structure 122 is electrically connected to a corresponding pillar structure 130. The absorption plate 121 serves to absorb infrared radiation energy of a target object and convert the infrared radiation energy into an effective electrical signal, and the beam structure 122 transfers the effective electrical signal generated by the absorption plate 121 to a readout circuit through the pillar structure 130, while the beam structure 122 is also a thermally conductive member for heat dissipation. In addition, the absorption plate 121 is also used for absorbing energy of temperature noise radiation and converting the energy of the temperature noise radiation into a noise signal, and the beam structure 122 transfers the noise electrical signal generated by the absorption plate 121 to a readout circuit through the pillar structure 130 to realize detection of the noise signal of the infrared detector.

It should be noted that fig. 1-6 only exemplarily show that the infrared conversion structure 120 includes two beam structures 122, and in practical applications, the number of beam structures 122 is not particularly limited.

In addition, the absorption plate 121 and the beam structure 122 may be located at the same layer as shown in fig. 1, 2, and 6; the absorber plates 121 and the beam structures 122 may also be located in different layers as shown in fig. 5, both of which are described in detail below.

Alternatively, with continued reference to fig. 1 and 2, the absorber plates 121 and the beam structures 122 may be located at the same layer.

Illustratively, as shown in conjunction with fig. 1 and 2, beam structure 122 includes a support layer 210, an electrode layer 220, and a passivation layer 230, and absorbent sheet 121 includes a support layer 210, an electrode layer 220, a passivation layer 230, and a heat sensitive layer 240. The electrode layer 220 is positioned on the support layer 210, the heat sensitive layer 240 is positioned on the electrode layer 220, and the passivation layer 230 is positioned on the heat sensitive layer 240.

Specifically, the supporting layer 210 is configured to support an upper film layer in the infrared conversion structure 120 after the sacrificial layer is released, the thermosensitive layer 240 is configured to convert an infrared temperature detection signal into an infrared detection electrical signal, the electrode layer 220 is configured to transmit the infrared detection electrical signal converted by the thermosensitive layer 240 to the CMOS measurement circuit system 101 through the beam structures 122 on the left and right sides, the beam structures 122 on the left and right sides transmit positive and negative signals of the infrared detection electrical signal respectively, a readout circuit in the CMOS measurement circuit system 101 implements non-contact infrared temperature detection by analyzing the acquired infrared detection electrical signal, and the passivation layer 230 is configured to protect the electrode layer 220 from oxidation or corrosion. The thermosensitive layer 240 may be located above the electrode layer 220, or may be located below the electrode layer 220. The corresponding absorption plate 121 may be disposed, the thermosensitive layer 240 and the electrode layer 220 are located in a sealed space formed by the supporting layer 210 and the passivation layer 230 to protect the thermosensitive layer 240 and the electrode layer 220 in the absorption plate 121, and the electrode layer 220 is located in a sealed space formed by the supporting layer 210 and the passivation layer 230 to protect the electrode layer 220 in the beam structure 122 corresponding to the beam structure 122.

For example, the material constituting the heat sensitive layer 240 may include at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide, the material constituting the support layer 210 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium, the material constituting the electrode layer 220 may include one or more of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-silicon alloy, nickel, or chromium, and the material constituting the passivation layer 230 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium. In addition, when the absorber plate 121 is disposed to include the thermal sensitive layer 240, and the thermal sensitive layer 240 is made of amorphous silicon, amorphous carbon, amorphous germanium or amorphous silicon germanium, the supporting layer 210 and/or the passivation layer 230 on the beam structure 122 may be replaced by the thermal sensitive layer 240, because the thermal conductivity of the amorphous silicon, amorphous germanium or amorphous silicon germanium is relatively small, which is beneficial to reducing the thermal conductivity of the beam structure 122, and further improving the infrared responsivity of the infrared detector.

It should be noted that fig. 2 is only exemplary to arrange the electrode layer 220 on the side of the thermosensitive layer 240 adjacent to the CMOS measurement circuitry 101. In other embodiments, the electrode layer 220 may be disposed on a side of the thermosensitive layer 240 adjacent to the passivation layer 230, and a dielectric layer is disposed between the electrode layer 220 and the thermosensitive layer 240, as shown in fig. 8.

In the embodiment of the invention, the absorption plate 121 and the beam structure 122 are arranged on the same layer, so that no mask plate is required to be respectively manufactured on the absorption plate 121 and the beam structure 122, the number of manufacturing processes is reduced, the production cost of the infrared detector can be saved, and the production efficiency is improved.

Optionally, fig. 9 is a schematic perspective exploded view of a further infrared detector mirror image pixel based on a CMOS process according to an embodiment of the present invention, and fig. 10 is a schematic perspective exploded view of a further infrared detector mirror image pixel based on a CMOS process according to an embodiment of the present invention, with reference to fig. 5, 9 and 10, the absorption plate 121 and the beam structure 122 may also be located at different layers, the beam structure 122 includes a first electrode layer 221, the absorption plate 121 includes a second electrode layer 222 and a thermal sensitive layer 240, and the second electrode layer 222 is electrically connected to the pillar structure 130 through the first electrode layer 221.

Illustratively, as shown in fig. 5, 9 and 10, the beam structure 122 includes a first support layer 211, a first electrode layer 221 and a first passivation layer 231, the first electrode layer 221 is located on the first support layer 211, the first support layer 211 is adjacent to the CMOS measurement circuitry 101, the first passivation layer 231 is located on the first electrode layer 221, and the first support layer 211 functions as a structural support. An absorber plate 121 is located on a side of the beam structure 122 facing away from the CMOS measurement circuitry 101, the absorber plate 121 comprising: a second support layer 212, a second electrode layer 222, a second passivation layer 232, and a thermally sensitive layer 240, the second electrode layer 222 being on the second support layer 212, the second support layer 212 being adjacent to a side of the beam structure 122, the second passivation layer 232 being on the thermally sensitive layer 240, the second support layer 212 serving as a structural support. The second support layer 212 is provided with a through hole 250, and the second electrode layer 222 and the first electrode layer 221 are electrically connected through the through hole 250.

Specifically, as shown in fig. 9 and 10, the first electrode layer 221 includes a first electrode 221a and a second electrode 221b, the second electrode layer 222 includes a third electrode 222a and a fourth electrode 222b, the middle of the second support layer 212 is hollowed to form a through hole 250, the third electrode 222a is electrically connected to the first electrode 221a through the through hole 250, and the fourth electrode 222b is electrically connected to the second electrode 221b through the through hole 250. The third electrode 222a transmits the generated positive thermosensitive signal of the thermosensitive layer 240 to the first electrode 221a, the first electrode 221a transmits the positive thermosensitive signal to the readout circuit through the corresponding columnar structure 130, the fourth electrode 222b transmits the generated negative thermosensitive signal of the thermosensitive layer 240 to the second electrode 221b, and the second electrode 221b transmits the negative thermosensitive signal to the readout circuit through the corresponding columnar structure 130, so as to realize the detection function of the noise signal.

It should be noted that fig. 10 is only exemplary to arrange the second electrode layer 222 on the side of the thermosensitive layer 240 adjacent to the CMOS measurement circuitry 101. In other embodiments, the second electrode layer 222 may also be disposed on a side of the thermal sensitive layer 240 adjacent to the second passivation layer 232, a dielectric layer is further disposed between the second electrode layer 222 and the thermal sensitive layer 240, and the dielectric layer, the thermal sensitive layer 240 and the second support layer 212 are hollowed out to form a through hole 250 penetrating through the dielectric layer, the thermal sensitive layer 240 and the second support layer 212, as shown in fig. 11. It should be noted that the through hole 250 may be a through hole as shown in fig. 10 and 11, or may be two through holes as shown in fig. 12.

According to the embodiment of the invention, the absorption plate 121 and the beam structure 122 are arranged on different layers, so that the area of the beam structure 122 does not affect the area of the absorption plate 121, and the absorption plate 121 with a larger area is favorably realized, and thus the radiant quantity of temperature noise absorbed by the absorption plate 121 can be increased, that is, the radiant quantity of the infrared detector can be increased, more accurate noise signals can be obtained, and the detection performance of the infrared detector can be favorably improved. In addition, the size of the infrared detector mirror image element 100 is no longer limited by the sum of the area of the absorption plate 121 and the area of the beam structure 122, so that the size of the infrared detector mirror image element 100 can be reduced, which is beneficial to the development of miniaturization of the infrared detector.

Optionally, fig. 13 is a schematic structural diagram of a beam structure according to an embodiment of the present invention, as shown in fig. 13, the beam structure 122 is respectively connected to the intermediate support structure 150 and the pillar structure 130, two parallel beam structures 122 meeting at the same node in a beam path from the intermediate support structure 150 to the corresponding pillar structure 130 in the plurality of beam structures 122 are respectively a first half-bridge structure 1221 and a second half-bridge structure 1222, and the first half-bridge structure 1221 and the second half-bridge structure 1222 form a thermally symmetric structure. Wherein the length of the first half-bridge structure 1221 is greater than the length of the second half-bridge structure 1222, and the thickness of the first half-bridge structure 1221 is greater than the thickness 1222 of the second half-bridge structure in a direction perpendicular to the CMOS measurement circuitry 101.

Specifically, when the absorption plate 121 and the beam structure 122 are located on different layers, the absorption plate 121 is located on the side of the beam structure 122 adjacent to the CMOS measurement circuitry 101, and an intermediate support structure 150 is disposed on the same layer as the beam structure 122 for supporting the beam structure 122 and maintaining the stability of the beam structure 122. The intermediate support structure 150 is fabricated using the same process flow as the beam structure 122, i.e., the intermediate support structure 150 includes a first electrode layer.

Illustratively, as shown in fig. 13, a parallel beam structure a and a parallel beam structure B meet at the same node a, a parallel beam structure C and a parallel beam structure D meet at a node B and a node C, and a parallel beam structure e and a parallel beam structure f meet at the same node D. In addition, the length of the first half-bridge structure 1221 in the thermally symmetric structure is greater than that of the second half-bridge structure 1222, so that the parallel beam structure a is the first half-bridge structure 1221, the parallel beam structure b is the second half-bridge structure 1222 and constitutes a thermally symmetric structure, the parallel beam structure c is the first half-bridge structure 1221, the parallel beam structure d is the second half-bridge structure 1222 and constitutes a thermally symmetric structure, the parallel beam structure e is the first half-bridge structure 1221, and the parallel beam structure f is the second half-bridge structure 1222 and constitutes a thermally symmetric structure.

The thickness of the first half-bridge structure 1221 is greater than the thickness of the second half-bridge structure 1222, and in the case that the first half-bridge structure 1221 and the second half-bridge structure 1222 are equal in length, the first half-bridge structure 1221 has a greater thickness, and therefore conducts heat faster than the second half-bridge structure 1222. The length of the first half-bridge structure 1221 and the length of the second half-bridge structure 1222 are asymmetrically designed, that is, the length of the first half-bridge structure 1221 is set to be greater than the length of the second half-bridge structure 1222, so as to slow down the heat conduction speed of the first half-bridge structure 1221 with a faster heat conduction speed due to a thickness factor, and further achieve that the difference between the heat conduction imbalance of the first half-bridge structure 1221 and the second half-bridge structure 1222 in the thermally symmetric structure is less than or equal to a set value, which may be 20%, for example, the difference between the heat conduction speeds of the first half-bridge structure 1221 and the second half-bridge structure 1222 in the thermally symmetric structure is less than or equal to 20%, for example, the heat conduction speed of the first half-bridge structure 1221 is 1, and the heat conduction speed of the second half-bridge structure 1222 is greater than or equal to 0.8 and less than or equal to 1.2.

With reference to fig. 1 to 13, the thermal conductivities of the parallel beam structure a and the parallel beam structure b are similar, the thermal conductivities of the parallel beam structure c and the parallel beam structure d are similar, the thermal conductivities of the parallel beam structure e and the parallel beam structure f are similar, the heat of the absorption plate 121 is transmitted to the parallel beam structure c and the parallel beam structure d substantially synchronously after passing through the parallel beam structure a and the parallel beam structure b, the heat is transmitted to the parallel beam structure e and the parallel beam structure f substantially synchronously after passing through the parallel beam structure e and the parallel beam structure f, the heat is transmitted to the upper column structure 130 and the lower column structure 130 substantially synchronously after passing through the parallel beam structure e and the parallel beam structure f, and the heat is dissipated by the CMOS measurement circuit system 101.

Thus, the time for the heat to reach the lower columnar structure 130 through the first half-bridge structure 1221 and the time for the heat to reach the upper columnar structure 130 through the second half-bridge structure 1222 are close by the absorption plate 121, thereby realizing the thermal balance on the beam structure 122, reducing the total thermal conductance of the image pixel 100 of the infrared detector, and optimizing the total thermal conductance of the infrared detector, such as the infrared detection performance of the infrared focal plane detector, so that the Noise Equivalent Temperature Difference (NETD) performance of the infrared detector is improved by more than 15%.

In addition, this disclosed embodiment sets up the great length of first half-bridge structure 1221 of thickness, be greater than the length of the less second half-bridge structure 1222 of thickness, compare in the identical symmetrical structure of length of first half-bridge structure 1221 and second half-bridge structure 1222, reduced the stress and the deformation that infrared detector mirror image pixel 100 received under the effect of the same power, under the same effort, the stress that infrared detector mirror image pixel 100 received reduces at least 10%, deformation reduces at least 50%, the stability and the shock resistance of infrared detector mirror image pixel 100 have been improved, and then whole infrared detector's structural stability has been improved, the mechanical strength of infrared detector has been strengthened.

It should be noted that fig. 1-13 only exemplarily set up that infrared detector mirror image pixel 100 includes three thermally symmetric structures formed by three first half-bridge structures 1221 and three second half-bridge structures 1222, and the specific number of thermally symmetric structures included in infrared detector mirror image pixel 100 is not limited in the embodiments of the present disclosure, so that it is sufficient to ensure that infrared detector mirror image pixel 100 includes at least one thermally symmetric structure.

Alternatively, fig. 14 is a schematic structural diagram of another infrared detector mirror image element based on a CMOS process according to an embodiment of the present invention, the infrared conversion structure may include two beam structures 122 as shown in fig. 1 to 13, and the infrared conversion structure may further include four beam structures 122 as shown in fig. 14, that is, the infrared conversion structure includes a first beam structure 122a and a second beam structure 122b arranged along a first direction XX ', and a third beam structure 122c and a fourth beam structure 122d arranged along a second direction YY', where the first direction XX 'is perpendicular to the second direction YY'.

As shown in fig. 14, the first beam structure 122a and the second beam structure 122b include a thermally symmetric structure, the position of the thermally symmetric structure can be referred to fig. 1-12, the third beam structure 122c and the fourth beam structure 122d do not include a thermally symmetric structure, the first beam structure 122a and the second beam structure 122b satisfy the thermally symmetric relationship, and the third beam structure 122c and the fourth beam structure 122d satisfy the thermally symmetric relationship.

As shown in fig. 14, the thermal conductance of the third beam structure 122c is set to be less than or equal to the thermal conductance of the first beam structure 122a or the thermal conductance of the second beam structure 122b, and the thermal conductance of the fourth beam structure 122d is set to be less than or equal to the thermal conductance of the first beam structure 122a or the thermal conductance of the second beam structure 122b, which is beneficial to reducing the total thermal conductance of the image element of the infrared detector and optimizing the infrared detection performance of the infrared detector formed by the image element of the infrared detector.

Alternatively, infrared detector mirror image element 100 may be configured to include one or two sets of two diagonally arranged columnar structures 130, as shown in fig. 1-12, and exemplarily, infrared detector mirror image element 100 is configured to include two sets of two diagonally arranged columnar structures 130, that is, infrared detector mirror image element 100 is configured to include columnar structures 130, and infrared detector mirror image element 100 may also be configured to include one set of two diagonally arranged columnar structures 130, that is, infrared detector mirror image element 100 is configured to include two columnar structures 130, as shown in fig. 15.

Alternatively, the columnar structure 130 in the infrared detector mirror image element 100 can be a hollow columnar structure as shown in fig. 1-14, and the columnar structure 130 can also be a solid columnar structure as shown in fig. 15.

For example, as shown in fig. 1-14, the columnar structure 130 may be a hollow columnar structure, which has low thermal conductivity and can reduce the thermal conductivity of the entire structure. The columnar structure 130 may also be a solid columnar structure, as shown in fig. 15, no residual sacrificial layer is left in the columnar structure 130, so that the vacuum degree of the infrared detector mirror image pixel 100 can be improved, and the influence on the electrical performance of the infrared detector mirror image pixel 100 is avoided. Meanwhile, the mechanical strength of the solid column structure is high, and the structural stability of the mirror image pixel 100 of the infrared detector can be improved. Illustratively, the material of the solid pillar structure may be at least one of aluminum, copper, and tungsten.

Optionally, fig. 16 is a schematic diagram of a film structure of an infrared detector mirror image element based on a CMOS process, where the CMOS infrared sensing structure further includes: a planarization layer 160, the planarization layer 160 comprising a patterned media structure, the patterned media structure and the support pedestal 111 being located on the same layer, and a Chemical Mechanical Polishing (CMP) process is used to make the surface of the planarization layer 160 facing away from the CMOS measurement circuitry 101 flush with the surface of the reflective layer 110 facing away from the CMOS measurement circuitry 101.

Specifically, a reflective layer 110 is formed on the CMOS measurement circuitry 101, and then the reflective layer 110 is patterned by etching, i.e., a supporting base 111 and a reflective plate 112 are formed. A space exists between the support base 111 and the reflective plate 112, i.e., a depression exists on the surface of the reflective layer 110. A flat layer 160 is deposited on the reflective layer 110, and the flat layer 160 can fill the recess of the reflective layer 110, at this time, the surface of the second flat layer 160 facing away from the CMOS measurement circuitry 101 is also uneven, wherein the surface of the film layer corresponding to the supporting base 111 and the reflective plate 112 is higher. The CMP process is adopted to polish the surface of one side, away from the CMOS measurement circuit system 101, of the flat layer 160, so that the height of the surface of the flat layer 160 corresponding to the supporting base 111 and the reflecting plate 112 is reduced, the surface, away from the CMOS measurement circuit system 101, of the flat layer 160 is flush with the surface, away from the CMOS measurement circuit system 101, of the reflecting layer 110, and each film formed in the subsequent process is guaranteed to be flat, so that the process difficulty can be reduced, the control precision of process parameters is high, and the yield of the infrared detector is improved.

Fig. 17 is a schematic view of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention. As shown in fig. 17, on the basis of the above embodiment, the CMOS manufacturing process of the CMOS measurement circuitry 101 may also include a metal interconnection process and a via process, the CMOS measurement circuitry 101 includes spaced metal interconnection layers 1011, dielectric layers 1012 and a silicon substrate 1013 at the bottom, and the upper and lower metal interconnection layers 1011 are electrically connected through a via 1014.

With reference to fig. 1 to 17, the CMOS infrared sensing structure 102 includes a resonant cavity formed by a reflective layer 110 and a thermal sensitive medium layer, a suspended microbridge structure for controlling heat transfer, and a pillar structure 130 having electrical connection and support functions, and the CMOS measurement circuitry 101 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 102 and convert an infrared signal into an electrical image signal.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 110 and the absorbing plate 121, for example, infrared light is reflected back and forth in the resonant cavity through the absorbing plate 121 to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structure 130, the beam structure 122 and the absorbing plate 121 form a suspended micro-bridge structure for controlling heat transfer, and the columnar structure 130 is electrically connected to the supporting base 111 and the corresponding beam structure 122 and is used for supporting the infrared conversion structure 120 on the columnar structure 130.

Alternatively, the CMOS infrared sensing structure 102 may be fabricated on top of or at the same level as the metal interconnect layers of the CMOS measurement circuitry 101.

Specifically, the metal interconnection layer of the CMOS measurement circuitry 101 may be a top metal layer in the CMOS measurement circuitry 101, and the CMOS infrared sensing structure 102 may be fabricated on the metal interconnection layer of the CMOS measurement circuitry 101, and the CMOS infrared sensing structure 102 is electrically connected to the CMOS measurement circuitry 101 through a supporting base 111 located on the metal interconnection layer of the CMOS measurement circuitry 101, so as to transmit the electrical signal converted by the infrared signal to the CMOS measurement circuitry 101, as shown in fig. 17.

Fig. 18 is a schematic view of a film structure of a mirror image pixel of an infrared detector based on a CMOS process according to another embodiment of the present invention. As shown in fig. 18, the CMOS infrared sensing structure 102 may also be prepared on the same layer as the metal interconnection layer of the CMOS measurement circuitry 101, that is, the CMOS measurement circuitry 101 and the CMOS infrared sensing structure 102 are arranged on the same layer, the CMOS infrared sensing structure 102 is arranged on one side of the CMOS measurement circuitry 101, and the top of the CMOS measurement circuitry 101 may also be provided with a hermetic release isolation layer to protect the CMOS measurement circuitry 101.

Optionally, with continued reference to fig. 16, the pillar structure 130 includes a plurality of independent pillar structures 131, the independent pillar structures 131 are located at different layers, and the independent pillar structures 131 are disposed corresponding to one or more layers of the hermetic release insulation layer 140.

Illustratively, as shown in fig. 16, the CMOS infrared sensing structure includes a plurality of hermetic release insulating layers 140, and accordingly, the pillar structure 130 includes a plurality of independent pillar structures 131, and the independent pillar structures 131 correspond to one hermetic release insulating layer 140. The method can be specifically realized by the following steps: after each layer of the close release isolation layer 140 is deposited, a pattern is formed on the close release isolation layer 140 by etching, and then a film structure of the independent columnar structure 131 is deposited, thereby forming the independent columnar structure 131. By the way of alternately forming the closed release isolation layer 140 and the independent columnar structure 131, the etching depth is small in the process, the etching process parameters of the closed release isolation layer 140 are easy to control, and the yield of the infrared detector is improved.

In other embodiments, there may be a plurality of hermetic release barriers 140 corresponding to one isolated pillar 131, as shown in fig. 19. The method can be specifically realized by the following steps: after the plurality of hermetic release insulating layers 140 are continuously deposited, a pattern is formed on the plurality of hermetic release insulating layers 140 by etching, and a film structure of the independent columnar structure 131 is deposited, thereby forming the independent columnar structure 131. The number of the process procedures can be reduced, the time of the process procedures is shortened, and the production efficiency of the infrared detector is improved.

Alternatively, fig. 20 is a schematic structural diagram of a reflective layer according to an embodiment of the invention, and as shown in fig. 20, the reflective plate 112 is electrically contacted to the grounded supporting base 111.

Specifically, as shown in fig. 20, the grounded support base 111 serves as a support and can discharge electric charges to the ground. The reflective plate 112 is electrically connected to the support base 111, which is grounded, and the charges accumulated in the reflective plate 112 can be discharged to the ground through the support base, so that the charges are prevented from accumulating to influence the electrical performance of the circuit.

Optionally, the material comprising the sacrificial layer in the mirror image element 100 comprises silicon oxide.

Illustratively, taking the infrared detector mirror image pixel 100 shown in fig. 2 as an example, the method for manufacturing the infrared detector mirror image pixel 100 may include sequentially forming a reflective layer 110, a sacrificial layer (not shown), a pillar structure 130, a support layer 210, an electrode layer 220, a thermal sensitive layer 240, and a passivation layer 230 on the CMOS measurement circuitry 101, and releasing the sacrificial layer, i.e., removing the sacrificial layer.

Optionally, the sacrificial layer is used to form the CMOS infrared sensing structure 102 into a hollowed-out structure, and the sacrificial layer is etched by a post-CMOS process, which may, for example, use at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane to etch the sacrificial layer. The sacrificial layer may be made of silicon oxide, which is a commonly used material in CMOS processes, i.e., silicon oxide is compatible with CMOS processes, so that the sacrificial layer can be formed using CMOS processes. For example: a silicon oxide layer is deposited on one side of the reflective layer 110, and then a silicon oxide layer with a specific pattern is formed by etching, i.e., a sacrificial layer is formed. Therefore, the readout circuit and the sacrificial layer in the CMOS measurement circuit system 101 can be prepared by using a CMOS process, which is beneficial to realizing full CMOS process flow of the infrared detector, i.e., the integrated manufacturing of the infrared detector can be realized by using the CMOS process, which is beneficial to improving the manufacturing yield and productivity of the infrared detector and reducing the manufacturing cost of the infrared detector.

In other embodiments, the thermal sensitive layer 240, the dielectric layer, the electrode layer 220, and the passivation layer 230 may be sequentially formed on the support layer 210 to form the mirror image pixel 100 shown in fig. 8, and in practical applications, the process sequence of the thermal sensitive layer 240 and the electrode layer 220 may be flexibly adjusted.

Illustratively, taking the infrared detector mirror image pixel 100 shown in fig. 9 and 10 as an example, the method for manufacturing the infrared detector mirror image pixel 100 may include sequentially forming a reflective layer 110, a first sacrificial layer (not shown), a pillar structure 130, a first support layer 211, a first electrode layer 221, a first passivation layer 231, a second sacrificial layer (not shown), a second support layer 212, a second electrode layer 222, a thermal sensitive layer 240, and a second passivation layer 232 on the CMOS measurement circuitry 101, and releasing the first sacrificial layer and the second sacrificial layer, i.e., removing the first sacrificial layer and the second sacrificial layer.

Optionally, the first sacrificial layer and the second sacrificial layer are used for forming the CMOS infrared sensing structure 102 into a hollow structure, and the first sacrificial layer and the second sacrificial layer are etched by a post-CMOS process, which may, for example, etch the first sacrificial layer and the second sacrificial layer by using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane. Both the first sacrificial layer and the second sacrificial layer may be made of silicon oxide, which is a material commonly used in CMOS processes, i.e., silicon oxide is compatible with CMOS processes, and thus the first sacrificial layer and the second sacrificial layer can be formed using CMOS processes. For example: a silicon oxide layer is deposited on one side of the reflective layer 110, and then the silicon oxide layer with a specific pattern is formed by etching, i.e., a first sacrificial layer is formed. Therefore, the readout circuit and the first sacrificial layer in the CMOS measurement circuit system 101 can be prepared by using a CMOS process, which is beneficial to realizing full CMOS process flow of the infrared detector, i.e., the integrated manufacturing of the infrared detector can be realized by using the CMOS process, which is beneficial to improving the manufacturing yield and productivity of the infrared detector and reducing the manufacturing cost of the infrared detector. The above embodiment is only exemplarily illustrated by using silicon oxide to prepare the first sacrificial layer, and in practical applications, the second sacrificial layer may also be prepared by using silicon oxide, which also has the beneficial effects of the above embodiment, and is not described herein again.

In other embodiments, the thermosensitive layer 240, the dielectric layer, the second electrode layer 222, and the second passivation layer 232 may be sequentially formed on the second supporting layer 212 to form the mirror image pixel 100 as shown in fig. 11, and in practical applications, the process sequence of the thermosensitive layer 240 and the second electrode layer 222 may be flexibly adjusted.

In addition, the material of the thermosensitive layer 240 may be one or more of amorphous silicon, amorphous carbon, amorphous germanium, or amorphous silicon germanium, so that the thermosensitive layer 240 may serve as a support structure in the absorption plate 121, and a separate support film layer is not required to be fabricated, which is beneficial to further reducing the thickness of the absorption plate 121, further reducing the heat capacity of the absorption plate 121, and reducing the thermal response time of the infrared detector.

Optionally, the image element of the infrared detector mirror image can be set based on a CMOS process of 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm, and the aforementioned dimensions represent process nodes of the integrated circuit, that is, feature dimensions during the processing of the integrated circuit.

Optionally, the side length of the supporting base 111 is equal to or less than 3 micrometers and equal to or more than 0.5 micrometers.

Specifically, the material constituting the infrared detector mirror image pixel reflection layer 110 based on the CMOS process may be set to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measurement circuit system 101 and the CMOS infrared sensing structure 102 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 102 is directly prepared on the CMOS measurement circuit system 101, so that it can be realized that the side length of the supporting base 111 is less than or equal to 3 micrometers and greater than or equal to 0.5 micrometers, the width of the beam structure 122, that is, the width of a single line in the beam structure 122 is less than or equal to 0.3um, the height of the resonant cavity is greater than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel is greater than or equal to 6um and less than or equal to 17 um. For the full CMOS process of the detector, the reflective layer 110 can be formed in both the effective pixel and the mirror image pixel by the same process, and for the effective pixel, the smaller the side length of the supporting base 111, i.e., the smaller the area of the supporting base 111, the larger the area of the reflective plate 112, the more infrared radiation energy absorbed by the sensor, and thus the detection efficiency of the infrared detector can be improved.

An embodiment of the present invention further provides an infrared detector based on a CMOS process, and fig. 21 is a schematic perspective view of the infrared detector based on the CMOS process according to the embodiment of the present invention. As shown in fig. 21, the infrared detector 200 based on the CMOS process includes any one of the above-mentioned embodiments of the mirror image pixel 100 of the infrared detector based on the CMOS process, and the advantageous effects of the above-mentioned embodiments are not described herein again. Illustratively, the infrared detector may be, for example, an uncooled infrared focal plane detector.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared detector mirror image pixel based on CMOS technology, comprising:

2. The CMOS process-based infrared detector mirror image pixel of claim 1, wherein the infrared conversion structure comprises a plurality of beam structures and an absorption plate, the absorption plate is used for converting infrared signals into electrical signals and is electrically connected with the corresponding pillar structures through the corresponding beam structures;

3. The CMOS process-based infrared detector mirror image pixel of claim 2, wherein the absorber plate and the beam structure are on different layers, the beam structure comprising a first electrode layer, the absorber plate comprising a second electrode layer and a thermally sensitive layer, the second electrode layer being electrically connected to the pillar structure through the first electrode layer.

4. The CMOS-process-based infrared detector mirror image pixel according to claim 2 or 3, wherein the beam structures are respectively connected with an intermediate support structure and the columnar structures, and in a plurality of the beam structures, two parallel beam structures meeting at the same node in a beam path from the intermediate support structure to the corresponding columnar structure are respectively a first half-bridge structure and a second half-bridge structure, and the first half-bridge structure and the second half-bridge structure form a thermally symmetric structure; wherein the length of the first half-bridge structure is greater than the length of the second half-bridge structure, and the thickness of the first half-bridge structure is greater than the thickness of the second half-bridge structure in a direction perpendicular to the CMOS measurement circuitry.

5. The CMOS process-based infrared detector mirror pixel of claim 1, wherein the CMOS infrared sensing structure further comprises:

and the surface of the flat layer, which is far away from the CMOS measuring circuit system, is flush with the surface of the reflection layer, which is far away from the CMOS measuring circuit system, by adopting a CMP process.

6. The CMOS process-based infrared detector mirror image pixel of claim 1, wherein the pillar structures comprise a plurality of independent pillar structures located at different layers, the independent pillar structures being disposed in correspondence with one or more of the hermetic release barrier layers.

7. The CMOS-process-based infrared detector mirror image cell of claim 1, wherein the reflector plate is in electrical contact with the support base that is grounded.

8. The CMOS-process-based infrared detector mirror pixel of claim 1, wherein a material comprising the sacrificial layer in the mirror pixel comprises silicon oxide.

9. The CMOS process-based infrared detector mirror image pixel of claim 8, wherein the sacrificial layer is used for forming the CMOS infrared sensing structure into a hollowed-out structure, and the sacrificial layer is etched by at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane.

10. The CMOS process-based infrared detector mirror image pixel of claim 1, wherein the side length of said supporting base is 3 microns or less and 0.5 microns or more.

11. An infrared detector based on a CMOS process, characterized by comprising an infrared detector mirror image element according to any one of claims 1 to 10.