CN113720452B

CN113720452B - Infrared detector pixel based on CMOS (complementary metal oxide semiconductor) process and infrared detector

Info

Publication number: CN113720452B
Application number: CN202110324040.1A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2023-03-24
Anticipated expiration: 2041-03-26
Also published as: CN113720452A

Abstract

The utility model relates to an infrared detector pixel and infrared detector based on CMOS technology, which comprises a CMOS measuring circuit system and a CMOS infrared sensing structure on the CMOS measuring circuit system; the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, and the at least one layer of closed release isolation layer is positioned in the CMOS infrared sensing structure; the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of first columnar structures, wherein the infrared conversion structure comprises an absorption plate and a plurality of beam structures, and the width of each beam structure is less than or equal to 0.3 micrometer; the material of the sacrificial layer in the infrared detector comprises silicon oxide, the problems of low performance, low pixel scale, low yield and the like of the infrared detector in the traditional MEMS process are solved, the release difficulty of the sacrificial layer is reduced by the closed release isolation layer in the CMOS infrared sensing structure, and the detection sensitivity of the infrared detector is improved.

Description

Infrared detector pixel based on CMOS (complementary metal oxide semiconductor) process and infrared detector

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an infrared detector pixel and an infrared detector based on a CMOS (complementary metal oxide semiconductor) process.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) The infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

In addition, the resonant cavity in the existing infrared detector is high, and the release difficulty of the sacrificial layer is increased.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides an infrared detector pixel and an infrared detector based on a CMOS process, which solve the problems of low performance, low pixel scale, low yield and the like of the conventional MEMS process infrared detector, and a hermetic release isolation layer in a CMOS infrared sensing structure reduces the release difficulty of a sacrificial layer and improves the detection sensitivity of the infrared detector.

In a first aspect, an embodiment of the present disclosure provides an infrared detector pixel based on a CMOS process, including:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure, and the at least one layer of closed release isolation layer is positioned in the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of first columnar structures, wherein the reflecting layer, the infrared conversion structure and the plurality of first columnar structures are positioned on the CMOS measuring circuit system, the first columnar structures are positioned between the reflecting layer and the infrared conversion structure, the reflecting layer comprises a reflecting plate and a supporting base, and the infrared conversion structure is electrically connected with the CMOS measuring circuit system through the first columnar structures and the supporting base;

the infrared conversion structure comprises an absorption plate and a plurality of beam structures, the absorption plate is used for converting infrared signals into electric signals and is electrically connected with the corresponding first columnar structures through the corresponding beam structures, the absorption plate comprises a thermosensitive layer, the thermosensitive layer is made of at least one of titanium oxide, vanadium oxide or titanium vanadium oxide, the material is perpendicular to the extending direction of the beam structures, and the width of each beam structure is less than or equal to 0.3 micrometer;

the sacrificial layer in the infrared detector is made of silicon oxide, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the sacrificial layer is corroded by a post-CMOS process, and the sacrificial layer is corroded by at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane in the post-CMOS process.

Optionally, the absorber plate and the beam structure are located in the same layer.

Optionally, the beam structure includes a support layer and an electrode layer, the support layer is located on one side of the electrode layer adjacent to the CMOS measurement circuitry, and a material constituting the electrode layer includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum; alternatively, the first and second electrodes may be,

the beam structure comprises a supporting layer, an electrode layer and a passivation layer, wherein the electrode layer is located between the supporting layer and the passivation layer, the supporting layer is located on one side, close to the CMOS measuring circuit system, of the passivation layer, and the material for forming the electrode layer comprises at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel and platinum.

Optionally, the absorption plate further comprises a support layer and a passivation layer, the heat sensitive layer is located between the support layer and the passivation layer, and the support layer is located on a side of the passivation layer adjacent to the CMOS measurement circuitry; alternatively, the first and second electrodes may be,

the absorption plate further comprises a supporting layer, an electrode layer and a passivation layer, wherein the electrode layer and the heat-sensitive layer are located between the supporting layer and the passivation layer, and the supporting layer is located on one side, close to the CMOS measuring circuit system, of the passivation layer.

Optionally, the beam structure is located on a side of the absorption plate close to the CMOS measurement circuit system, a second columnar structure is disposed between the absorption plate and the beam structure, and the absorption plate is configured to convert an infrared signal into an electrical signal and is electrically connected to the corresponding first columnar structure through the second columnar structure and the corresponding beam structure.

Optionally, the beam structure includes a first support layer and a first electrode layer, the first support layer is located on a side where the first electrode layer is close to the CMOS measurement circuit system, and a material constituting the first electrode layer includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum.

Optionally, the absorber plate further comprises a second support layer and a second passivation layer, the heat sensitive layer being located between the second support layer and the second passivation layer, the second support layer being located on a side of the second passivation layer adjacent to the CMOS measurement circuitry; alternatively, the first and second electrodes may be,

the absorption plate further comprises a second supporting layer, a second electrode layer and a second passivation layer, the second electrode layer and the thermosensitive layer are located between the second supporting layer and the second passivation layer, the second supporting layer is located on one side, close to the CMOS measuring circuit system, of the second passivation layer, and the material forming the second electrode layer comprises at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel or platinum.

Optionally, the beam structure includes a first supporting layer, a first electrode layer and a first passivation layer, the first electrode layer is located the first supporting layer with between the first passivation layer, the first supporting layer is located the first passivation layer is close to one side of the CMOS measurement circuitry, and the material constituting the first electrode layer includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel or platinum.

Optionally, the absorber plate further comprises a second support layer and a second passivation layer, the thermally sensitive layer being located between the second support layer and the second passivation layer, the second support layer being located on a side of the second passivation layer adjacent to the CMOS measurement circuitry; alternatively, the first and second liquid crystal display panels may be,

the absorption plate further comprises a second supporting layer, a second electrode layer and a second passivation layer, the second electrode layer and the thermosensitive layer are located between the second supporting layer and the second passivation layer, the second supporting layer is located on one side, close to the CMOS measuring circuit system, of the second passivation layer, and the material forming the second electrode layer comprises at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel and platinum.

Optionally, the heat-sensitive layer comprises a heat-sensitive structure, and corrosion protection structures are arranged on the upper surface, the lower surface and the side surfaces of the heat-sensitive structure.

In a second aspect, an embodiment of the present disclosure provides an infrared detector, including a plurality of infrared detection pixels as described in the first aspect.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

(1) The CMOS measurement circuit system and the CMOS infrared sensing structure are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has mature process production line and higher process control precision, can better meet the design requirement, has better product consistency, is more beneficial to the adjustment performance of a circuit chip and is more beneficial to industrialized mass production;

(2) The CMOS measurement circuit system comprises at least one layer of closed release isolation layer above, wherein the closed release isolation layer is used in the etching process of manufacturing a CMOS infrared sensing structure and protects the CMOS measurement circuit system from being influenced by the process, the at least one layer of closed release isolation layer is positioned in the CMOS infrared sensing structure, the closed release isolation layer can be positioned above a metal interconnection layer of a reflecting layer, the closed release isolation layer coats a columnar structure, and the closed release isolation layer coats the columnar structure. On the other hand, the airtight release insulating layer coating the columnar structure can reduce the contact between the columnar structure and the external environment, reduce the contact resistance between the columnar structure and the external environment, further reduce the noise of the infrared detector pixel and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrifice layer is arranged between the reflecting layer and the infrared conversion structure and is in contact with the reflecting layer and the infrared conversion structure. When at least one layer of closed release isolation layer positioned on the reflection layer is arranged as one part of the resonant cavity, the height of the resonant cavity can be reduced by the closed release isolation layer arranged at the moment, so that the thickness of the sacrificial layer is reduced, and the release difficulty of the sacrificial layer formed by silicon oxide in the resonant cavity is reduced. In addition, a closed release isolation layer and the columnar structure are arranged to form a closed structure, the CMOS measurement circuit system is completely separated from the sacrificial layer, and the CMOS measurement circuit system is protected.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

FIG. 1 is a schematic perspective view of an infrared detector pixel provided in an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of an infrared detector pixel based on a CMOS process provided in fig. 1;

FIG. 3 is a schematic perspective view of another infrared detector pixel provided in an embodiment of the present invention;

FIG. 4 is a schematic perspective view of the pixel of the infrared detector provided in FIG. 3;

FIG. 5 is a schematic cross-sectional view of an infrared detector pixel provided in an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of an infrared detector pixel provided in an embodiment of the present invention;

fig. 7 is a schematic cross-sectional structure diagram of a pixel of another infrared detector provided by an embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view of an infrared detector pixel provided in an embodiment of the present invention;

FIG. 9 is an exploded view of a beam structure according to an embodiment of the present invention;

FIG. 10 is an exploded view of an absorbent panel according to an embodiment of the present invention;

FIG. 11 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

FIG. 12 is an exploded view of another absorbent panel provided by an embodiment of the present invention;

FIG. 13 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

FIG. 14 is an exploded view of another beam construction provided by an embodiment of the present invention;

FIG. 15 is an exploded view of another absorbent panel according to an embodiment of the present invention;

FIG. 16 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

FIG. 17 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

FIG. 18 is a schematic cross-sectional view of a pixel of an infrared detector provided in an embodiment of the invention;

FIG. 19 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

FIG. 20 is a schematic diagram of a CMOS measurement circuitry according to an embodiment of the present invention;

FIG. 21 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the present invention;

fig. 22 is a schematic perspective view of an infrared detector according to an embodiment of the present invention.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective view of an infrared detector pixel provided in an embodiment of the present invention, fig. 2 is a schematic cross-sectional view of the infrared detector pixel provided in fig. 1, fig. 3 is a schematic perspective view of another infrared detector pixel provided in an embodiment of the present invention, fig. 4 is a schematic cross-sectional view of the infrared detector pixel provided in fig. 3, and in conjunction with fig. 1, fig. 2, fig. 3, and fig. 4, an infrared detector pixel 01 based on a CMOS process includes: the CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 located on the CMOS measurement circuit system 100, the CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 are all manufactured by adopting a CMOS process, and the CMOS infrared sensing structure 200 is directly manufactured on the CMOS measurement circuit system 100. The CMOS measurement circuit system 100 includes at least one layer of hermetic release isolation layer 40 above, the hermetic release isolation layer 40 is used for protecting the CMOS measurement circuit system 100 from process influence during an etching process for manufacturing the CMOS infrared sensing structure 200, and the at least one layer of hermetic release isolation layer 40 is located in the CMOS infrared sensing structure 200. The CMOS fabrication process of the CMOS infrared sensing structure 200 includes a metal interconnection process, a via process, and an RDL process, and the CMOS infrared sensing structure 200 includes at least two metal interconnection layers, at least two dielectric layers, and a plurality of interconnection vias. . The infrared conversion structure 20 includes an absorption plate 21 and a plurality of beam structures 22, and the absorption plate 21 is used to convert an infrared signal into an electrical signal and is electrically connected to the corresponding first pillar structure 30 through the corresponding beam structure 22. The absorption plate 21 includes a thermosensitive layer, a material constituting the thermosensitive layer includes at least one of titanium oxide, vanadium oxide, or vanadium titanium oxide, perpendicular to an extending direction of the beam structure 22, and a width of the beam structure 22 is 0.3 μm or less. The sacrificial layer is made of silicon oxide and used for enabling the CMOS infrared sensing structure to form a hollow structure, the sacrificial layer is corroded by a post-CMOS process, and the sacrificial layer is corroded by at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane in the post-CMOS process.

Specifically, the CMOS infrared sensing structure 200 is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 100, and the CMOS measurement circuit system 100 reflects temperature information of the corresponding infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 200 is directly prepared on the CMOS measurement circuit system 100, namely, the CMOS measurement circuit system 100 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 200 is continuously prepared by using the CMOS process by using parameters of a CMOS production line and various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty faced by the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

Referring to fig. 1 and 2, the CMOS infrared sensing structure 200 includes a reflective layer 10, an infrared conversion structure 20, and a plurality of first pillar structures 30, which are located on the CMOS measurement circuit system 100, the reflective layer 10 is used to reflect infrared rays to an absorption plate in a detector pixel and implement secondary absorption of infrared rays by matching with a resonant cavity, the plurality of first pillar structures 30 are used to support the infrared conversion structure 20 in the detector pixel, the infrared conversion structure 20 detects infrared radiation signals and converts the detected infrared radiation signals into electrical signals, the electrical signals formed by conversion are transmitted to the CMOS measurement circuit system 100 through the first pillar structures 30, and the CMOS measurement circuit system 100 processes and outputs the electrical signals.

Specifically, the first columnar structure 30 is located between the reflection layer 10 and the infrared conversion structure 20 and is used for supporting the infrared conversion structure 20 after a sacrificial layer on the CMOS measurement circuit system 100 is released, the sacrificial layer is located between the reflection layer 10 and the infrared conversion structure 20, the first columnar structure 30 is a metal structure, an electrical signal converted by the infrared signal of the infrared conversion structure 20 is transmitted to the CMOS measurement circuit system 100 through the corresponding first columnar structure 30 and the corresponding support base 12, the CMOS measurement circuit system 100 processes the electrical signal to reflect temperature information, and non-contact infrared temperature detection of the infrared detector is achieved. The CMOS infrared sensing structure 200 outputs a positive electrical signal and a ground electrical signal through different electrode structures, and the positive electrical signal and the ground electrical signal are transmitted to the supporting base 12 electrically connected to the first columnar structure 30 through different first columnar structures 30, fig. 1 exemplarily illustrates that four columnar structures 30 are included along the CMOS infrared sensing structure 200, two of the columnar structures 30 may be configured to transmit the positive electrical signal, the other two columnar structures 30 are configured to transmit the ground electrical signal, and the CMOS infrared sensing structure 200 may also be configured to include two columnar structures 30 that respectively transmit the positive electrical signal and the ground electrical signal. In addition, the reflective layer 10 includes a reflective plate 11 and a supporting base 12, a portion of the reflective layer 10 is used as a dielectric for electrically connecting the first columnar structure 30 with the CMOS measurement circuit system 100, that is, the supporting base 12, and the reflective plate 11 is used for reflecting infrared rays to the infrared conversion structure 20, and the secondary absorption of infrared rays is realized by matching with a resonant cavity formed between the reflective layer 10 and the infrared conversion structure 20, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

In the reflective layer 10, the material of the reflective plate 11 may be at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, the material of the reflective plate 11 is not particularly limited in the embodiment of the present invention, and the thickness of the reflective layer 10 is 1000A to 10000A.

Referring to fig. 2, the CMOS measurement circuit system 100 includes at least one hermetic release isolation layer 40 above, the hermetic release isolation layer 40 is used to protect the CMOS measurement circuit system 100 from process influence during an etching process for fabricating the CMOS infrared sensing structure 200, the at least one hermetic release isolation layer 40 is located in the CMOS infrared sensing structure 200, fig. 2 exemplarily sets the hermetic release isolation layer 400 in the CMOS infrared sensing structure 200, the hermetic release isolation layer 40 may be located above a metal interconnection layer of the reflection layer 10, for example, the hermetic release isolation layer 40 covers the first pillar structure 30, and by setting the hermetic release isolation layer 40 to cover the first pillar structure 30, on one hand, the hermetic release isolation layer 40 may be used as a support at the first pillar structure 30, so as to improve stability of the first pillar structure 30, and ensure electrical connection between the first pillar structure 30 and the infrared conversion structure 20 and the support base 12. On the other hand, the closed release insulating layer 40 covering the first columnar structure 30 can reduce the contact between the first columnar structure 30 and the external environment, reduce the contact resistance between the first columnar structure 30 and the external environment, further reduce the noise of the infrared detector pixel, and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrifice layer is arranged between the reflecting layer and the infrared conversion structure and is in contact with the reflecting layer and the infrared conversion structure. When at least one layer of the closed release isolation layer 40 on the reflection layer 10 is arranged as a part of the resonant cavity, the height of the resonant cavity can be reduced by the closed release isolation layer 40, so that the thickness of the sacrificial layer is reduced, and the release difficulty of the sacrificial layer formed by silicon oxide in the resonant cavity is reduced. In addition, the hermetic release isolation layer 40 and the first columnar structure 30 are arranged to form a hermetic structure, so as to completely separate the CMOS measurement circuit system 100 from the sacrificial layer, thereby protecting the CMOS measurement circuit system 100.

The CMOS manufacturing process of the CMOS infrared sensing structure 200 comprises a metal interconnection process, a through hole process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure 200 comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes, the dielectric layers at least comprise a sacrificial layer and a heat-sensitive dielectric layer, the heat-sensitive dielectric layer at least comprises a heat-sensitive layer and also comprises a supporting layer and/or a passivation layer, and the metal interconnection layers at least comprise a reflecting layer and an electrode layer; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and then an infrared target signal is converted into a signal capable of being read electrically through the CMOS measurement circuit system 100.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a redistribution layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the reflection layer 10 in the infrared detector can be prepared on the top metal of the CMOS measurement circuit system 100 through the RDL process, and the support base 12 on the reflection layer 10 is electrically connected with the top metal of the CMOS measurement circuit system 100. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

It should be noted that fig. 2 exemplarily shows that the first columnar structure 30 is a hollow structure, in other embodiments, the first columnar structure 30 may be a solid structure, and the specific structure of the first columnar structure 30 is not limited in the embodiment of the present invention. In addition, the material of the first pillar structure 30 may be a metal material or a non-metal material, as long as it is ensured that an electrical signal can be transmitted to the CMOS measurement circuitry 100 through the first pillar structure 30 and the support base 12.

Further, the film layers of the beam structure 22 may be designed according to an overall structure, and when the beam structure 22 is formed by using a CMOS process, each film layer of the beam structure 22 may be made very thin by using the CMOS process, and has good uniformity and small thermal conductivity, thereby improving the detection sensitivity of the infrared detector. In addition, when the CMOS infrared sensing structure is manufactured by using a CMOS process, the width of the manufactured beam structure 22 in the direction perpendicular to the extending direction of the beam structure 22 is less than or equal to 0.3 μm, that is, the line width of the beam structure 22 manufactured by using the CMOS process is smaller, and the smaller line width can reduce the thermal conductance of the beam structure 22, reduce the occupied area of the beam structure 22, further increase the area of the absorption plate 21, and improve the detection performance of the detector.

Specifically, the absorption plate and the beam structure of the infrared conversion structure may be arranged in the same layer, as shown in fig. 1 and 2, or in different layers, as shown in fig. 3 and 4, which will be illustrated by specific examples.

For example, specifically explaining the absorption plate and the beam structure in the same layer arrangement, fig. 5 is a schematic cross-sectional structure diagram of another infrared detector pixel based on a CMOS process according to an embodiment of the present invention, and as shown in fig. 5, the beam structure 22 includes a supporting layer 220 and an electrode layer 221, the supporting layer 220 is located on a side of the electrode layer 221 adjacent to the CMOS measurement circuitry 100, and a material constituting the electrode layer 221 includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a support layer 211 and a passivation layer 212, the thermo-sensitive layer 210 being located between the support layer 211 and the passivation layer 212, the support layer 211 being located on a side of the passivation layer 212 adjacent to the CMOS measurement circuitry 100.

As shown in fig. 5, by providing the beam structure 22 including the support layer 220, the electrode layer 221 of the beam structure 22 is supported by the support layer 220. The support layer 211 on the absorber plate 21 provides support for the heat sensitive layer 210 on the absorber plate 21, and the passivation layer 212 serves to protect the heat sensitive layer 210 from oxidation or corrosion.

With continued reference to fig. 5, the absorption plate 21 further comprises patterned electrode structures 213, the patterned electrode structures 213 being electrically connected with the corresponding beam structures 22, the patterned electrode structures 213 being adapted to transmit electrical signals converted out by the thermosensitive layer 210 to the corresponding beam structures 22. Specifically, the thermal sensitive layer 210 is used to convert an infrared signal into an electrical signal, and the patterned electrode structure 213 transmits the electrical signal converted by the thermal sensitive layer 210 to the CMOS measurement circuitry 100 through the electrode layer 221 on the beam structure 22. Illustratively, the patterned electrode structure may have a serpentine shape of a reverse turn, the patterned electrode structure comprising two portions, each portion being electrically connected to each other, one portion for transmitting a positive electrical signal and one portion for transmitting a ground electrical signal.

When the beam structure is arranged to include the two-layer structure of the support layer 220 and the electrode layer 221, the material of the electrode layer 221 arranged to form the beam structure 22 includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel or platinum, which can effectively improve the oxidation resistance of the first electrode layer 221 and reduce the thermal conductivity of the first electrode layer 221, so that a passivation layer is not required to be arranged on the beam structure 22, the thickness of the beam structure 22 is reduced, the thermal conductivity of the beam structure 121 is favorably reduced, and the thermal responsiveness of the infrared detector is improved.

When the absorption plate 21 is disposed to include the three-layer structure of the support layer 211, the heat sensitive layer 210 and the passivation layer 212, the patterned electrode structure 213 may be disposed at the same layer as the passivation layer 212, or the patterned electrode structure 213 may be disposed at the same layer as the heat sensitive layer 210. For example, when the patterned electrode structure 213 and the passivation layer 212 are disposed on the same layer, as shown in fig. 5, the upper and lower surfaces and the side surfaces of the thermal sensitive structure are provided with corrosion protection structures, the patterned electrode structure 213, the passivation layer 212, and the support layer 211 form protection for the upper and lower surfaces and the side surfaces of the thermal sensitive layer 210, and the patterned electrode structure 213, the passivation layer 212, and the support layer 211 form a corrosion protection structure, so as to prevent corrosion of the material of the thermal sensitive layer 210 by the gas-phase hydrogen fluoride when the structure is hollowed out by etching the sacrificial layer by the VHF gas-phase hydrogen fluoride etching process. In addition, the three-layer structure comprising the support layer 211, the heat sensitive layer 210 and the passivation layer 212 is arranged to form the absorption plate 21, so that the patterned electrode structure 213 and the passivation layer 212 in the absorption plate 21 can be prepared in the same process, or the patterned electrode structure 213 and the heat sensitive layer 210 are prepared in the same process, and the process complexity is reduced. The beam structure comprises a supporting layer 220 and an electrode layer 221, a passivation layer is not required to be arranged on the beam structure 22, the thickness of the beam structure 22 is reduced, the thermal conduction of the beam structure 121 is favorably reduced, and the thermal responsivity of the infrared detector is improved.

Optionally, when the absorber plate and the beam structure are arranged on the same layer, the beam structure 22 includes a support layer 220 and an electrode layer 221, the support layer 220 is located on a side of the electrode layer 221 close to the CMOS measurement circuit system 100, and a material constituting the electrode layer 221 includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a support layer 211, an electrode layer 213 and a passivation layer 212, the electrode layer 213 and the thermo-sensitive layer 210 being located between the support layer 211 and the passivation layer 212, the support layer 211 being located on a side of the passivation layer 212 adjacent to the CMOS measurement circuitry 100, as shown in fig. 6.

Referring to fig. 6, the arrangement beam structure 11 includes two layers, namely a support layer 220 and an electrode layer 221, the absorption plate 21 includes four layers, namely a support layer 211, an electrode layer 213, a thermal sensitive layer 210 and a passivation layer 212, in this case, the electrode layer 213 of the absorption plate may be disposed on a side of the thermal sensitive layer 210 adjacent to the support layer 211, or the electrode layer 213 may be disposed on a side of the thermal sensitive layer 210 adjacent to the passivation layer 212, and the position of the electrode layer 213 in the absorption plate 21 may be selected according to a specific manufacturing process, so that process compatibility is good. When the absorption plate 21 comprises four-layer structures of the support layer 211, the electrode layer 213, the thermal sensitive layer 210 and the passivation layer 212, corrosion protection structures are arranged on the upper surface, the lower surface and the side surfaces of the thermal sensitive structure, the electrode layer 213, the passivation layer 212 and the support layer 211 form protection on the upper surface, the lower surface and the side surfaces of the thermal sensitive layer 210, the patterned electrode structure 213, the passivation layer 212 and the support layer 211 form a corrosion protection structure, and corrosion of the thermal sensitive layer material by gas-phase hydrogen fluoride is avoided when the sacrificial layer is corroded by a VHF gas-phase hydrogen fluoride corrosion process to realize structure hollowing.

The absorption plate 21 comprises a four-layer structure of a support layer 211, an electrode layer 213, a thermosensitive layer 210 and a passivation layer 212, and the electrode layer 213 in the absorption plate 21 can be arranged at a position selected according to a specific preparation process, so that the process compatibility is good. In addition, the arranged passivation layer can protect the electrode layer and the thermosensitive layer, and the material selection range of the electrode layer is wider. The beam structure comprises a supporting layer 220 and an electrode layer 221, a passivation layer is not required to be arranged on the beam structure 22, the thickness of the beam structure 22 is reduced, the thermal conductivity of the beam structure 121 is favorably reduced, the thermal responsivity of the infrared detector is improved, and the process complexity is reduced.

Optionally, when the absorber plate and the beam structure are arranged on the same layer, the beam structure 22 includes a support layer 220, an electrode layer 221, and a passivation layer 222, the electrode layer 221 is located between the support layer 220 and the passivation layer 222, the support layer 220 is located on a side of the passivation layer 222 adjacent to the CMOS measurement circuit system 100, and a material constituting the electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, and platinum. The absorption plate 21 further comprises a support layer 211 and a passivation layer 212, the thermo-sensitive layer 210 being located between the support layer 211 and the passivation layer 212, the support layer 211 being located on a side of the passivation layer 212 adjacent to the CMOS measurement circuitry 100, see fig. 7.

As shown in fig. 7, the beam structure 22 is provided with a three-layer structure including a support layer 220, an electrode layer 221 and a passivation layer 222, the absorption plate 21 includes a three-layer structure including a support layer 211, a thermosensitive layer 210 and a passivation layer 212, the electrode layer 221 of the beam structure 22 is supported by the support layer 220, and the passivation layer 222 of the beam structure 22 is used for protecting the electrode layer 221 on the beam structure 22, so as to prevent the electrode layer 221 from being corroded, and to enhance the mechanical strength of the beam structure. Illustratively, the material of the electrode layer 221 constituting the beam structure 22 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum, and the material of the electrode layer 221 is not specifically limited in the embodiments of the present invention.

It should be noted that when the absorber plate 21 is formed to include a three-layer structure of the support layer 211, the heat sensitive layer 210 and the passivation layer 212, and the beam structure 22 is formed to include a three-layer structure of the support layer 220, the electrode layer 221 and the passivation layer 222, the patterned electrode structure 213 on the absorber plate 21 is disposed at the same layer as the heat sensitive layer 210, and the heat sensitive layer 210 and the patterned electrode structure 213 are protected by the passivation layer 212. Since the formed absorption plate 21 includes the three-layer structure and the formed beam structure 22 includes the three-layer structure, the beam structure 22 and the absorption plate 21 can be separately formed in the same manufacturing process, thereby reducing the process complexity. In addition, when the beam structure is arranged to include the three-layer structure of the support layer 220, the electrode layer 221 and the passivation layer 222, the passivation layer 222 on the electrode layer 221 can protect the electrode layer 221, so that the electrode layer 221 is not corroded, the mechanical strength of the beam structure 22 is enhanced, and further, more materials can be selected for the electrode layer 221.

Optionally, when the absorber plates and the beam structures are arranged on the same layer, the beam structure 22 is configured to include a support layer 220, an electrode layer 221, and a passivation layer 222, the electrode layer 221 is located between the support layer 220 and the passivation layer 222, the support layer 220 is located on a side of the passivation layer 222 close to the CMOS measurement circuit system 100, and a material constituting the electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, a titanium tungsten alloy, a nickel-chromium alloy, a nickel-platinum alloy, a silicon-nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a support layer 211, an electrode layer 213 and a passivation layer 212, the electrode layer 213 and the thermo-sensitive layer 210 being located between the support layer 211 and the passivation layer 212, the support layer 211 being located on a side of the passivation layer 212 adjacent to the CMOS measurement circuitry 100, see fig. 8.

As shown in fig. 8, the arrangement beam structure 22 includes a three-layer structure of a support layer 220, an electrode layer 221, and a passivation layer 222, and the arrangement absorber plate 21 further includes a four-layer structure of a support layer 211, an electrode layer 213, a thermal sensitive layer 210, and a passivation layer 212, where the electrode layer 213 on the absorber plate 21 may be located on a side of the thermal sensitive layer 210 close to the passivation layer 212, and the electrode layer 213 may also be located on a side of the thermal sensitive layer 210 close to the support layer 211, where the electrode layer 213 in the absorber plate 21 may be selectively arranged according to a specific manufacturing process, and process compatibility is good. When the beam structure is arranged to include three layers of the support layer 220, the electrode layer 221 and the passivation layer 222, the passivation layer 222 on the electrode layer 221 can protect the electrode layer 221, so that the electrode layer 221 is not corroded, the mechanical strength of the beam structure 22 is enhanced, and further, more materials can be selected for the electrode layer 221.

Fig. 4 to 8 illustrate the same layer arrangement of the absorption plate and the beam structure, and the following embodiments will specifically illustrate the different layer arrangement of the absorption plate and the beam structure, specifically, the beam structure 22 is located at a side of the absorption plate 21 adjacent to the CMOS measurement circuitry 100, and the second pillar structure 50 is disposed between the absorption plate 21 and the beam structure 22, as shown in fig. 3, and the absorption plate 21 is used to convert the infrared signal into an electrical signal and is electrically connected to the corresponding first pillar structure 30 through the second pillar structure 50 and the corresponding beam structure 22.

Optionally, fig. 9 is a schematic exploded structure diagram of a beam structure provided in an embodiment of the present invention, fig. 10 is a schematic exploded structure diagram of an absorption plate provided in an embodiment of the present invention, and fig. 11 is a schematic cross-sectional structure diagram of a pixel of another infrared detector provided in an embodiment of the present invention, as shown in fig. 9, fig. 10, and fig. 11, a beam structure 22 includes a first supporting layer 220 and a first electrode layer 221, the first supporting layer 220 is located on a side of the first electrode layer 221 adjacent to the CMOS measurement circuit system 100, and a material constituting the first electrode layer 221 includes at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a second support layer 211 and a second passivation layer 212, the thermo sensitive layer 210 being located between the second support layer 211 and the second passivation layer 212, the second support layer 211 being located on a side of the second passivation layer 212 adjacent to the CMOS measurement circuitry 100.

Referring to fig. 9 to 11, the first support layer 220 of the beam structure 22 supports the first electrode layer 221 of the beam structure 22. The second support layer 211 of the absorber plate 21 provides support for the heat sensitive layer 210 on the absorber plate 21, and the second passivation layer 212 serves to protect the heat sensitive layer 210 from oxidation or corrosion.

Referring to fig. 10 and 11, the absorber plate 21 further comprises two patterned electrode structures 213, the patterned electrode structures 213 being electrically connected with the first electrode layer 221 via the second cylindrical structures 50, the patterned electrode structures 213 being adapted to transmit electrical signals converted out of the thermosensitive layer 210 to the corresponding beam structures 22 via the second cylindrical structures 50. Specifically, the thermosensitive layer 210 is used to convert a temperature signal into an electrical signal, the patterned electrode structure 213 on the absorption plate 21 is used to adjust the resistance of the thermosensitive layer 210, the patterned electrode structure 213 is electrically connected to the first electrode layer 221 through the second columnar structure 50, and the electrical signal converted and formed by the thermosensitive layer 210 is transmitted to the beam structure 22 through the second columnar structure 50 and is transmitted to the CMOS measurement circuit system 100 through the first electrode layer 221.

As shown in fig. 10 and 11, the absorber plate 21 further comprises a patterned electrode structure 213, the patterned electrode structure 213 is electrically connected to the first electrode layer 221 through the second cylindrical structure 50, and the patterned electrode structure 213 is used for transmitting an electrical signal converted out by the thermosensitive layer 210 to the corresponding beam structure 22 through the second cylindrical structure 50. Specifically, the thermal sensitive layer 210 is used to convert an infrared signal into an electrical signal, the patterned electrode structure 213 is electrically connected to the first electrode layer 221 through the second columnar structure 50, and the electrical signal converted and formed by the thermal sensitive layer 210 is transmitted to the beam structure 22 through the second columnar structure 50, and then transmitted to the CMOS measurement circuit system 100 through the first electrode layer 221, the first columnar structure 30 and the support base 12. Illustratively, the patterned electrode structure may have a serpentine shape of a reverse turn, the patterned electrode structure comprising two portions, each portion being electrically connected to each other, one portion for transmitting a positive electrical signal and one portion for transmitting a ground electrical signal.

When the beam structure 22 includes the first support layer 220 and the first electrode layer 221, the material forming the first electrode layer 221 is at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel or platinum, which can effectively improve the oxidation resistance of the first electrode layer 221 and reduce the thermal conductivity coefficient of the first electrode layer 221, so that a passivation layer is not required to be arranged on the beam structure 22, the thickness of the beam structure 22 is reduced, the thermal conductivity of the beam structure 121 is favorably reduced, and the thermal responsiveness of the infrared detector is improved.

It should be noted that, when the absorbing plate 21 is formed to include a three-layer structure including the second support layer 211, the thermal sensitive layer 210 and the second passivation layer 212, the patterned electrode structure 213 may be disposed on the same layer as the second passivation layer 212, or the patterned electrode structure 213 may be disposed on the same layer as the thermal sensitive layer 210. Illustratively, when the patterned electrode structure 213 and the second passivation layer 212 are disposed on the same layer, as shown in fig. 13 and 14, the patterned electrode structure 213, the second passivation layer 212, and the second support layer 211 form protection for the upper and lower surfaces and the side surfaces of the thermal sensitive layer 210, so as to avoid corrosion of the material of the thermal sensitive layer 210 by the gas-phase hydrogen fluoride when the structure is etched by the VHF gas-phase hydrogen fluoride etching process. In addition, the three-layer structure including the second support layer 211, the heat sensitive layer 210 and the second passivation layer 212 is arranged to form the absorption plate 21, so that the patterned electrode structure 213 and the second passivation layer 212 in the absorption plate 21 can be prepared and formed in the same process or the patterned electrode structure 213 and the heat sensitive layer 210 can be prepared in the same process, and the process complexity is reduced.

Optionally, fig. 12 is an exploded structural schematic view of another absorption plate provided in an embodiment of the present invention, fig. 13 is a cross-sectional structural schematic view of another infrared detector pixel provided in an embodiment of the present invention, and with reference to fig. 9, fig. 12, and fig. 13, the beam structure 22 includes a first supporting layer 220 and a first electrode layer 221, the first supporting layer 220 is located on a side of the first electrode layer 221 adjacent to the CMOS measurement circuit system 100, and a material constituting the first electrode layer 221 includes at least one of titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, silicon nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a second support layer 211, a second electrode layer 213 and a second passivation layer 212, the second electrode layer 213 and the thermo sensitive layer 210 being located between the second support layer 211 and the second passivation layer 212, the second support layer 211 being located on a side of the second passivation layer 212 adjacent to the CMOS measurement circuitry 100.

As shown in fig. 9, 12 and 13, when the beam structure 22 includes the first support layer 220 and the first electrode layer 221, the absorption plate 21 further includes the second support layer 211, the second electrode layer 213 and the second passivation layer 212, that is, the absorption plate 21 includes four layers of the second support layer 211, the second electrode layer 213, the thermal sensitive layer 210 and the second passivation layer 212, in this case, the second electrode layer 213 may be disposed on a side of the thermal sensitive layer 210 adjacent to the second support layer 211, or the second electrode layer 213 may be disposed on a side of the thermal sensitive layer 210 adjacent to the second passivation layer 212, and the embodiment of the present invention does not specifically limit the position of the second electrode layer 213. In addition, the second electrode layer 213 in the absorption plate 21 can be selectively disposed according to a specific manufacturing process, and process compatibility is good. In addition, the second electrode layer 213, the second passivation layer 212 and the second support layer 211 of the absorber plate 21 form protection for the upper surface, the lower surface and the side surface of the thermosensitive layer 210, and the patterned electrode structure 213, the second passivation layer 212 and the second support layer 211 form a corrosion protection structure, so that corrosion of the thermosensitive layer material by the gas-phase hydrogen fluoride is avoided when the structure is hollowed out by adopting a VHF gas-phase hydrogen fluoride corrosion process to corrode the sacrificial layer.

In addition, the three-layer structure including the second support layer 211, the heat sensitive layer 210 and the second passivation layer 212 is arranged to form the absorption plate 21, so that the patterned electrode structure 213 and the second passivation layer 212 in the absorption plate 21 can be prepared in the same process, or the patterned electrode structure 213 and the heat sensitive layer 210 are prepared in the same process, and the process complexity is reduced. And the beam structure comprises two layers of structures, namely a first supporting layer 220 and a first electrode layer 221, and a passivation layer is not required to be arranged on the beam structure 22, so that the thickness of the beam structure 22 is reduced, the thermal conduction of the beam structure 121 is favorably reduced, and the thermal responsivity of the infrared detector is improved.

Optionally, fig. 14 is a schematic exploded view of another beam structure provided in an embodiment of the present invention, fig. 15 is a schematic exploded view of another absorption plate provided in an embodiment of the present invention, fig. 16 is a schematic cross-sectional view of another infrared detector pixel provided in an embodiment of the present invention, and with reference to fig. 14 to fig. 16, a beam structure 22 includes a first supporting layer 220, a first electrode layer 221, and a first passivation layer 222, the first electrode layer 221 is located between the first supporting layer 220 and the first passivation layer 222, the first supporting layer 220 is located on a side of the first passivation layer 222 adjacent to the CMOS measurement circuit system 100, and a material constituting the first electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel chrome alloy, nickel platinum alloy, silicon nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a second support layer 211 and a second passivation layer 212, the thermo sensitive layer 210 being located between the second support layer 211 and the second passivation layer 212, the second support layer 211 being located on a side of the second passivation layer 212 adjacent to the CMOS measurement circuitry 100.

As shown in fig. 14 to 16, the beam structure 22 includes a first support layer 220, a first electrode layer 221, and a first passivation layer 222, and the absorption plate 21 includes a thermosensitive layer 210, a second support layer 211, and a second passivation layer 212.

As shown in fig. 15 and 16, the absorber plate 21 further includes a patterned electrode structure 213, the patterned electrode structure 213 is electrically connected to the first electrode layer 221 through the second columnar structure 50, and transmits an electrical signal formed by conversion of the thermosensitive layer 210 to the beam structure 22 through the second columnar structure 50 and to the CMOS measurement circuitry 100 through the first electrode layer 221. Specifically, the thermosensitive layer 210 is used to convert a temperature signal into an electrical signal, the patterned electrode structure 213 on the absorption plate 21 is used to adjust the resistance of the thermosensitive layer 210, and the electrical signal converted by the thermosensitive layer 210 is transmitted to the CMOS measurement circuitry 100 through the first electrode layer 221 on the beam structure 22. Illustratively, the material of the first electrode layer 221 constituting the beam structure 22 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum, and the material of the first electrode layer 221 is not particularly limited in the embodiments of the present invention.

When the absorber plate 21 is formed to include a three-layer structure of the second support layer 211, the heat sensitive layer 210 and the second passivation layer 212, and the beam structure 22 is formed to include a three-layer structure of the first support layer 220, the first electrode layer 221 and the first passivation layer 222, the patterned electrode structure 213 disposed on the absorber plate 21 is located at the same layer as the heat sensitive layer 210, and the heat sensitive layer 210 and the patterned electrode structure 213 are protected by the second passivation layer 212. Since the formed absorption plate 21 includes the three-layer structure and the formed beam structure 22 includes the three-layer structure, the beam structure 22 and the absorption plate 21 can be separately formed in the same manufacturing process, thereby reducing the process complexity. In addition, when the beam structure is configured to include three layers, i.e., the first support layer 220, the first electrode layer 221 and the first passivation layer 222, the first passivation layer 222 on the first electrode layer 221 can protect the first electrode layer 221, so that the first electrode layer 221 is not corroded, the mechanical strength of the beam structure 22 is enhanced, and further, more materials can be selected for the first electrode layer 221. Illustratively, the material of the first electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, silicon nickel alloy, nickel, or platinum.

Optionally, fig. 17 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention, and referring to fig. 12 and fig. 15 and fig. 17, the beam structure 22 includes a first supporting layer 220, a first electrode layer 221, and a first passivation layer 222, where the first electrode layer 221 is located between the first supporting layer 220 and the first passivation layer 222, the first supporting layer 220 is located on a side of the first passivation layer 222 adjacent to the CMOS measurement circuit system 100, and a material constituting the first electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum. The absorption plate 21 further comprises a second support layer 211, a second electrode layer 213 and a second passivation layer 212, the second electrode layer 213 and the thermo sensitive layer 210 being located between the second support layer 211 and the second passivation layer 212, the second support layer 211 being located on a side of the second passivation layer 212 adjacent to the CMOS measurement circuitry 100.

As shown in fig. 12, 15 and 17, the beam structure 22 includes a three-layer structure of a first support layer 220, a first electrode layer 221 and a first passivation layer 222, and the absorber plate 21 includes four-layer structures of a second support layer 211, a second electrode layer 213, a thermal sensitive layer 210 and a second passivation layer 212, where the second electrode layer 213 on the absorber plate 21 may be disposed on a side of the thermal sensitive layer 210 adjacent to the second passivation layer 212, and the second electrode layer 213 may also be disposed on a side of the thermal sensitive layer 210 adjacent to the second support layer 211. When the beam structure includes three layers, i.e., the first support layer 220, the first electrode layer 221 and the first passivation layer 222, the first passivation layer 222 on the first electrode layer 221 can protect the first electrode layer 221, so that the first electrode layer 221 is not corroded, the mechanical strength of the beam structure 22 is enhanced, and further, more materials can be selected for the electrode layer 221. Illustratively, the material of the first electrode layer 221 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum.

It should be noted that, in the infrared detector pixel provided in the foregoing embodiment, the thermosensitive layer and the supporting layer in the absorption plate are respectively located at different layers, and when the thermosensitive layer includes a thermosensitive material or a thermocouple material, the thermosensitive layer can be used as the supporting layer, that is, the thermosensitive layer is reused as the supporting layer, so that the thermosensitive layer serves as the second supporting structure, and a separate supporting film layer is not required to be manufactured, which is beneficial to further reducing the thickness of the absorption plate, further reducing the heat capacity of the absorption plate, and reducing the thermal response time of the infrared detector. In addition, the duty ratio of the absorption plate in each of the above embodiments is greater than 70%, even up to 90% or more, and the absorption plate may further include other structures, such as a metamaterial structure or a polarization structure, which is not specifically limited in the embodiments of the present invention.

Optionally, the heat-sensitive layer 210 includes a heat-sensitive structure, and corrosion protection structures are disposed on upper and lower surfaces and side surfaces of the heat-sensitive structure.

Because the material forming the heat-sensitive layer 210 comprises at least one of titanium oxide, vanadium oxide or titanium vanadium oxide, when the sacrificial layer is corroded by using the VHF gas-phase hydrogen fluoride corrosion process to realize hollow-out of the resonant cavity structure, the used hydrogen fluoride can corrode the heat-sensitive layer 210 in the absorption plate, and therefore by arranging the heat-sensitive layer 210 to comprise the heat-sensitive structure, and the upper surface, the lower surface and the side surface of the heat-sensitive structure are both provided with corrosion protection structures, the corrosion of hydrogen fluoride on the material of the heat-sensitive layer is avoided when the sacrificial layer is corroded by using the VHF gas-phase hydrogen fluoride corrosion process by using the corrosion protection structures to protect the material of the heat-sensitive layer.

Optionally, the material of the hermetic release insulating layer 40 includes at least one of silicon, germanium, silicon germanium, amorphous silicon, amorphous germanium, or amorphous silicon germanium, and the thickness of the hermetic release insulating layer 40 is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

The material forming the closed release isolation layer 40 comprises at least one of silicon, germanium, silicon germanium, amorphous silicon, amorphous germanium or amorphous silicon germanium, the thickness of the closed release isolation layer 40 is greater than or equal to 0.01 micrometer and less than or equal to 0.1 micrometer, so that the closed release isolation layer 40 hardly influences the reflection process in the resonant cavity, namely the reflection process of the resonant cavity is influenced by the closed release isolation layer 40, and further the influence of the closed release isolation layer 40 on the detection sensitivity of the CMOS infrared sensing structure 200 is avoided.

By way of example, in the foregoing embodiments, the material of the passivation layer may include at least one of amorphous carbon, amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or silicon carbide, and the material of the support layer includes at least one of amorphous carbon, amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or silicon carbide, and the materials of the passivation layer and the support layer are not specifically limited in the embodiments of the present invention.

Optionally, fig. 18 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention, and as shown in fig. 18, at least one hermetic release isolation layer 40 is located at an interface between the CMOS measurement circuitry 100 and the CMOS infrared sensing structure 200, and the supporting base is electrically connected to the CMOS measurement circuitry 100 through a through hole penetrating the hermetic release isolation layer located between the CMOS measurement circuitry 100 and the CMOS infrared sensing structure 200.

Illustratively, as shown in fig. 18, at least one hermetic release barrier layer 40 is located at the interface between the CMOS measurement circuitry 100 and the CMOS infrared sensing structure 200. For example, the hermetic release insulating layer 40 is located between the reflective layer 10 and the CMOS measurement circuitry 100, i.e., the hermetic release insulating layer 40 is located under the metal interconnection layer of the reflective layer 10, and the support base 12 is electrically connected to the CMOS measurement circuitry 100 through a through hole penetrating the hermetic release insulating layer 40. Specifically, since the CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 are both formed by using a CMOS process, after the CMOS measurement circuit system 100 is formed, a wafer including the CMOS measurement circuit system 100 is transferred to a next process to form the CMOS infrared sensing structure 200, since silicon oxide is a most commonly used dielectric material in the CMOS process, and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, and therefore, in order to release the silicon oxide of the sacrificial layer, the silicon oxide dielectric on the CMOS measurement circuit system is not corroded, and the hermetic release insulating layer 40 is provided. After the CMOS measurement circuit system 100 is prepared and formed, a closed release isolation layer 40 is prepared and formed on the CMOS measurement circuit system 100, the CMOS measurement circuit system 100 is protected by the closed release isolation layer 40, and in order to ensure the electrical connection between the support base 12 and the CMOS measurement circuit system 100, after the closed release isolation layer 40 is prepared and formed, a through hole is formed in a region of the closed release isolation layer 40 corresponding to the support base 12 by using an etching process, and the support base 12 is electrically connected with the CMOS measurement circuit system 100 through the through hole. In addition, the hermetic release isolation layer 40 and the support base 12 are arranged to form a hermetic structure, so as to completely separate the CMOS measurement circuit system 100 from the sacrificial layer, thereby protecting the CMOS measurement circuit system 100.

It should be noted that, when the hermetic release isolation layer 40 is located between the reflective layer 10 and the CMOS measurement circuitry 100, for example, the material constituting the hermetic release isolation layer 40 may include at least one of silicon, germanium, silicon germanium, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, or aluminum oxide, and the thickness of the hermetic release isolation layer 40 is greater than or equal to 1000A and less than or equal to 20000A. Specifically, silicon, germanium, silicon germanium, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, or aluminum oxide are all CMOS process corrosion resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 40 can be used to protect the CMOS measurement circuitry 100 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the close release isolation layer 400 is disposed to cover the CMOS measurement circuitry 100, and the close release isolation layer 40 may also be used to protect the CMOS measurement circuitry 100 from process effects during the etching process for fabricating the CMOS infrared sensing structure 200.

In addition, fig. 18 is a schematic structural view illustrating the absorption plate and the beam structure of the infrared conversion structure arranged in the same layer, and the absorption plate and the beam structure of the infrared conversion structure may be disposed in different layers.

Optionally, fig. 18 is a schematic cross-sectional structure diagram of a pixel of another infrared detector provided in an embodiment of the present invention, as shown in fig. 18, a CMOS manufacturing process of the CMOS measurement circuit system 100 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 100 includes metal interconnection layers 101 and dielectric layers 102 arranged at intervals, and a silicon substrate 103 located at the bottom, where the upper and lower metal interconnection layers 101 are electrically connected through vias 104.

The CMOS infrared sensing structure 200 includes a resonant cavity formed by a reflective layer and a heat sensitive dielectric layer, a suspended microbridge structure for controlling heat transfer, and a columnar structure 30 having electrical connection and support functions, and the CMOS measurement circuitry 100 is used to measure and process the array resistance value formed by one or more CMOS infrared sensing structures 200 and convert infrared signals into electrical image signals.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 10 and the absorbing plate, for example, the infrared light is reflected back and forth in the resonant cavity through the absorbing plate to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structure 30, the beam structure and the absorbing plate form a suspended micro-bridge structure for controlling the heat transfer, and the columnar structure 30 is electrically connected to the supporting base 12 and the corresponding beam structure, and is also used for supporting the infrared conversion structure 20 on the columnar structure.

Fig. 20 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present invention, and in conjunction with fig. 1 and fig. 20, the CMOS measurement circuit system 100 includes a bias generation circuit 701, a column-level analog front-end circuit 801 and a row-level circuit 901, an input terminal of the bias generation circuit 701 is connected to an output terminal of the row-level circuit 901, an input terminal of the column-level analog front-end circuit 801 is connected to an output terminal of the bias generation circuit 701, the row-level circuit 901 includes a row-level mirror image pixel Rsm and a row selection switch K1, and the column-level analog front-end circuit 801 includes a blind pixel RD; the row-level circuit 901 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing generation circuit, and outputs a current signal to the column-level analog front-end circuit 801 under the action of the bias generation circuit 701 to perform current-voltage conversion output; the row stage circuit 901 outputs a third bias voltage VRsm to the bias generation circuit 701 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 701 outputs a first bias voltage V1 and a second bias voltage V2 according to an input constant voltage and the third bias voltage VRsm, and the column stage analog front end circuit 801 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on a difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row stage circuit 901 includes a row stage mirror image element Rsm and a row selection switch K1, and the row stage circuit 901 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a shading process, so that the row-level image elements Rsm are subjected to a fixed radiation of a shading sheet with a temperature constantly equal to the substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 701, that is, the row-level circuit 901 outputs the third bias voltage VRsm to the bias generation circuit 701 when being controlled by the row selection switch K1 to be turned on. The bias generating circuit 701 may include a first bias generating circuit 71 and a second bias generating circuit 72, the first bias generating circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 801 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed in correspondence with the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed in one-to-one correspondence with the gate driving sub-circuits 722, and the gate driving sub-circuits 722 are configured to supply the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 801 includes an effective pixel RS and a blind pixel RD, the column control sub-circuit is configured to generate a first current I1 according to a first bias voltage V1 and the blind pixel RD, generate a second current I2 according to a second bias voltage V2 and the effective pixel RS, perform transimpedance amplification on a difference between the first current I1 and the second current I2, and output the amplified difference, where the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 100 and are shaded, which are subjected to fixed radiation from a shade plate at a temperature substantially equal to the substrate temperature. The absorption plate of the effective pixel RS is thermally insulated from the CMOS measurement circuitry 100, and the effective pixel RS receives external radiation. The absorbing plates of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measurement circuitry 100, and thus both the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the row selection switch K1 is used for gating the corresponding row-level mirror image element Rsm, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective pixel RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective pixel RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective pixel RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective pixel RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective pixel RS are the same under the same environmental temperature, the change of the row-level mirror image element Rsm and the effective pixel RS are synchronous, the resistance value change of the row-level mirror image element Rsm and the effective pixel RS under the same environmental temperature is favorably compensated, and the stable output of the reading circuit is realized.

In addition, by arranging the second bias generating circuit 701 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate corresponding second bias voltages V2 respectively according to the row control signal, so that each row of pixels has one path to drive the entire columns of pixels in the row separately, the requirement for the second bias voltages V2 is reduced, that is, the driving capability of the bias generating circuit 701 is improved, and the readout circuit is advantageously used to drive a larger-scale infrared detector pixel array. In addition, the specific details of the CMOS measurement circuitry 100 are well known to those skilled in the art and will not be described herein.

In addition, referring to fig. 21, the CMOS infrared sensing structure 200 is prepared on the same layer as the metal interconnection layer of the CMOS measurement circuitry 100, that is, the CMOS measurement circuitry 100 and the CMOS infrared sensing structure 200 are arranged on the same layer, the CMOS infrared sensing structure 200 is arranged on one side of the CMOS measurement circuitry 100, and the top of the CMOS measurement circuitry 100 may also be provided with a hermetic release isolation layer 40 to protect the CMOS measurement circuitry 100.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit.

Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measurement circuit system 100 and the CMOS infrared sensing structure 200 are both prepared by using a CMOS process, the CMOS infrared sensing structure 200 is directly prepared on the CMOS measurement circuit system 100, the radial side length of the columnar structure 30 is more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure, namely the width of a single line in the beam structure is less than or equal to 0.3um, the height of the resonant cavity is more than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel of the CMOS infrared sensing structure 200 is more than or equal to 6um and less than or equal to 17um.

Optionally, on the basis of the above embodiment, an infrared detector is further provided in the embodiment of the present invention, and fig. 22 is a schematic perspective view of an infrared detector provided in the embodiment of the present disclosure. As shown in fig. 22, the infrared detector includes a plurality of infrared detector pixels 01 according to the above embodiment, and therefore, the infrared detector provided in the embodiment of the present disclosure has the beneficial effects described in the above embodiment, which are not described herein again. Illustratively, the type of the infrared detector may be an amorphous silicon detector, a titanium oxide detector, a vanadium oxide or titanium vanadium oxide detector, etc., i.e., the material constituting the thermosensitive layer may include at least one of amorphous silicon, titanium oxide, vanadium oxide or titanium vanadium oxide, and the specific type of the infrared detector is not limited in the embodiments of the present invention.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared detector pixel based on a CMOS process, comprising:

the infrared conversion structure comprises an absorption plate and a plurality of beam structures, the absorption plate is used for converting infrared signals into electric signals and is electrically connected with the corresponding first columnar structures through the corresponding beam structures, the absorption plate comprises a heat-sensitive layer, the heat-sensitive layer is made of at least one of titanium oxide, vanadium oxide or titanium vanadium oxide, the material is perpendicular to the extending direction of the beam structures, and the width of the beam structures is less than or equal to 0.3 micrometer;

the material for forming the sacrificial layer in the infrared detector comprises silicon oxide, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the sacrificial layer is corroded by a post-CMOS process, and the sacrificial layer is corroded by at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane in the post-CMOS process;

the closed release isolation layer is located above the reflection layer and covers all side walls of the first columnar structure so as to improve the stability of the first columnar structure, reduce the contact resistance between the first columnar structure and the external environment, reduce the release difficulty of the sacrificial layer and realize the protection of the CMOS measurement circuit system.

2. The CMOS process-based infrared detector pixel of claim 1, wherein said absorber plate and said beam structure are on the same layer.

3. The CMOS process based infrared detector pixel according to claim 2, wherein the beam structure comprises a support layer and an electrode layer, the support layer is located on a side of the electrode layer adjacent to the CMOS measurement circuitry, and a material constituting the electrode layer comprises at least one of titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, silicon nickel alloy, nickel, or platinum; alternatively, the first and second electrodes may be,

4. The CMOS process-based infrared detector pixel according to claim 3, wherein said absorber plate further comprises a support layer and a passivation layer, said thermal sensitive layer being located between said support layer and said passivation layer, said support layer being located on a side of said passivation layer adjacent to said CMOS measurement circuitry; alternatively, the first and second electrodes may be,

5. The CMOS process-based infrared detector pixel according to claim 1, wherein the beam structure is located on a side of the absorber plate adjacent to the CMOS measurement circuitry, and a second pillar structure is disposed between the absorber plate and the beam structure, and the absorber plate is configured to convert an infrared signal into an electrical signal and electrically connect to the corresponding first pillar structure through the second pillar structure and the corresponding beam structure.

6. The CMOS process based infrared detector pixel of claim 5, wherein said beam structure comprises a first support layer and a first electrode layer, said first support layer is located on a side of said first electrode layer adjacent to said CMOS measurement circuitry, and a material comprising said first electrode layer comprises at least one of titanium tungsten, nickel chromium, nickel platinum, silicon nickel, or platinum.

7. The CMOS process-based infrared detector pixel according to claim 6, wherein said absorber plate further comprises a second support layer and a second passivation layer, said thermal sensitive layer being located between said second support layer and said second passivation layer, said second support layer being located on a side of said second passivation layer adjacent to said CMOS measurement circuitry; alternatively, the first and second electrodes may be,

8. The CMOS process-based infrared detector pixel of claim 5, wherein said beam structure comprises a first support layer, a first electrode layer and a first passivation layer, said first electrode layer is located between said first support layer and said first passivation layer, said first support layer is located on a side of said first passivation layer adjacent to said CMOS measurement circuitry, and a material comprising said first electrode layer comprises at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel, or platinum.

9. The CMOS process-based infrared detector pixel according to claim 8, wherein said absorber plate further comprises a second support layer and a second passivation layer, said thermal sensitive layer being located between said second support layer and said second passivation layer, said second support layer being located on a side of said second passivation layer adjacent to said CMOS measurement circuitry; alternatively, the first and second electrodes may be,

the absorption plate further comprises a second supporting layer, a second electrode layer and a second passivation layer, the second electrode layer and the heat-sensitive layer are located between the second supporting layer and the second passivation layer, the second supporting layer is located on one side, close to the CMOS measuring circuit system, of the second passivation layer, and materials forming the second electrode layer comprise at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, silicon-nickel alloy, nickel or platinum.

10. The CMOS process-based infrared detector pixel according to any one of claims 2 to 9, wherein the thermal sensitive layer comprises a thermal sensitive structure, and corrosion protection structures are provided on upper and lower surfaces and on side surfaces of the thermal sensitive structure.

11. An infrared detector based on a CMOS process, characterized by comprising a plurality of infrared detector pixels based on a CMOS process according to any one of claims 1 to 10.