CN113690321B - 一种碳化硅沟槽栅mosfet及其制造方法 - Google Patents
一种碳化硅沟槽栅mosfet及其制造方法 Download PDFInfo
- Publication number
- CN113690321B CN113690321B CN202111239940.2A CN202111239940A CN113690321B CN 113690321 B CN113690321 B CN 113690321B CN 202111239940 A CN202111239940 A CN 202111239940A CN 113690321 B CN113690321 B CN 113690321B
- Authority
- CN
- China
- Prior art keywords
- epitaxial
- region
- current diffusion
- trench gate
- doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 139
- 238000002347 injection Methods 0.000 claims abstract description 89
- 239000007924 injection Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000007480 spreading Effects 0.000 claims description 8
- 238000003892 spreading Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000009825 accumulation Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 18
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 210000004027 cell Anatomy 0.000 description 152
- 238000010586 diagram Methods 0.000 description 27
- 238000002513 implantation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001994 activation Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供了一种碳化硅沟槽栅MOSFET及其制造方法,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上方具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和楼电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部。合理设置注入型电流扩散区,能够限制器件的饱和电流,同时能分离电场峰值和电流位置的位置,降低发热功率,增大器件的短路能力。
Description
技术领域
本发明涉及一种半导体器件,尤其涉及一种碳化硅沟槽栅MOSFET及其制造方法。
背景技术
传统硅基半导体器件的性能已经逐渐接近材料的物理极限,而采用以SiC材料的第三代功率半导体器件因其优异的高频、高压、导热能力强等特性在高功率密度和高效率装置中具有强大的吸引力。SiC MOSFET器件因其驱动容易以及开关频率高的特性,在电动汽车、光伏逆变等应用场景中逐步使用。SiC MOSFET器件主要右平面栅双扩散SiC MOSFET以及沟槽栅MOSFET。相比较平面栅MOSFET,沟槽栅MOSFET消除了JFET区电阻,同时具有较高的沟道密度,这使得器件的通态特征电阻显著减小。同时因材料晶向的原因,沟槽侧壁具备了较为优异的沟道电子迁移率。
然而,SiC沟槽MOSFET器件在实际制作和应用中仍然存在几个问题:(1)SiC漂移区的高电场导致栅介质上的电场很高,这个问题在槽角处加剧,从而在高漏极电压下造成栅介质迅速击穿;(2)由于沟槽MOSFET的导通电阻较小,导致其在发生短路时电路电流较大,器件发热严重,短路能力相比平面栅MOSFET较弱。因此需要对结构进行优化来避免栅槽底部的提前击穿。图1结构中所述传统沟槽栅型SiC MOSFET元胞采用底部注入第二掺杂类型(例如P型)的方式来保护栅介质。其结构包括具有第一掺杂类型的碳化硅衬底区域001,具有第一掺杂类型(例如N型)的碳化硅外延区域002,具有第二掺杂类型的碳化硅外延阱区003,具有第二掺杂类型的源接触区004,具有第一掺杂类型的源接触区005,沟槽栅介质006,具有第二掺杂类型的电场屏蔽区007(一般为重掺杂P型区域),沟槽栅电极008,漏电极010,源电极011。所述传统沟槽栅型MOSFET器件导通时(沟槽栅电极008施加正电压,例如10~20V,漏电极010施加正电压,例如0-20V,源电极011施加零电压,例如0V)的电流路径如图2中Ia所示,在沟槽两侧形成沟道009,用于控制器件的开关。目前经典沟槽MOSFET结构能缓解槽角处电场,但不能改善其短路能力。
发明内容
为了解决上述现有情况下的问题,本发明提出一种碳化硅沟槽栅MOSFET及其制造方法。
根据本发明一实施例提出一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上方具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度,所述注入型电流扩散区与所述外延阱区直接接触,所述外延阱区的底部低于沟槽栅底部。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;以及形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区,所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度,所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接,所述外延保护区的底部低于沟槽栅底部。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;以及形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区,所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度,所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接,所述外延保护区的底部低于沟槽栅底部;以及形成于外延保护区上方、外延阱区内的具有第一掺杂类型的外延电流扩散区,所述外延电流扩散区与沟槽栅两侧侧壁直接接触。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET的制造方法,其特征在于,所述制造方法包括:在衬底上形成外延层;在外延层上形成外延阱区;形成第一源接触区;形成第二源接触区;在半导体表面刻蚀沟槽;利用沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;在沟槽表面形成栅介质;在沟槽内部填充栅电极;以及形成漏电极和源电极;其中衬底、外延层、第一源接触区、注入型电流扩散区具有第一掺杂类型,外延阱区、第二源接触区具有第二掺杂类型。
本发明具有以下有益技术效果:
1、相比于传统的沟槽栅底部设置具有第二掺杂类型(例如P型)的保护区的MOSFET,本发明具有第一掺杂类型(例如N型)的凹型形状的注入型电流扩散区的MOSFET的有效漂移区厚度更大,击穿电压更高,同时具有注入型电流扩散区的MOSFET能提供的额外的积累层的通道,降低导通电阻。合理设置注入型电流扩散区,能够限制器件的饱和电流,同时能分离电场峰值和电流峰值的位置,降低发热功率,增大器件的短路能力;
2、设置注入型电流扩散区的形状为包裹沟槽栅底部的凹型形状,例如U型、V型、多边形或圆角矩形等,在工艺上实现便于垂直注入形成电流扩散区,降低工艺难度;
3、在注入型电流扩散区内、沟槽栅底部中间位置形成P型屏蔽区,可有效降低栅介质的电场;
4、在注入型电流扩散区两侧、外延阱区底部形成外延保护区,能有效降低栅介质电场,同时对器件的短路电路能起到较好地抑制作用;
5、在外延保护区上、外延阱区下形成外延电流扩散区,能使得器件的电流得到扩散,同时能使得沟槽栅的角落更稳定地被N型掺杂包围;所述外延电流扩散区底部不高于沟槽栅底部,所述外延电流扩散区顶部高于沟槽栅底部;
6、除了设置第二源接触区外,还可在外延电流扩散区外侧、外延保护区上方设置第三源接触区1041,可以具有与第二源接触区104相同的掺杂类型和掺杂浓度(例如第二掺杂类型P型),起到缓冲电路的作用,降低电压尖峰;
7、在工艺流程中,可以利用刻蚀沟槽的掩膜通过离子注入形成注入型电流扩散区,实际过程中可以利用注入工艺的弹射和掺杂离子激活工艺中的扩散能力形成包裹角落的注入型电流扩散区。在本实施例中,由于注入型电流扩散区需要高剂量注入(一实施例中需高于外延阱区浓度,另一实施例中需高于外延保护区浓度),因此会在角落处注入离子发生弹射,更容易聚集掺杂离子,形成包裹角落的状态。相比沟槽两侧注入P型区保护栅介质的方案,能避免使用高能离子注入。相比传统结构,本实施例以及匹配的工艺不会浪费外延层厚度,可以使用更薄的外延层达到相同的耐压,以达到更优化的器件特性。
附图说明
图1为传统碳化硅沟槽栅MOSFET器件元胞000的结构示意图;
图2为传统碳化硅沟槽栅MOSFET器件元胞000在导通状态下电流通路示意图;
图3为本发明碳化硅沟槽栅MOSFET器件第一元胞100的结构示意图;
图4为本发明碳化硅沟槽栅MOSFET器件第一元胞100在正向导通状态下的电流通路及内部状态变化图;
图5为根据本发明第一元胞100衍生出的碳化硅多边形沟槽栅MOSFET器件第二元胞200的结构示意图;
图6为根据本发明第一元胞100衍生出的碳化硅圆角矩形沟槽栅MOSFET器件第三元胞300的结构示意图;
图7为根据本发明第一元胞100衍生出的碳化硅U型沟槽栅MOSFET器件第四元胞400的结构示意图;
图8为根据本发明第一元胞100衍生出具有分立沟槽栅MOSFET器件第五元胞500的结构示意图;
图9为根据本发明第二元胞200衍生出具有分立沟槽栅MOSFET器件第六元胞600的结构示意图;
图10为根据本发明第三元胞300衍生出具有分立沟槽栅MOSFET器件第七元胞700的结构示意图;
图11为根据本发明第四元胞400衍生出具有分立沟槽栅MOSFET器件第八元胞800的结构示意图;
图12为根据本发明第一元胞100衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件第九元胞900结构示意图;
图13为根据本发明第二元胞200衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十元胞1000示意图;
图14为根据本发明第三元胞300衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十一元胞1100示意图;
图15为根据本发明第四元胞400衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十二元胞1200示意图;
图16为根据本发明第一元胞100衍生出具有外延保护区的沟槽栅第十三元胞1300示意图;
图17为根据本发明第二元胞200衍生出具有外延保护区的沟槽栅第十四元胞1400结构示意图;
图18为根据本发明第三元胞300衍生出具有外延保护区的沟槽栅第十五元胞1500结构示意图;
图19为根据本发明第四元胞400衍生出具有外延保护区的沟槽栅第十六元胞1600结构示意图;
图20为根据本发明第十三元胞1300衍生出具有外延电流扩散区的沟槽栅第十七元胞1700结构示意图;
图21为根据本发明第十四元胞1400衍生出具有外延电流扩散区的沟槽栅第十八元胞1800结构示意图;
图22为根据本发明第十五元胞1500衍生出具有外延电流扩散区的沟槽栅第十九元胞1900结构示意图;
图23为根据本发明第十六元胞1600衍生出具有外延电流扩散区的沟槽栅第二十元胞2000结构示意图;
图24为根据本发明第十七元胞1700衍生出第三源接触区的沟槽栅第二十一元胞2100示意图;
图25为根据本发明第十八元胞1800衍生出第三源接触区的沟槽栅第二十二元胞200示意图;
图26为根据本发明第十九元胞1900衍生出第三源接触区的沟槽栅第二十三元胞2300示意图;
图27为根据本发明第二十元胞2000衍生出第三源接触区的沟槽栅第二十四元胞2400示意图;
图28为本发明一实施例的碳化硅沟槽型MOSFET器件的工艺制作流程示意图2500。
具体实施方式
下面将结合附图详细描述本发明的具体实施例,应当注意,这里描述的实施例只用于举例说明,并不用于限制本发明。在以下描述中,为了便于对本发明的透彻理解,阐述了大量特定细节。然而,本领域普通技术人员可以理解,这些特定细节并非为实施本发明所必需。此外,在一些实施例中,为了避免混淆本发明,未对公知的电路、材料或方法做具体描述。
在整个说明书中,对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着:结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此,在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外,可以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外,本领域普通技术人员应当理解,在此提供的附图均是为了说明的目的,其中相同的附图标记指示相同的元件,但不限于元件结构必须完全相同。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
本发明所指的第一掺杂类型与第二掺杂类型相反,当第一掺杂类型为N型时,第二掺杂类型为P型,当第一掺杂类型为P型时,第二掺杂类型为N型。本发明所指掺杂类型包括但不限于P型掺杂或N型掺杂。本发明所指的凹型不限于图3或图4所示的结构,也可以是V型、U型、多边形、圆角矩形等凹型。
本发明公开的碳化硅沟槽型MOSFET器件第一元胞100结构如图3所示。其元胞结构包括:具有第一掺杂类型(例如N型)的衬底101;形成在衬底101上的具有第一掺杂类型的外延层102;形成在外延层102上方具有第二掺杂类型(例如P型)的外延阱区103,在一个实施例中,形成在外延层102上方可以是直接在外延层102上与外延层102接触,也可以是指在外延层102上方不直接与外延层102接触(例如中间还设置有其它区域);形成在外延阱区103内的具有第一掺杂类型的第一源接触区105;形成在外延阱区103内的具有第二掺杂类型的第二源接触区104,第二源接触区104与第一源接触区105可以毗邻;沟槽栅168,包括栅介质106和形成在栅介质106上的栅电极108(可以为多晶硅填充);包围在沟槽栅168底部(或者底部及底部侧面)的具有第一掺杂类型的注入型电流扩散区107,在一个实施例中,注入型电流扩散区107呈凹型包围在栅介质106底部及底部侧面,且注入型电流扩散区107的底部不高于外延阱区103的底部以保证器件能正常正向导通,所述注入型电流扩散区107的掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度;漏电极111和源电极112。碳化硅沟槽型MOSFET器件在正向导通的状态下的电流Ib的导通电流路径如如图4中带箭头的虚线所示,其中箭头指向为电流Ib的流向,在一个实施例中,在栅电极108上施加正电压(例如10~20V),漏电极111上施加正电压(例如0~20V),源电极112接地,在此状态下所述碳化硅沟槽型MOSFET器件在沟槽栅168两侧形成沟道109,在沟槽栅底部两侧角落形成积累区110,电流从漏电极111经衬底101、外延层102、注入型电流扩散区107、积累区110、沟道109、第一源接触区105流向源电极112。在另一个实施例中,存在一种器件经受大电流高电压的极端情况,当碳化硅沟槽型MOSFET器件处于高压阻断的情况下(例如阻断电压600V情况下),栅电极108上的电压变高(例如20V),沟道109打开,器件导通,此时器件会因为耗尽区的存在出现高电场,同时因为导通而存在大电流使得出现短路情况,其中电场峰值在沟槽栅168底部的栅介质106的中心位置,电流Ib峰值在沟槽栅168两侧,而第一元胞100的这种结构能在短路过程中减小发热。
请参考图5,根据本发明第一元胞100衍生出的碳化硅多边形沟槽栅MOSFET的第二元胞200。与第一元胞100的区别在于,第二元胞200具有多边形的沟槽栅168(包括多边形的栅介质106和栅电极108)以及多边形的注入型电流扩散区107。第二元胞200倾斜的沟槽栅168能便于垂直注入形成所述注入型电流扩散区107。
请参考图6,根据本发明第一元胞100衍生出的碳化硅圆角矩形沟槽栅MOSFET的第三元胞300结构,与第一元胞100的区别在于,第三元胞300具有圆角矩形的沟槽栅168(包括圆角矩形的栅介质106和栅电极108)以及圆角矩形的注入型电流扩散区107。第三元胞300圆角矩形的沟槽栅168能便于垂直注入形成注入型电流扩散区107。
请参考图7,根据本发明第一元胞100衍生出的碳化硅U型沟槽栅MOSFET的第四元胞400结构。与第一元胞100的区别在于,第四元胞400结构具有U型的沟槽栅168(包括U型的栅介质106和栅电极108)以及U型的注入型电流扩散区107。第四元胞400的U型沟槽栅168能便于垂直注入形成注入型电流扩散区107。
请参考图8,根据本发明第一元胞100衍生出的碳化硅分立沟槽栅MOSFET的第五元胞500结构。与第一元胞100的区别在于,第五元胞500包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积,能有效降低栅-漏的电容。
请参考图9,根据本发明第二元胞200衍生出的碳化硅分立沟槽栅MOSFET的元胞的第六元胞600结构。与第二元胞200的区别在于,第六元胞600包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积,能有效降低栅-漏的电容。
请参考图10,根据本发明第三元胞300衍生出的碳化硅分立沟槽栅MOSFET的第七元胞700结构。与第三元胞300的区别在于,第七元胞700包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积,能有效降低栅-漏的电容。
请参考图11,根据本发明第四元胞400衍生出的碳化硅分立沟槽栅MOSFET的第八元胞800结构。与第四元胞400的区别在于,第八元胞800包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积,能有效降低栅-漏的电容。
请参考图12,根据本发明第一元胞100衍生出的碳化硅沟槽栅MOSFET的第九元胞900结构。与第一元胞100的区别在于,第九元胞900还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901,所述屏蔽区901的注入深度连续可调,能有效地降低栅介质的电场。
请参考图13,根据本发明第二元胞200衍生出的碳化硅沟槽栅MOSFET的第十元胞1000结构。与第二元胞200的区别在于,第十元胞1000还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901,所述屏蔽区901的注入深度连续可调,能有效地降低栅介质的电场。
请参考图14,根据本发明第三元胞300衍生出的碳化硅沟槽栅MOSFET的第十一元胞1100。与第三元胞300的区别在于,第十一元胞1100还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901,所述屏蔽区901的注入深度连续可调,能有效地降低栅介质的电场。
请参考图15,根据本发明第四元胞400衍生出的碳化硅沟槽栅MOSFET的第十二元胞1200。与第四元胞400的区别在于,第十二元胞1200还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901,所述屏蔽区901的注入深度连续可调,能有效地降低栅介质的电场。
图4至图15所示实施例中,所述注入型电流扩散区107与所述外延阱区103直接接触(例如所述注入型电流扩散区107两侧与所述外延阱区103直接接触),所述外延阱区103的底部低于沟槽栅168底部,以保证器件正向导通工作时,沟道形成于沟槽栅侧壁的外延阱区103中,并且沟道中载流子进入注入型电流扩散区。
请参考图16,根据本发明第一元胞100衍生出的碳化硅沟槽栅MOSFET的第十三元胞1300结构。与第一元胞100的区别在于,所述第十三元胞1300还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302,所述外延保护区1302具有第二掺杂类型,其掺杂浓度(例如1×1018cm-3~3×1018cm-3)高于所述外延阱区103的掺杂浓度(例如1×1017cm-3~1×1018cm-3)。外延保护区1302能有效降低栅介质电场,同时对器件的短路电路能起到较好地抑制作用。
请参考图17,根据本发明第二元胞200衍生出的碳化硅沟槽栅MOSFET的第十四元胞1400结构。与第二元胞200的区别在于,第十四元胞1400还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302,所述外延保护区1302具有第二掺杂类型,其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场,同时对器件的短路电路能起到较好地抑制作用。
请参考图18,根据本发明第三元胞300衍生出的碳化硅沟槽栅MOSFET的第十五元胞1500结构。与第三元胞300的区别在于,第十五元胞1500还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302,所述外延保护区1302具有第二掺杂类型,其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场,同时对器件的短路电路能起到较好地抑制作用。
请参考图19,根据本发明第四元胞400衍生出的碳化硅沟槽栅MOSFET的第十六元胞1600结构。与第四元胞400的区别在于,第十六元胞1600还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302,所述外延保护区1302具有第二掺杂类型,其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场,同时对器件的短路电路能起到较好地抑制作用。
图16至图19所示实施例中,所述注入型电流扩散区107的底部不高于外延阱区103的底部,掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度,所述外延保护区1302的掺杂浓度高于所述外延阱区103的掺杂浓度。所述注入型电流扩散区107通过所述外延保护区1302与所述外延阱区103连接(例如注入型电流扩散区107两侧与所述外延保护区1302直接接触),所述注入电流扩散区107两侧上方角落处可以与所述外延阱区103直接接触,所述外延保护区1302的底部低于沟槽栅168底部,以保证器件正向导通工作时,沟道形成于沟槽栅168侧壁的外延阱区103中,并且沟道中载流子进入注入型电流扩散区107。
请参考图20,根据本发明第十三元胞1300衍生出的碳化硅沟槽栅MOSFET的第十七元胞1700结构。与第十三元胞1300的区别在于,第十七元胞1700还包括形成于外延保护区1302上方、外延阱区103内的外延电流扩散区1701,所述外延电流扩散区1701具有第一掺杂类型(例如N型掺杂浓度为1×1016cm-3~3×1017cm-3)。外延电流扩散区1701不仅能使得器件的电流得到扩散,同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型(例如N型)包围,同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触,能抑制动态电阻并保护栅介质106。
请参考图21,根据本发明第十四元胞1400衍生出的碳化硅沟槽栅MOSFET的第十八元胞1800结构。与第十四元胞1400的区别在于,第十八元胞1800还包括形成于外延保护区1302上方、外延阱区103内的外延电流扩散区1701,所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散,同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型(例如N型)包围,同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触,能抑制动态电阻并保护栅介质106。
请参考图22,根据本发明第十五元胞1500衍生出的碳化硅沟槽栅MOSFET的第十九元胞1900。与第十五元胞1500的区别在于,第十九元胞1900还包括形成于外延保护区1302上方外延阱区103内的外延电流扩散区1701,所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散,同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型(例如N型)包围,同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触,能抑制动态电阻并保护栅介质106。
请参考图23,根据本发明第十六元胞1600衍生出的碳化硅沟槽栅MOSFET的第二十元胞2000结构。与第十六元胞1600的区别在于,第二十元胞2000还包括形成于外延保护区1302上方外延阱区103内的外延电流扩散区1701,所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散,同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型(例如N型)包围,同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触,能抑制动态电阻并保护栅介质106。
请参考图24,根据本发明第十七元胞1700衍生出的碳化硅沟槽栅MOSFET的第二十一元胞2100结构。与第十七元胞1700的区别在于,第二十一元胞2100除了包括第二源接触区104外,还包括形成于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041,可以具有与第二源接触区104相同的掺杂类型和掺杂浓度(例如第二掺杂类型P型),起到缓冲电路的作用,降低电压尖峰。
请参考图25,根据本发明第十八元胞1800衍生出的碳化硅沟槽栅MOSFET的第二十二元胞2200结构。与第十八元胞1800的区别在于,第二十二元胞2200除了包括第二源接触区104外,还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041,可以具有与第二源接触区104相同的掺杂类型和掺杂浓度(例如第二掺杂类型P型),起到缓冲电路的作用,降低电压尖峰。
请参考图26,根据本发明第十九元胞1900衍生出的碳化硅沟槽栅MOSFET的第二十三元胞2300。与第十九元胞1900的区别在于,第二十三元胞2300除了包括第二源接触区104外,还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041,可以具有与第二源接触区104相同的掺杂类型和掺杂浓度(例如第二掺杂类型P型),起到缓冲电路的作用,降低电压尖峰。
请参考图27,根据本发明第二十元胞2000衍生出的碳化硅沟槽栅MOSFET的第二十四元胞2400。与第二十元胞2000的区别在于,第二十四元胞2400除了包括第二源接触区104外,还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041,可以具有与第二源接触区104相同的掺杂类型和掺杂浓度(例如第二掺杂类型P型),起到缓冲电路的作用,降低电压尖峰。
图20至图27所示实施例中,所述注入型电流扩散区107的底部不高于外延阱区103的底部,掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度,所述外延保护区1302的掺杂浓度高于所述外延阱区103的掺杂浓度。所述注入型电流扩散区107通过所述外延保护区1302和所述外延电流扩散区1701与所述外延阱区103连接(例如注入型电流扩散区107两侧与所述外延保护区1302直接接触,注入型电流扩散区107两侧上方角落处可以与所述外延电流扩散区1701直接接触),所述外延保护区1302的底部低于沟槽栅168底部,以保证器件正向导通工作时,沟道形成于沟槽栅168侧壁的外延阱区103中,并且沟道中载流子进入注入型电流扩散区107。
综合图3至图27所示实施例,所述注入型电流扩散区107可以与所述外延阱区103直接接触,也可以通过外延保护区1302或外延保护区1302和外延电流扩散区1701与所述外延阱区103连接,以保证器件正向导通工作时,沟道形成于沟槽栅侧壁的外延阱区103中,并且沟道中载流子进入注入型电流扩散区107。
图28为根据本发明实施例的制作如图3所示的碳化硅沟槽栅MOSFET器件的流程图。制作方法包括步骤S1-S9。
步骤S1,在衬底101上方形成外延层102(例如在衬底101表面生长外延层102)。衬底101与外延层102均具有第一掺杂类型,衬底101的掺杂浓度高于外延层102的掺杂浓度。
步骤S2,在外延层102上方形成外延阱区103(例如在外延层102表面生长外延阱区103)。如果需要制作类似如图16所示的包括外延保护区1302的碳化硅沟槽栅MOSFET器件,则可以先在外延层表面生长外延保护区1302,然后在外延保护区1302表面继续生长外延阱区。如果需要制作类似如图24所示的包括外延电流扩散区1701的碳化硅沟槽栅MOSFET器件,则可以先在外延保护区1302表面生长外延电流扩散区1701,再在外延电流扩散区1701表面生长外延阱区。采用外延的方式形成具有第二掺杂类型的外延保护区1302,激活率易于控制,并且避免了沟道左右两侧第二掺杂类型的高能注入,易于实现结构。
步骤S3,形成第一源接触区105,例如在半导体表面通过注入形成第一源接触区105。
步骤S4,形成第二源接触区104,例如在半导体表面通过注入形成第二源接触区104。当制作类似如图24所示的包括第三源接触区1041的碳化硅沟槽栅MOSFET器件时,可以通过一次离子注入同时形成第二源接触区104和第三源接触区1041。
步骤S5,在半导体表面刻蚀沟槽068。在一个实施例中,控制沟槽068顶部倾斜角度小于5°,沟槽底部为凹型(可为V型、U型或圆角矩形等)。在一种实施例中,沟槽068停止在具有第二掺杂类型的外延阱区103中;在另一种实施例中,沟槽068停止在具有第二掺杂类型的外延保护区1302中;在另一个实施例中,沟槽068停止在具有第一掺杂类型的外延电流扩散区1701中。
步骤S6,利用沟槽的掩膜离子注入形成注入型电流扩散区107,例如利用沟槽的掩膜使用第一掺杂的离子进行离子注入,形成注入型电流扩散区107。在一个实施例中,利用注入工艺的弹射和掺杂离子的扩散能力,形成包裹沟槽底部的注入型电流扩散区107。相比传统方法,该结构和工艺不会浪费外延层厚度,可以使用更薄的外延层达到耐压,以达到更优化的器件特性;相比沟槽两侧注入P型区保护栅介质的方案,能避免使用高能离子注入。
步骤S7,在沟槽068表面形成栅介质106。在一个实施例中,可以通过高温氧化以及CVD/PVD/ALD的工艺形成栅介质106。
步骤S8,在沟槽068内部填充栅电极108。在一个实施例中,所述栅电极108为多晶硅。
步骤S9,形成漏电极111和源电极112。在一个实施例中,可以通过金属溅射和欧姆接触形成漏电极111和源电极112。
虽然已参照几个典型实施例描述了本发明,但应当理解,所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质,所以应当理解,上述实施例不限于任何前述的细节,而应在随附权利要求所限定的精神和范围内广泛地解释,因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。
Claims (12)
1.一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度,所述注入型电流扩散区与所述外延阱区直接接触,所述外延阱区的底部低于沟槽栅底部;
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区,所述外延保护区的底部低于沟槽栅底部。
2.根据权利要求1所述的碳化硅沟槽栅MOSFET,其特征在于,其中所述凹型包括U型、V型、多边形或圆角矩形中的任意一种。
3.根据权利要求1所述的碳化硅沟槽栅MOSFET,其特征在于,还包括形成于注入型电流扩散区内、沟槽栅底部的具有第二掺杂型的屏蔽区。
4.根据权利要求1所述的碳化硅沟槽栅MOSFET,其特征在于,当所述碳化硅沟槽栅MOSFET处于正向导通状态时,沟槽栅两侧形成沟道,沟槽栅底部两侧角落处形成积累区,电流从漏电极经衬底、外延层、注入型电流扩散区、积累区、沟道、第一源接触区流向源电极。
5.一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;以及
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区,所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度,所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接,所述外延保护区的底部低于沟槽栅底部。
6.根据权利要求5所述的碳化硅沟槽栅MOSFET,其特征在于,还包括形成于注入型电流扩散区内、沟槽栅底部的具有第二掺杂型的屏蔽区。
7.一种碳化硅沟槽栅MOSFET,包括具有第一掺杂类型的衬底,形成在衬底上具有第一掺杂类型的外延层,形成在外延层上具有第二掺杂类型的外延阱区,形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区,沟槽栅,源电极和漏电极,所述沟槽栅包括栅介质和栅电极,其特征在于,所述碳化硅沟槽栅MOSFET包括:
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;以及
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区,所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度,所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接,所述外延保护区的底部低于沟槽栅底部;以及
形成于外延保护区上方、外延阱区内的具有第一掺杂类型的外延电流扩散区,所述外延电流扩散区与沟槽栅两侧侧壁直接接触。
8.一种碳化硅沟槽栅MOSFET的制造方法,其特征在于,所述制造方法包括:
在衬底上形成外延层;
在外延层上形成外延阱区;
形成第一源接触区;
形成第二源接触区;
在半导体表面刻蚀沟槽;
利用刻蚀沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区,其中所述注入型电流扩散区的底部不高于外延阱区的底部,掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度;
在沟槽表面形成栅介质;
在沟槽内部填充栅电极;以及
形成漏电极和源电极;其中
衬底、外延层、第一源接触区、注入型电流扩散区具有第一掺杂类型,外延阱区、第二源接触区具有第二掺杂类型;
还包括在所述外延层表面生长外延保护区,然后在所述外延保护区表面继续生长所述外延阱区,在刻蚀沟槽过程中,沟槽停止在所述外延保护区中。
9.如权利要求8所述的制造方法,其特征在于,在刻蚀沟槽过程中,沟槽停止在外延阱区中。
10.如权利要求8所述的制造方法,其特征在于,还包括在所述外延层表面生长外延保护区,再在所述外延保护区表面生长外延电流扩散区,再在所述外延电流扩散区表面生长所述外延阱区,在刻蚀沟槽过程中,沟槽停止在所述外延电流扩散区中。
11.如权利要求8所述的制造方法,其特征在于,其中利用刻蚀沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区包括:利用注入工艺的弹射和掺杂离子的扩散能力,形成包裹沟槽底部的注入型电流扩散区。
12.如权利要求8所述的制造方法,其特征在于,还包括在外延电流扩散区外侧、外延保护区上方形成第三源接触区,第二源接触区和第三源接触区通过同一道离子注入工艺形成。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111239940.2A CN113690321B (zh) | 2021-10-25 | 2021-10-25 | 一种碳化硅沟槽栅mosfet及其制造方法 |
US17/971,665 US20230130726A1 (en) | 2021-10-25 | 2022-10-24 | Silicon Carbide Trench Gate MOSFET and Method for Manufacturing Thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111239940.2A CN113690321B (zh) | 2021-10-25 | 2021-10-25 | 一种碳化硅沟槽栅mosfet及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113690321A CN113690321A (zh) | 2021-11-23 |
CN113690321B true CN113690321B (zh) | 2022-03-15 |
Family
ID=78587824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111239940.2A Active CN113690321B (zh) | 2021-10-25 | 2021-10-25 | 一种碳化硅沟槽栅mosfet及其制造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20230130726A1 (zh) |
CN (1) | CN113690321B (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114420761B (zh) * | 2022-03-30 | 2022-06-07 | 成都功成半导体有限公司 | 一种耐高压碳化硅器件及其制备方法 |
CN114597130B (zh) * | 2022-04-02 | 2022-12-27 | 致瞻科技(上海)有限公司 | 一种基于分裂栅的碳化硅mosfet器件及其制造方法 |
CN114597257B (zh) * | 2022-05-05 | 2022-07-26 | 南京微盟电子有限公司 | 一种沟槽栅碳化硅mosfet器件及其工艺方法 |
CN116230549B (zh) * | 2023-04-27 | 2023-08-29 | 浙江大学 | 集成低势垒二极管的沟槽型绝缘栅场效应管及其制造方法 |
CN116525681B (zh) * | 2023-05-18 | 2023-11-24 | 南京第三代半导体技术创新中心有限公司 | 集成沟道二极管的碳化硅槽栅mosfet器件及制造方法 |
CN116936620A (zh) * | 2023-09-14 | 2023-10-24 | 凌锐半导体(上海)有限公司 | 一种碳化硅沟槽栅mosfet的制备方法 |
CN117766572B (zh) * | 2024-01-17 | 2024-07-16 | 无锡芯动半导体科技有限公司 | 一种复合型碳化硅mosfet元胞结构及器件 |
CN117976699B (zh) * | 2024-02-01 | 2024-08-13 | 杭州芯迈半导体技术有限公司 | 一种碳化硅沟槽栅mosfet的元胞结构及版图 |
CN118197923B (zh) * | 2024-05-20 | 2024-08-02 | 扬州扬杰电子科技股份有限公司 | 一种降低沟槽栅氧电场的碳化硅mosfet器件及制备方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4954854A (en) * | 1989-05-22 | 1990-09-04 | International Business Machines Corporation | Cross-point lightly-doped drain-source trench transistor and fabrication process therefor |
JP2917922B2 (ja) * | 1996-07-15 | 1999-07-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US20010001494A1 (en) * | 1999-04-01 | 2001-05-24 | Christopher B. Kocon | Power trench mos-gated device and process for forming same |
CN101656269B (zh) * | 2009-09-18 | 2012-05-09 | 哈尔滨工程大学 | 具有低导通电阻的沟槽dmos器件 |
CN111668312B (zh) * | 2020-06-15 | 2023-08-04 | 东南大学 | 一种低导通电阻的沟槽碳化硅功率器件及其制造工艺 |
CN111755525A (zh) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | 一种Trench MOS功率器件及制备方法 |
CN112186027A (zh) * | 2020-08-28 | 2021-01-05 | 派恩杰半导体(杭州)有限公司 | 一种带有栅极沟槽结构的碳化硅mosfet |
-
2021
- 2021-10-25 CN CN202111239940.2A patent/CN113690321B/zh active Active
-
2022
- 2022-10-24 US US17/971,665 patent/US20230130726A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230130726A1 (en) | 2023-04-27 |
CN113690321A (zh) | 2021-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN113690321B (zh) | 一种碳化硅沟槽栅mosfet及其制造方法 | |
US10157983B2 (en) | Vertical power MOS-gated device with high dopant concentration N-well below P-well and with floating P-islands | |
US9093522B1 (en) | Vertical power MOSFET with planar channel and vertical field plate | |
US9627520B2 (en) | MOS transistor having a cell array edge zone arranged partially below and having an interface with a trench in an edge region of the cell array | |
KR100869324B1 (ko) | 베이스 리치-쓰루를 방지하는 측면 확장 베이스 차폐영역을 구비한 전력 반도체 소자 및 그 제조방법 | |
US7915617B2 (en) | Semiconductor device | |
KR101722811B1 (ko) | 낮은 소스 저항을 갖는 전계 효과 트랜지스터 장치 | |
EP1095409B1 (en) | Silicon carbide horizontal channel buffered gate semiconductor devices | |
EP2294621B1 (en) | Method of forming a power semiconductor device and power semiconductor device | |
KR20180001044A (ko) | 반도체 소자 및 그 제조 방법 | |
US7521731B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2021040131A (ja) | トレンチ・ゲートを有する炭化ケイ素デバイス | |
CN112186027A (zh) | 一种带有栅极沟槽结构的碳化硅mosfet | |
CN115148826A (zh) | 一种深沟槽碳化硅jfet结构的制作方法 | |
US20220238698A1 (en) | Mos-gated trench device using low mask count and simplified processing | |
KR101539880B1 (ko) | 전력 반도체 소자 | |
EP1703566A1 (en) | MOS device having at least two channel regions | |
EP1863096A1 (en) | Semiconductor device and method of manufacturing the same | |
EP3881360B1 (en) | Insulated gate bipolar transistor | |
WO2022119743A1 (en) | Finfet power semiconductor devices | |
JP2004253510A (ja) | 半導体装置 | |
CN107863378B (zh) | 超结mos器件及其制造方法 | |
US20230352577A1 (en) | Vertical shielded gate accumulation field effect transistor | |
CN118315429A (zh) | 一种集成异质结二极管的鳍型栅宽禁带和超宽禁带mosfet器件 | |
CN118136678A (zh) | 双栅双沟道ldmos器件及制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20231030 Address after: S103-3, Building 6, Phase 5, Information Port, No. 733 Jianshe Third Road, Ningwei Street, Xiaoshan District, Hangzhou City, Zhejiang Province, 311200 Patentee after: Hangzhou Xinzhu Semiconductor Co.,Ltd. Address before: No. 733, Jianshe 3rd road, Xiaoshan District, Hangzhou, Zhejiang 311200 Patentee before: ZJU-Hangzhou Global Scientific and Technological Innovation Center |