CN113690321B - 一种碳化硅沟槽栅mosfet及其制造方法 - Google Patents

一种碳化硅沟槽栅mosfet及其制造方法 Download PDF

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CN113690321B
CN113690321B CN202111239940.2A CN202111239940A CN113690321B CN 113690321 B CN113690321 B CN 113690321B CN 202111239940 A CN202111239940 A CN 202111239940A CN 113690321 B CN113690321 B CN 113690321B
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epitaxial
region
current diffusion
trench gate
doping
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CN113690321A (zh
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盛况
任娜
徐弘毅
江崇瑜
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Hangzhou Xinzhu Semiconductor Co ltd
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ZJU Hangzhou Global Scientific and Technological Innovation Center
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Abstract

本发明提供了一种碳化硅沟槽栅MOSFET及其制造方法，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上方具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和楼电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部。合理设置注入型电流扩散区，能够限制器件的饱和电流，同时能分离电场峰值和电流位置的位置，降低发热功率，增大器件的短路能力。

Description

一种碳化硅沟槽栅MOSFET及其制造方法
技术领域
本发明涉及一种半导体器件，尤其涉及一种碳化硅沟槽栅MOSFET及其制造方法。
背景技术
传统硅基半导体器件的性能已经逐渐接近材料的物理极限，而采用以SiC材料的第三代功率半导体器件因其优异的高频、高压、导热能力强等特性在高功率密度和高效率装置中具有强大的吸引力。SiC MOSFET器件因其驱动容易以及开关频率高的特性，在电动汽车、光伏逆变等应用场景中逐步使用。SiC MOSFET器件主要右平面栅双扩散SiC MOSFET以及沟槽栅MOSFET。相比较平面栅MOSFET，沟槽栅MOSFET消除了JFET区电阻，同时具有较高的沟道密度，这使得器件的通态特征电阻显著减小。同时因材料晶向的原因，沟槽侧壁具备了较为优异的沟道电子迁移率。
然而，SiC沟槽MOSFET器件在实际制作和应用中仍然存在几个问题：（1）SiC漂移区的高电场导致栅介质上的电场很高，这个问题在槽角处加剧，从而在高漏极电压下造成栅介质迅速击穿；（2）由于沟槽MOSFET的导通电阻较小，导致其在发生短路时电路电流较大，器件发热严重，短路能力相比平面栅MOSFET较弱。因此需要对结构进行优化来避免栅槽底部的提前击穿。图1结构中所述传统沟槽栅型SiC MOSFET元胞采用底部注入第二掺杂类型（例如P型）的方式来保护栅介质。其结构包括具有第一掺杂类型的碳化硅衬底区域001，具有第一掺杂类型（例如N型）的碳化硅外延区域002，具有第二掺杂类型的碳化硅外延阱区003，具有第二掺杂类型的源接触区004，具有第一掺杂类型的源接触区005，沟槽栅介质006，具有第二掺杂类型的电场屏蔽区007（一般为重掺杂P型区域），沟槽栅电极008，漏电极010，源电极011。所述传统沟槽栅型MOSFET器件导通时（沟槽栅电极008施加正电压，例如10~20V，漏电极010施加正电压，例如0-20V，源电极011施加零电压，例如0V）的电流路径如图2中Ia所示，在沟槽两侧形成沟道009，用于控制器件的开关。目前经典沟槽MOSFET结构能缓解槽角处电场，但不能改善其短路能力。
发明内容
为了解决上述现有情况下的问题，本发明提出一种碳化硅沟槽栅MOSFET及其制造方法。
根据本发明一实施例提出一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上方具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度，所述注入型电流扩散区与所述外延阱区直接接触，所述外延阱区的底部低于沟槽栅底部。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；以及形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区，所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度，所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接，所述外延保护区的底部低于沟槽栅底部。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；以及形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区，所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度，所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接，所述外延保护区的底部低于沟槽栅底部；以及形成于外延保护区上方、外延阱区内的具有第一掺杂类型的外延电流扩散区，所述外延电流扩散区与沟槽栅两侧侧壁直接接触。
根据本发明又一实施例提出一种碳化硅沟槽栅MOSFET的制造方法，其特征在于，所述制造方法包括：在衬底上形成外延层；在外延层上形成外延阱区；形成第一源接触区；形成第二源接触区；在半导体表面刻蚀沟槽；利用沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；在沟槽表面形成栅介质；在沟槽内部填充栅电极；以及形成漏电极和源电极；其中衬底、外延层、第一源接触区、注入型电流扩散区具有第一掺杂类型，外延阱区、第二源接触区具有第二掺杂类型。
本发明具有以下有益技术效果：
1、相比于传统的沟槽栅底部设置具有第二掺杂类型（例如P型）的保护区的MOSFET，本发明具有第一掺杂类型（例如N型）的凹型形状的注入型电流扩散区的MOSFET的有效漂移区厚度更大，击穿电压更高，同时具有注入型电流扩散区的MOSFET能提供的额外的积累层的通道，降低导通电阻。合理设置注入型电流扩散区，能够限制器件的饱和电流，同时能分离电场峰值和电流峰值的位置，降低发热功率，增大器件的短路能力；
2、设置注入型电流扩散区的形状为包裹沟槽栅底部的凹型形状，例如U型、V型、多边形或圆角矩形等，在工艺上实现便于垂直注入形成电流扩散区，降低工艺难度；
3、在注入型电流扩散区内、沟槽栅底部中间位置形成P型屏蔽区，可有效降低栅介质的电场；
4、在注入型电流扩散区两侧、外延阱区底部形成外延保护区，能有效降低栅介质电场，同时对器件的短路电路能起到较好地抑制作用；
5、在外延保护区上、外延阱区下形成外延电流扩散区，能使得器件的电流得到扩散，同时能使得沟槽栅的角落更稳定地被N型掺杂包围；所述外延电流扩散区底部不高于沟槽栅底部，所述外延电流扩散区顶部高于沟槽栅底部；
6、除了设置第二源接触区外，还可在外延电流扩散区外侧、外延保护区上方设置第三源接触区1041，可以具有与第二源接触区104相同的掺杂类型和掺杂浓度（例如第二掺杂类型P型），起到缓冲电路的作用，降低电压尖峰；
7、在工艺流程中，可以利用刻蚀沟槽的掩膜通过离子注入形成注入型电流扩散区，实际过程中可以利用注入工艺的弹射和掺杂离子激活工艺中的扩散能力形成包裹角落的注入型电流扩散区。在本实施例中，由于注入型电流扩散区需要高剂量注入（一实施例中需高于外延阱区浓度，另一实施例中需高于外延保护区浓度），因此会在角落处注入离子发生弹射，更容易聚集掺杂离子，形成包裹角落的状态。相比沟槽两侧注入P型区保护栅介质的方案，能避免使用高能离子注入。相比传统结构，本实施例以及匹配的工艺不会浪费外延层厚度，可以使用更薄的外延层达到相同的耐压，以达到更优化的器件特性。
附图说明
图1为传统碳化硅沟槽栅MOSFET器件元胞000的结构示意图；
图2为传统碳化硅沟槽栅MOSFET器件元胞000在导通状态下电流通路示意图；
图3为本发明碳化硅沟槽栅MOSFET器件第一元胞100的结构示意图；
图4为本发明碳化硅沟槽栅MOSFET器件第一元胞100在正向导通状态下的电流通路及内部状态变化图；
图5为根据本发明第一元胞100衍生出的碳化硅多边形沟槽栅MOSFET器件第二元胞200的结构示意图；
图6为根据本发明第一元胞100衍生出的碳化硅圆角矩形沟槽栅MOSFET器件第三元胞300的结构示意图；
图7为根据本发明第一元胞100衍生出的碳化硅U型沟槽栅MOSFET器件第四元胞400的结构示意图；
图8为根据本发明第一元胞100衍生出具有分立沟槽栅MOSFET器件第五元胞500的结构示意图；
图9为根据本发明第二元胞200衍生出具有分立沟槽栅MOSFET器件第六元胞600的结构示意图；
图10为根据本发明第三元胞300衍生出具有分立沟槽栅MOSFET器件第七元胞700的结构示意图；
图11为根据本发明第四元胞400衍生出具有分立沟槽栅MOSFET器件第八元胞800的结构示意图；
图12为根据本发明第一元胞100衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件第九元胞900结构示意图；
图13为根据本发明第二元胞200衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十元胞1000示意图；
图14为根据本发明第三元胞300衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十一元胞1100示意图；
图15为根据本发明第四元胞400衍生出在注入型电流扩散区底部具有第二掺杂类型的屏蔽区的沟槽栅MOSFET器件元胞结构第十二元胞1200示意图；
图16为根据本发明第一元胞100衍生出具有外延保护区的沟槽栅第十三元胞1300示意图；
图17为根据本发明第二元胞200衍生出具有外延保护区的沟槽栅第十四元胞1400结构示意图；
图18为根据本发明第三元胞300衍生出具有外延保护区的沟槽栅第十五元胞1500结构示意图；
图19为根据本发明第四元胞400衍生出具有外延保护区的沟槽栅第十六元胞1600结构示意图；
图20为根据本发明第十三元胞1300衍生出具有外延电流扩散区的沟槽栅第十七元胞1700结构示意图；
图21为根据本发明第十四元胞1400衍生出具有外延电流扩散区的沟槽栅第十八元胞1800结构示意图；
图22为根据本发明第十五元胞1500衍生出具有外延电流扩散区的沟槽栅第十九元胞1900结构示意图；
图23为根据本发明第十六元胞1600衍生出具有外延电流扩散区的沟槽栅第二十元胞2000结构示意图；
图24为根据本发明第十七元胞1700衍生出第三源接触区的沟槽栅第二十一元胞2100示意图；
图25为根据本发明第十八元胞1800衍生出第三源接触区的沟槽栅第二十二元胞200示意图；
图26为根据本发明第十九元胞1900衍生出第三源接触区的沟槽栅第二十三元胞2300示意图；
图27为根据本发明第二十元胞2000衍生出第三源接触区的沟槽栅第二十四元胞2400示意图；
图28为本发明一实施例的碳化硅沟槽型MOSFET器件的工艺制作流程示意图2500。
具体实施方式
下面将结合附图详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了便于对本发明的透彻理解，阐述了大量特定细节。然而，本领域普通技术人员可以理解，这些特定细节并非为实施本发明所必需。此外，在一些实施例中，为了避免混淆本发明，未对公知的电路、材料或方法做具体描述。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图均是为了说明的目的，其中相同的附图标记指示相同的元件,但不限于元件结构必须完全相同。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
本发明所指的第一掺杂类型与第二掺杂类型相反，当第一掺杂类型为N型时，第二掺杂类型为P型，当第一掺杂类型为P型时，第二掺杂类型为N型。本发明所指掺杂类型包括但不限于P型掺杂或N型掺杂。本发明所指的凹型不限于图3或图4所示的结构，也可以是V型、U型、多边形、圆角矩形等凹型。
本发明公开的碳化硅沟槽型MOSFET器件第一元胞100结构如图3所示。其元胞结构包括：具有第一掺杂类型（例如N型）的衬底101；形成在衬底101上的具有第一掺杂类型的外延层102；形成在外延层102上方具有第二掺杂类型（例如P型）的外延阱区103，在一个实施例中，形成在外延层102上方可以是直接在外延层102上与外延层102接触，也可以是指在外延层102上方不直接与外延层102接触（例如中间还设置有其它区域）；形成在外延阱区103内的具有第一掺杂类型的第一源接触区105；形成在外延阱区103内的具有第二掺杂类型的第二源接触区104，第二源接触区104与第一源接触区105可以毗邻；沟槽栅168，包括栅介质106和形成在栅介质106上的栅电极108（可以为多晶硅填充）；包围在沟槽栅168底部（或者底部及底部侧面）的具有第一掺杂类型的注入型电流扩散区107，在一个实施例中，注入型电流扩散区107呈凹型包围在栅介质106底部及底部侧面，且注入型电流扩散区107的底部不高于外延阱区103的底部以保证器件能正常正向导通，所述注入型电流扩散区107的掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度；漏电极111和源电极112。碳化硅沟槽型MOSFET器件在正向导通的状态下的电流Ib的导通电流路径如如图4中带箭头的虚线所示，其中箭头指向为电流Ib的流向，在一个实施例中，在栅电极108上施加正电压（例如10~20V），漏电极111上施加正电压（例如0~20V）,源电极112接地，在此状态下所述碳化硅沟槽型MOSFET器件在沟槽栅168两侧形成沟道109，在沟槽栅底部两侧角落形成积累区110，电流从漏电极111经衬底101、外延层102、注入型电流扩散区107、积累区110、沟道109、第一源接触区105流向源电极112。在另一个实施例中，存在一种器件经受大电流高电压的极端情况，当碳化硅沟槽型MOSFET器件处于高压阻断的情况下（例如阻断电压600V情况下），栅电极108上的电压变高（例如20V），沟道109打开，器件导通，此时器件会因为耗尽区的存在出现高电场，同时因为导通而存在大电流使得出现短路情况，其中电场峰值在沟槽栅168底部的栅介质106的中心位置，电流Ib峰值在沟槽栅168两侧，而第一元胞100的这种结构能在短路过程中减小发热。
请参考图5，根据本发明第一元胞100衍生出的碳化硅多边形沟槽栅MOSFET的第二元胞200。与第一元胞100的区别在于，第二元胞200具有多边形的沟槽栅168（包括多边形的栅介质106和栅电极108）以及多边形的注入型电流扩散区107。第二元胞200倾斜的沟槽栅168能便于垂直注入形成所述注入型电流扩散区107。
请参考图6，根据本发明第一元胞100衍生出的碳化硅圆角矩形沟槽栅MOSFET的第三元胞300结构，与第一元胞100的区别在于，第三元胞300具有圆角矩形的沟槽栅168（包括圆角矩形的栅介质106和栅电极108）以及圆角矩形的注入型电流扩散区107。第三元胞300圆角矩形的沟槽栅168能便于垂直注入形成注入型电流扩散区107。
请参考图7，根据本发明第一元胞100衍生出的碳化硅U型沟槽栅MOSFET的第四元胞400结构。与第一元胞100的区别在于，第四元胞400结构具有U型的沟槽栅168（包括U型的栅介质106和栅电极108）以及U型的注入型电流扩散区107。第四元胞400的U型沟槽栅168能便于垂直注入形成注入型电流扩散区107。
请参考图8，根据本发明第一元胞100衍生出的碳化硅分立沟槽栅MOSFET的第五元胞500结构。与第一元胞100的区别在于，第五元胞500包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积，能有效降低栅-漏的电容。
请参考图9，根据本发明第二元胞200衍生出的碳化硅分立沟槽栅MOSFET的元胞的第六元胞600结构。与第二元胞200的区别在于，第六元胞600包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积，能有效降低栅-漏的电容。
请参考图10，根据本发明第三元胞300衍生出的碳化硅分立沟槽栅MOSFET的第七元胞700结构。与第三元胞300的区别在于，第七元胞700包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积，能有效降低栅-漏的电容。
请参考图11，根据本发明第四元胞400衍生出的碳化硅分立沟槽栅MOSFET的第八元胞800结构。与第四元胞400的区别在于，第八元胞800包括无掩膜刻蚀形成的多晶硅分裂栅501。采用分裂栅501能减小栅和漏重叠面积，能有效降低栅-漏的电容。
请参考图12，根据本发明第一元胞100衍生出的碳化硅沟槽栅MOSFET的第九元胞900结构。与第一元胞100的区别在于，第九元胞900还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901，所述屏蔽区901的注入深度连续可调，能有效地降低栅介质的电场。
请参考图13，根据本发明第二元胞200衍生出的碳化硅沟槽栅MOSFET的第十元胞1000结构。与第二元胞200的区别在于，第十元胞1000还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901，所述屏蔽区901的注入深度连续可调，能有效地降低栅介质的电场。
请参考图14，根据本发明第三元胞300衍生出的碳化硅沟槽栅MOSFET的第十一元胞1100。与第三元胞300的区别在于，第十一元胞1100还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901，所述屏蔽区901的注入深度连续可调，能有效地降低栅介质的电场。
请参考图15，根据本发明第四元胞400衍生出的碳化硅沟槽栅MOSFET的第十二元胞1200。与第四元胞400的区别在于，第十二元胞1200还包括形成于注入型电流扩散区107中的具有第二掺杂类型的屏蔽区901，所述屏蔽区901的注入深度连续可调，能有效地降低栅介质的电场。
图4至图15所示实施例中，所述注入型电流扩散区107与所述外延阱区103直接接触（例如所述注入型电流扩散区107两侧与所述外延阱区103直接接触），所述外延阱区103的底部低于沟槽栅168底部，以保证器件正向导通工作时，沟道形成于沟槽栅侧壁的外延阱区103中，并且沟道中载流子进入注入型电流扩散区。
请参考图16，根据本发明第一元胞100衍生出的碳化硅沟槽栅MOSFET的第十三元胞1300结构。与第一元胞100的区别在于，所述第十三元胞1300还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302，所述外延保护区1302具有第二掺杂类型，其掺杂浓度（例如1×1018cm-3~3×1018cm-3）高于所述外延阱区103的掺杂浓度（例如1×1017cm-3~1×1018cm-3）。外延保护区1302能有效降低栅介质电场，同时对器件的短路电路能起到较好地抑制作用。
请参考图17，根据本发明第二元胞200衍生出的碳化硅沟槽栅MOSFET的第十四元胞1400结构。与第二元胞200的区别在于，第十四元胞1400还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302，所述外延保护区1302具有第二掺杂类型，其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场，同时对器件的短路电路能起到较好地抑制作用。
请参考图18，根据本发明第三元胞300衍生出的碳化硅沟槽栅MOSFET的第十五元胞1500结构。与第三元胞300的区别在于，第十五元胞1500还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302，所述外延保护区1302具有第二掺杂类型，其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场，同时对器件的短路电路能起到较好地抑制作用。
请参考图19，根据本发明第四元胞400衍生出的碳化硅沟槽栅MOSFET的第十六元胞1600结构。与第四元胞400的区别在于，第十六元胞1600还包括形成于注入型电流扩散区107两侧及外延阱区103底部的外延保护区1302，所述外延保护区1302具有第二掺杂类型，其掺杂浓度高于所述外延阱区103的掺杂浓度。外延保护区1302能有效降低栅介质电场，同时对器件的短路电路能起到较好地抑制作用。
图16至图19所示实施例中，所述注入型电流扩散区107的底部不高于外延阱区103的底部，掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度，所述外延保护区1302的掺杂浓度高于所述外延阱区103的掺杂浓度。所述注入型电流扩散区107通过所述外延保护区1302与所述外延阱区103连接（例如注入型电流扩散区107两侧与所述外延保护区1302直接接触），所述注入电流扩散区107两侧上方角落处可以与所述外延阱区103直接接触，所述外延保护区1302的底部低于沟槽栅168底部，以保证器件正向导通工作时，沟道形成于沟槽栅168侧壁的外延阱区103中，并且沟道中载流子进入注入型电流扩散区107。
请参考图20，根据本发明第十三元胞1300衍生出的碳化硅沟槽栅MOSFET的第十七元胞1700结构。与第十三元胞1300的区别在于，第十七元胞1700还包括形成于外延保护区1302上方、外延阱区103内的外延电流扩散区1701，所述外延电流扩散区1701具有第一掺杂类型（例如N型掺杂浓度为1×1016cm-3~3×1017cm-3）。外延电流扩散区1701不仅能使得器件的电流得到扩散，同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型（例如N型）包围，同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触，能抑制动态电阻并保护栅介质106。
请参考图21，根据本发明第十四元胞1400衍生出的碳化硅沟槽栅MOSFET的第十八元胞1800结构。与第十四元胞1400的区别在于，第十八元胞1800还包括形成于外延保护区1302上方、外延阱区103内的外延电流扩散区1701，所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散，同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型（例如N型）包围，同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触，能抑制动态电阻并保护栅介质106。
请参考图22，根据本发明第十五元胞1500衍生出的碳化硅沟槽栅MOSFET的第十九元胞1900。与第十五元胞1500的区别在于，第十九元胞1900还包括形成于外延保护区1302上方外延阱区103内的外延电流扩散区1701，所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散，同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型（例如N型）包围，同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触，能抑制动态电阻并保护栅介质106。
请参考图23，根据本发明第十六元胞1600衍生出的碳化硅沟槽栅MOSFET的第二十元胞2000结构。与第十六元胞1600的区别在于，第二十元胞2000还包括形成于外延保护区1302上方外延阱区103内的外延电流扩散区1701，所述外延电流扩散区1701具有第一掺杂类型。外延电流扩散区1701不仅能使得器件的电流得到扩散，同时能使得沟槽栅168的角落能更稳定地被第一掺杂类型（例如N型）包围，同时第二源接触区104的深度可连续延伸至分别与外延电流扩散区1701和外延保护区1302直接接触，能抑制动态电阻并保护栅介质106。
请参考图24，根据本发明第十七元胞1700衍生出的碳化硅沟槽栅MOSFET的第二十一元胞2100结构。与第十七元胞1700的区别在于，第二十一元胞2100除了包括第二源接触区104外，还包括形成于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041，可以具有与第二源接触区104相同的掺杂类型和掺杂浓度（例如第二掺杂类型P型），起到缓冲电路的作用，降低电压尖峰。
请参考图25，根据本发明第十八元胞1800衍生出的碳化硅沟槽栅MOSFET的第二十二元胞2200结构。与第十八元胞1800的区别在于，第二十二元胞2200除了包括第二源接触区104外，还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041，可以具有与第二源接触区104相同的掺杂类型和掺杂浓度（例如第二掺杂类型P型），起到缓冲电路的作用，降低电压尖峰。
请参考图26，根据本发明第十九元胞1900衍生出的碳化硅沟槽栅MOSFET的第二十三元胞2300。与第十九元胞1900的区别在于，第二十三元胞2300除了包括第二源接触区104外，还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041，可以具有与第二源接触区104相同的掺杂类型和掺杂浓度（例如第二掺杂类型P型），起到缓冲电路的作用，降低电压尖峰。
请参考图27，根据本发明第二十元胞2000衍生出的碳化硅沟槽栅MOSFET的第二十四元胞2400。与第二十元胞2000的区别在于，第二十四元胞2400除了包括第二源接触区104外，还包括位于外延电流扩散区1701外侧、外延保护区1302上方的第三源接触区1041，可以具有与第二源接触区104相同的掺杂类型和掺杂浓度（例如第二掺杂类型P型），起到缓冲电路的作用，降低电压尖峰。
图20至图27所示实施例中，所述注入型电流扩散区107的底部不高于外延阱区103的底部，掺杂浓度高于所述外延层102的掺杂浓度和所述外延阱区103的掺杂浓度，所述外延保护区1302的掺杂浓度高于所述外延阱区103的掺杂浓度。所述注入型电流扩散区107通过所述外延保护区1302和所述外延电流扩散区1701与所述外延阱区103连接（例如注入型电流扩散区107两侧与所述外延保护区1302直接接触，注入型电流扩散区107两侧上方角落处可以与所述外延电流扩散区1701直接接触），所述外延保护区1302的底部低于沟槽栅168底部，以保证器件正向导通工作时，沟道形成于沟槽栅168侧壁的外延阱区103中，并且沟道中载流子进入注入型电流扩散区107。
综合图3至图27所示实施例，所述注入型电流扩散区107可以与所述外延阱区103直接接触，也可以通过外延保护区1302或外延保护区1302和外延电流扩散区1701与所述外延阱区103连接，以保证器件正向导通工作时，沟道形成于沟槽栅侧壁的外延阱区103中，并且沟道中载流子进入注入型电流扩散区107。
图28为根据本发明实施例的制作如图3所示的碳化硅沟槽栅MOSFET器件的流程图。制作方法包括步骤S1-S9。
步骤S1，在衬底101上方形成外延层102（例如在衬底101表面生长外延层102）。衬底101与外延层102均具有第一掺杂类型，衬底101的掺杂浓度高于外延层102的掺杂浓度。
步骤S2，在外延层102上方形成外延阱区103（例如在外延层102表面生长外延阱区103）。如果需要制作类似如图16所示的包括外延保护区1302的碳化硅沟槽栅MOSFET器件，则可以先在外延层表面生长外延保护区1302，然后在外延保护区1302表面继续生长外延阱区。如果需要制作类似如图24所示的包括外延电流扩散区1701的碳化硅沟槽栅MOSFET器件，则可以先在外延保护区1302表面生长外延电流扩散区1701，再在外延电流扩散区1701表面生长外延阱区。采用外延的方式形成具有第二掺杂类型的外延保护区1302，激活率易于控制，并且避免了沟道左右两侧第二掺杂类型的高能注入，易于实现结构。
步骤S3，形成第一源接触区105，例如在半导体表面通过注入形成第一源接触区105。
步骤S4，形成第二源接触区104，例如在半导体表面通过注入形成第二源接触区104。当制作类似如图24所示的包括第三源接触区1041的碳化硅沟槽栅MOSFET器件时，可以通过一次离子注入同时形成第二源接触区104和第三源接触区1041。
步骤S5，在半导体表面刻蚀沟槽068。在一个实施例中，控制沟槽068顶部倾斜角度小于5°，沟槽底部为凹型（可为V型、U型或圆角矩形等）。在一种实施例中，沟槽068停止在具有第二掺杂类型的外延阱区103中；在另一种实施例中，沟槽068停止在具有第二掺杂类型的外延保护区1302中；在另一个实施例中，沟槽068停止在具有第一掺杂类型的外延电流扩散区1701中。
步骤S6，利用沟槽的掩膜离子注入形成注入型电流扩散区107，例如利用沟槽的掩膜使用第一掺杂的离子进行离子注入，形成注入型电流扩散区107。在一个实施例中，利用注入工艺的弹射和掺杂离子的扩散能力，形成包裹沟槽底部的注入型电流扩散区107。相比传统方法，该结构和工艺不会浪费外延层厚度，可以使用更薄的外延层达到耐压，以达到更优化的器件特性；相比沟槽两侧注入P型区保护栅介质的方案，能避免使用高能离子注入。
步骤S7，在沟槽068表面形成栅介质106。在一个实施例中，可以通过高温氧化以及CVD/PVD/ALD的工艺形成栅介质106。
步骤S8，在沟槽068内部填充栅电极108。在一个实施例中，所述栅电极108为多晶硅。
步骤S9，形成漏电极111和源电极112。在一个实施例中，可以通过金属溅射和欧姆接触形成漏电极111和源电极112。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (12)

1.一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度，所述注入型电流扩散区与所述外延阱区直接接触，所述外延阱区的底部低于沟槽栅底部；
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区，所述外延保护区的底部低于沟槽栅底部。
2.根据权利要求1所述的碳化硅沟槽栅MOSFET，其特征在于，其中所述凹型包括U型、V型、多边形或圆角矩形中的任意一种。
3.根据权利要求1所述的碳化硅沟槽栅MOSFET，其特征在于，还包括形成于注入型电流扩散区内、沟槽栅底部的具有第二掺杂型的屏蔽区。
4.根据权利要求1所述的碳化硅沟槽栅MOSFET，其特征在于，当所述碳化硅沟槽栅MOSFET处于正向导通状态时，沟槽栅两侧形成沟道，沟槽栅底部两侧角落处形成积累区，电流从漏电极经衬底、外延层、注入型电流扩散区、积累区、沟道、第一源接触区流向源电极。
5.一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；以及
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区，所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度，所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接，所述外延保护区的底部低于沟槽栅底部。
6.根据权利要求5所述的碳化硅沟槽栅MOSFET，其特征在于，还包括形成于注入型电流扩散区内、沟槽栅底部的具有第二掺杂型的屏蔽区。
7.一种碳化硅沟槽栅MOSFET，包括具有第一掺杂类型的衬底，形成在衬底上具有第一掺杂类型的外延层，形成在外延层上具有第二掺杂类型的外延阱区，形成在外延阱区内具有第一掺杂类型的第一源接触区和具有第二掺杂类型的第二源接触区，沟槽栅，源电极和漏电极，所述沟槽栅包括栅介质和栅电极，其特征在于，所述碳化硅沟槽栅MOSFET包括：
包裹在沟槽栅底部的呈凹型的具有第一掺杂类型的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；以及
形成于注入型电流扩散区两侧、外延阱区底部的具有第二掺杂类型的外延保护区，所述外延保护区的掺杂浓度高于所述外延阱区的掺杂浓度，所述注入型电流扩散区通过所述外延保护区与所述外延阱区连接，所述外延保护区的底部低于沟槽栅底部；以及
形成于外延保护区上方、外延阱区内的具有第一掺杂类型的外延电流扩散区，所述外延电流扩散区与沟槽栅两侧侧壁直接接触。
8.一种碳化硅沟槽栅MOSFET的制造方法，其特征在于，所述制造方法包括：
在衬底上形成外延层；
在外延层上形成外延阱区；
形成第一源接触区；
形成第二源接触区；
在半导体表面刻蚀沟槽；
利用刻蚀沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区，其中所述注入型电流扩散区的底部不高于外延阱区的底部，掺杂浓度高于所述外延层的掺杂浓度和所述外延阱区的掺杂浓度；
在沟槽表面形成栅介质；
在沟槽内部填充栅电极；以及
形成漏电极和源电极；其中
衬底、外延层、第一源接触区、注入型电流扩散区具有第一掺杂类型，外延阱区、第二源接触区具有第二掺杂类型；
还包括在所述外延层表面生长外延保护区，然后在所述外延保护区表面继续生长所述外延阱区，在刻蚀沟槽过程中，沟槽停止在所述外延保护区中。
9.如权利要求8所述的制造方法，其特征在于，在刻蚀沟槽过程中，沟槽停止在外延阱区中。
10.如权利要求8所述的制造方法，其特征在于，还包括在所述外延层表面生长外延保护区，再在所述外延保护区表面生长外延电流扩散区，再在所述外延电流扩散区表面生长所述外延阱区，在刻蚀沟槽过程中，沟槽停止在所述外延电流扩散区中。
11.如权利要求8所述的制造方法，其特征在于，其中利用刻蚀沟槽的掩膜离子注入形成包裹在沟槽底部的注入型电流扩散区包括：利用注入工艺的弹射和掺杂离子的扩散能力，形成包裹沟槽底部的注入型电流扩散区。
12.如权利要求8所述的制造方法，其特征在于，还包括在外延电流扩散区外侧、外延保护区上方形成第三源接触区，第二源接触区和第三源接触区通过同一道离子注入工艺形成。
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