CN113690250B - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

Info

Publication number
CN113690250B
CN113690250B CN202110906895.5A CN202110906895A CN113690250B CN 113690250 B CN113690250 B CN 113690250B CN 202110906895 A CN202110906895 A CN 202110906895A CN 113690250 B CN113690250 B CN 113690250B
Authority
CN
China
Prior art keywords
layer
wiring
stress balance
stress
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110906895.5A
Other languages
English (en)
Other versions
CN113690250A (zh
Inventor
赵玲
张伟闵
肖军城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL Huaxing Photoelectric Technology Co Ltd
Original Assignee
TCL Huaxing Photoelectric Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TCL Huaxing Photoelectric Technology Co Ltd filed Critical TCL Huaxing Photoelectric Technology Co Ltd
Priority to CN202110906895.5A priority Critical patent/CN113690250B/zh
Priority to PCT/CN2021/112988 priority patent/WO2023015579A1/zh
Priority to US17/600,406 priority patent/US11984456B2/en
Publication of CN113690250A publication Critical patent/CN113690250A/zh
Application granted granted Critical
Publication of CN113690250B publication Critical patent/CN113690250B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种阵列基板及其制作方法。阵列基板包括衬底基板层、第一走线层、绝缘层以及应力平衡层；所述第一走线层设于所述衬底基板层上；所述第一走线层包括第一走线；所述绝缘层设于所述第一走线层上且覆盖在所述第一走线上方；所述应力平衡层设于所述绝缘层上方且围绕所述衬底基板层边缘，其中，所述应力平衡层的边缘与所述衬底基板层的所述边缘切齐，所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m。本发明通过在间隔区、边框区或第一走线和/或第二走线上设置应力平衡层，利用应力平衡层材质的压应力平衡走线的拉翘应力，改善阵列基板在制备过程中的翘曲破片问题。

Description

阵列基板及其制作方法
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制作方法。
背景技术
随着科技的进步和时代的发展，人们对手机显示屏的要求也越来越高。当前主流的硬屏显示已不能满足市场的需求。
现有技术中，阵列基板中包括数据线或栅极线等导电层结构，目前8K显示装置产品为了提升充电比(Charge Ratio，CR)以减少电容延迟，需要用较厚的导电材质制备数据线或栅极线等导电层结构，而采用的材质越厚，应力越大，导致制备阵列基板的玻璃无论显示区还是边缘区均容易受到数据线或栅极线等导电层结构的拉伸应力而发生翘曲甚至破片。
因此制备数据线或栅极线等导电层结构时，亟待解决由于材质的拉伸应力导致的阵列基板翘曲甚至破片的问题。
发明内容
本发明的目的在于，提供一种阵列基板及其制作方法，用以解决制备数据线或栅极线等导电层结构时，由于材质的拉伸应力导致的阵列基板翘曲甚至破片的技术问题。
为了解决上述问题，本发明其中一实施例中提供一种阵列基板，包括衬底基板层、第一走线层、绝缘层以及应力平衡层；所述第一走线层设于所述衬底基板层上；所述第一走线层包括第一走线；所述绝缘层设于所述第一走线层上且覆盖在所述第一走线上方；所述应力平衡层设于所述绝缘层上方且围绕所述衬底基板层边缘，其中，所述应力平衡层的边缘与所述衬底基板层的所述边缘切齐，所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m。
于本申请一实施例中所述的阵列基板，其中，所述第一走线层的材质包括铜，所述第一走线的厚度大于或等于5500埃；所述应力平衡层的材质包括砷、多晶硅、SINx、SiQx、IGZO中的任一种；所述应力平衡层的厚度大于或等于900埃。
于本申请一实施例中所述的阵列基板，其中，所述应力平衡层覆盖在所述第一走线上方。
于本申请一实施例中所述的阵列基板，其中，所述阵列基板区分为显示区与包围所述显示区的边框区，所述应力平衡层设置于所述边框区内。
于本申请一实施例中所述的阵列基板，其中，所述阵列基板还包括第二走线层以及钝化层；所述第二走线层设于所述应力平衡层上；所述钝化层设于所述第二走线层上。
本发明再一实施例中提供一种阵列基板的制作方法，包括以下步骤：
在一衬底基板层上制作多组相同的第一走线层图案，每一组所述第一走线层图案包括第一走线，所述多组第一走线层图案在所述衬底基板层上排列成阵列且彼此间隔；
制作绝缘层覆盖在所述多组第一走线层图案及所述衬底基板层上；
在所述绝缘层上制作应力平衡层，所述应力平衡层覆盖所述多组第一走线层图案之间的间隔区；所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m；以及
沿间隔区将所述衬底基板层切割开以形成多片阵列基板。
于本申请一实施例中所述的阵列基板的制作方法，其中，所述第一走线层图案的材质包括铜，所述第一走线的厚度大于或等于5500埃；所述应力平衡层的材质包括砷、多晶硅、SINx、SiQx、IGZO中的任一种；所述应力平衡层的厚度大于或等于900埃。
于本申请一实施例中所述的阵列基板的制作方法，其中，所述应力平衡层覆盖在所述第一走线上方。
本申请还提供一种阵列基板的制作方法，包括以下步骤：
在一衬底基板层上制作多组相同的第一走线层图案，每一组所述第一走线层图案包括第一走线，所述多组第一走线层图案在所述衬底基板层上排列成阵列且彼此间隔；
制作绝缘层覆盖在所述多组第一走线层图案及所述衬底基板层上；
在所述绝缘层上制作应力平衡层，所述应力平衡层覆盖所述多组第一走线层图案之间的间隔区；所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m；
制作第二走线层图案，设于所述应力平衡层上；
制作钝化层，设于所述第二走线层图案上；以及
沿间隔区将所述衬底基板层切割开以形成多片阵列基板。
于本申请一实施例中所述的阵列基板的制作方法，其中，所述阵列基板区分为显示区与包围所述显示区的边框区，所述应力平衡层从所述间隔区覆盖至所述边框区内。
本发明的有益效果在于，提供一种阵列基板及其制作方法，通过在间隔区、边框区或第一走线和/或第二走线上设置应力平衡层，利用应力平衡层材质的压应力平衡走线的拉翘应力，改善阵列基板在制备过程中的翘曲破片问题。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1a为本发明实施例中一种阵列基板的截面结构示意图；
图1b为本发明实施例中一种阵列基板的俯视结构示意图；
图2为本发明实施例中另一种阵列基板的截面结构示意图；
图3为本发明实施例中在大板结构切割为小板结构形成阵列基板前的平面结构示意图；
图4为本发明实施例中一种阵列基板的制作方法的流程图。
图5为本发明实施例中另一种阵列基板的制作方法的流程图。
图中部件标识如下：
衬底基板层1，第一走线层2，绝缘层3，
应力平衡层4，第二走线层5，钝化层6，
阵列基板10，大板结构11，小板结构12，
第一走线21，显示区101，边框区102，
间隙区103。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1a、图1b、图2所示，本发明其中一实施例中提供一种阵列基板10；所述阵列基板10包括衬底基板层1、第一走线层2、绝缘层3以及应力平衡层4；所述第一走线层2设于所述衬底基板层1上；所述第一走线层2包括第一走线21；所述绝缘层3设于所述第一走线层2上且覆盖在所述第一走线21上方；所述应力平衡层4设于所述绝缘层3上方且围绕所述衬底基板层1边缘，其中，所述应力平衡层4的边缘与所述衬底基板层1的所述边缘切齐；所述应力平衡层4与所述第一走线21的弯曲应力方向相反，所述应力平衡层4弯曲的曲率小于1.2mm/m，从而弯曲应力相互抵消，进而保证制备的阵列基板10为平直的结构。
于本申请一实施例中，所述衬底基板层1优选为玻璃基板或者包含玻璃基板的结构。所述第一走线21的材质包括铜(Cu)，所述第一走线21的厚度Dm大于或等于5500埃，优选Dm为5500埃至15500埃；所述绝缘层3的材质包括氧化硅和/或氮化硅；所述应力平衡层4的材质包括砷、多晶硅、SINx、SiQx、IGZO中的任一种；所述应力平衡层4的厚度Da大于或等于900埃，优选Da为900埃至5600埃。所述应力平衡层4覆盖在所述第一走线21上方。当所述应力平衡层4的材质为多晶硅、SINx、SiQx、IGZO中的任一种时，在沉积多晶硅、SINx、SiQx、IGZO形成所述应力平衡层4中的H含量低于采用同样材质制备半导体层形成有源层结构时的H含量，具体是调整制备过程中的温度、H含量、氮硅比使其形成的成膜层为压应力，如降低SiH4流量，降低NH3流量，增加N2流量。目前所述应力平衡层4的翘曲度卡控在1.2mm以下，具体需要根据衬底基板层1中玻璃基板的韧性还有制程设备确定所述应力平衡层4的翘曲度(即曲率)。
请参阅图1a、图2所示，优选所述第一走线21为栅极走线(扫描线)，所述绝缘层3为栅极绝缘层。请参阅图3所示，优选在制作阵列基板10的大板结构11内包括多个小板结构12，每一小板结构12被切割后形成具有完整驱动功能的阵列基板10，每一小板结构12的阵列基板10包括显示区101和环绕所述显示区101设置的边框区102，在相邻两个小板结构12之间的边缘位置设置间隙区103，大板结构11通过在所述间隙区103位置切割形成切割线，经切割后形成多个小板结构12。其中所述应力平衡层4设置于所述边框区102内。
由于所述第一走线21的材质为铜，经分析，铜拉(张)应力导致阵列基板翘曲的原理为：在物理气相沉积(PVD)方式采用铜材质成膜，图案化处理形成所述第一走线21后，所述第一走线21薄膜和衬底基板层1从热状态到冷状态迁移，衬底基板层1包含玻璃，玻璃的热膨胀系数小于铜的热膨胀系数，引起第一走线21对衬底基板层1的张应力，使得衬底基板层1的两端向上翘起而弯曲，当应力过大时甚至会导致衬底基板层1中的玻璃破裂。而且所述第一走线21的膜层越厚，应力越大，导致制备阵列基板的玻璃无论显示区10还是边框区102均容易受第一走线21的拉伸应力而发生翘曲甚至破片。因此，本申请通过在第一走线21上设置应力平衡层4，利用应力平衡层4材质的压应力平衡第一走线21的拉应力，改善阵列基板10在制备过程中大板结构11的翘曲破片问题。
请参阅图2所示，于本申请一实施例中，所述阵列基板10还包括第二走线层5以及钝化层6；所述第二走线层5设于所述应力平衡层4上；所述第二走线层5与所述第一走线层2对应设置；所述钝化层6设于所述绝缘层3上且覆盖在所述第二走线层5上。其中优选所述第二走线层5为源漏极走线(数据线)。所述第二走线层5的材质包括铜，所述第二走线层5的厚度大于或等于5500埃，优选为5500埃至15500埃。
可理解的是，也可在所述钝化层6上对应所述第二走线层5位置设置另一应力平衡层，两层应力平衡层可有效增大对阵列基板的应力平衡作用，有效改善阵列基板在制备过程中的翘曲破片问题。
请结合图1a-图3并参考图4所示，本发明一实施例中提供一种阵列基板的制作方法，包括以下步骤S11-S16：
S11、制作第一走线层步骤，在一衬底基板层1(大板结构11)上制作多组相同的第一走线层2图案，每一组所述第一走线层2图案包括第一走线21，所述多组第一走线层2图案在所述衬底基板层1上排列成阵列且彼此间隔；
S12、制作绝缘层步骤，制作绝缘层3覆盖在所述多组第一走线层2图案及所述衬底基板层1上；
S13、制作应力平衡层步骤，在所述绝缘层3上制作应力平衡层4，所述应力平衡层4覆盖所述多组第一走线层2图案之间的间隔区103；当所述应力平衡层4的材质为多晶硅、SINx、SiQx、IGZO中的任一种时，在沉积多晶硅、SINx、SiQx、IGZO形成所述应力平衡层4中的H含量低于采用同样材质制备半导体层形成有源层结构时的H含量，具体是调整制备过程中的温度、H含量、氮硅比使其形成的成膜层为压应力，如降低SiH4流量，降低NH3流量，增加N2流量；目前所述应力平衡层4的翘曲度卡控在1.2mm以下，具体需要根据衬底基板层1中玻璃基板的韧性还有制程设备确定所述应力平衡层4的翘曲度(即曲率)；以及
S14、切割形成阵列基板步骤，沿间隔区103将所述衬底基板层1(大板结构11)切割开以形成多片阵列基板10。
请结合图1a-图3并参考图5所示，本发明再一实施例中提供一种阵列基板的制作方法，包括以下步骤S21-S26：
S21、制作第一走线层步骤，在一衬底基板层1(大板结构11)上制作多组相同的第一走线层2图案，每一组所述第一走线层2图案包括第一走线21，所述多组第一走线层2图案在所述衬底基板层1上排列成阵列且彼此间隔；
S22、制作绝缘层步骤，制作绝缘层3覆盖在所述多组第一走线层2图案及所述衬底基板层1上；
S23、制作应力平衡层步骤，在所述绝缘层3上制作应力平衡层4，所述应力平衡层4覆盖所述多组第一走线层2图案之间的间隔区103；
S24、制作第二走线层步骤，制作第二走线层5图案，设于所述应力平衡层4上；
S25、制作钝化层步骤，制作钝化层6，设于所述第二走线层5图案上；以及
S26、切割形成阵列基板步骤，沿间隔区103将所述衬底基板层1(大板结构11)切割开以形成多片阵列基板10。
在切割后的阵列基板10中，所述应力平衡层4设于所述绝缘层3上方且围绕所述衬底基板层1边缘，其中，所述应力平衡层4的边缘与所述衬底基板层1的所述边缘切齐；所述应力平衡层4与所述第一走线21的弯曲应力方向相反，从而弯曲应力相互抵消，进而保证制备的阵列基板10为平直的结构。
于本申请一实施例中，所述衬底基板层1优选为玻璃基板或者包含玻璃基板的结构。所述第一走线21的材质包括铜(Cu)，所述第一走线21的厚度Dm大于或等于5500埃，优选Dm为5500埃至15500埃；所述绝缘层3的材质包括氧化硅和/或氮化硅；所述应力平衡层4的厚度Da大于或等于900埃，优选Da为900埃至5600埃。所述应力平衡层4覆盖在所述第一走线21上方。当所述应力平衡层4的材质为多晶硅、SINx、SiQx、IGZO中的任一种时，在沉积多晶硅、SINx、SiQx、IGZO形成所述应力平衡层4中的H含量低于采用同样材质制备半导体层形成有源层结构时的H含量，具体是调整制备过程中的温度、H含量、氮硅比使其形成的成膜层为压应力，如降低SiH4流量，降低NH3流量，增加N2流量。目前所述应力平衡层4的翘曲度卡控在1.2mm以下，具体需要根据衬底基板层1中玻璃基板的韧性还有制程设备确定所述应力平衡层4的翘曲度(即曲率)。
请参阅图3所示，在切割制作阵列基板10前的大板结构11内包括多个小板结构12，每一小板结构12被切割后形成具有完整驱动功能的阵列基板10，每一小板结构12的阵列基板10包括显示区101和环绕所述显示区101设置的边框区102，在相邻两个小板结构12之间的边缘位置设置间隙区103，大板结构11通过在所述间隙区103位置切割形成切割线，经切割后形成多个小板结构12。其中所述应力平衡层4设置于所述边框区102内。
由于所述第一走线21的材质为铜，经分析，铜拉(张)应力导致阵列基板翘曲的原理为：在物理气相沉积(PVD)方式采用铜材质成膜，图案化处理形成所述第一走线21后，所述第一走线21薄膜和衬底基板层1从热状态到冷状态迁移，衬底基板层1包含玻璃，玻璃的热膨胀系数小于铜的热膨胀系数，引起第一走线21对衬底基板层1的张应力，使得衬底基板层1的两端向上翘起而弯曲，当应力过大时甚至会导致衬底基板层1中的玻璃破裂。而且所述第一走线21的膜层越厚，应力越大，导致制备阵列基板10的玻璃无论显示区101还是边框区102均容易受第一走线21的拉伸应力而发生翘曲甚至破片。因此，本申请通过在第一走线21上设置应力平衡层4，利用应力平衡层4材质的压应力平衡第一走线21的拉应力，改善阵列基板10在制备过程中大板结构11的翘曲破片问题。
可理解的是，也可在所述钝化层6上对应所述第二走线层5位置设置另一应力平衡层，两层应力平衡层可有效增大对阵列基板10的应力平衡作用，有效改善阵列基板10在制备过程中大板结构11的翘曲破片问题。
本发明的有益效果在于，提供一种阵列基板及其制作方法，通过在间隔区、边框区或第一走线和/或第二走线上设置应力平衡层，利用应力平衡层材质的压应力平衡的拉应力，改善阵列基板在制备过程中的翘曲破片问题。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

1.一种阵列基板，其特征在于，包括：
衬底基板层；
第一走线层，设于所述衬底基板层上；所述第一走线层包括第一走线；
绝缘层，设于所述第一走线层上且覆盖在所述第一走线上方；以及
应力平衡层，设于所述绝缘层上方且围绕所述衬底基板层边缘，所述应力平衡层覆盖在所述第一走线上方，其中，所述应力平衡层的边缘与所述衬底基板层的所述边缘切齐，所述阵列基板区分为显示区与包围所述显示区的边框区，所述应力平衡层设置于所述边框区内，所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m。
2.根据权利要求1所述的阵列基板，其特征在于，所述第一走线层的材质包括铜，所述第一走线的厚度大于或等于5500埃；所述应力平衡层的材质包括砷、多晶硅、SINx、SiQx、IGZO中的任一种；所述应力平衡层的厚度大于或等于900埃。
3.根据权利要求1所述的阵列基板，其特征在于，还包括：
第二走线层，设于所述应力平衡层上；以及
钝化层，设于所述第二走线层上。
4.一种阵列基板的制作方法，其特征在于，包括步骤：
在一衬底基板层上制作多组相同的第一走线层图案，每一组所述第一走线层图案包括第一走线，所述多组第一走线层图案在所述衬底基板层上排列成阵列且彼此间隔；
制作绝缘层覆盖在所述多组第一走线层图案及所述衬底基板层上；
在所述绝缘层上制作应力平衡层，所述应力平衡层覆盖所述多组第一走线层图案之间的间隔区；所述应力平衡层覆盖在所述第一走线上方，所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m；以及
沿间隔区将所述衬底基板层切割开以形成多片阵列基板，所述阵列基板区分为显示区与包围所述显示区的边框区，所述应力平衡层设置于所述边框区内。
5.根据权利要求4所述的阵列基板的制作方法，其特征在于，所述第一走线层图案的材质包括铜，所述第一走线的厚度大于或等于5500埃；所述应力平衡层的材质包括砷、多晶硅、SINx、SiQx、IGZO中的任一种；所述应力平衡层的厚度大于或等于900埃。
6.根据权利要求4所述的阵列基板的制作方法，其特征在于，所述应力平衡层覆盖在所述第一走线上方。
7.一种阵列基板的制作方法，其特征在于，包括步骤：
在一衬底基板层上制作多组相同的第一走线层图案，每一组所述第一走线层图案包括第一走线，所述多组第一走线层图案在所述衬底基板层上排列成阵列且彼此间隔；
制作绝缘层覆盖在所述多组第一走线层图案及所述衬底基板层上；
在所述绝缘层上制作应力平衡层，所述应力平衡层覆盖所述多组第一走线层图案之间的间隔区；所述应力平衡层具有与所述第一走线方向相反的弯曲应力，所述应力平衡层弯曲的曲率小于1.2mm/m；
制作第二走线层图案，设于所述应力平衡层上；
制作钝化层，设于所述第二走线层图案上；以及
沿间隔区将所述衬底基板层切割开以形成多片阵列基板。
8.根据权利要求7所述的阵列基板的制作方法，其特征在于，所述阵列基板区分为显示区与包围所述显示区的边框区，所述应力平衡层从所述间隔区覆盖至所述边框区内。
CN202110906895.5A 2021-08-09 2021-08-09 阵列基板及其制作方法 Active CN113690250B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202110906895.5A CN113690250B (zh) 2021-08-09 2021-08-09 阵列基板及其制作方法
PCT/CN2021/112988 WO2023015579A1 (zh) 2021-08-09 2021-08-17 阵列基板及其制作方法
US17/600,406 US11984456B2 (en) 2021-08-09 2021-08-17 Array base plate and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110906895.5A CN113690250B (zh) 2021-08-09 2021-08-09 阵列基板及其制作方法

Publications (2)

Publication Number Publication Date
CN113690250A CN113690250A (zh) 2021-11-23
CN113690250B true CN113690250B (zh) 2023-10-17

Family

ID=78579148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110906895.5A Active CN113690250B (zh) 2021-08-09 2021-08-09 阵列基板及其制作方法

Country Status (3)

Country Link
US (1) US11984456B2 (zh)
CN (1) CN113690250B (zh)
WO (1) WO2023015579A1 (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887416A (zh) * 2019-03-15 2019-06-14 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
WO2021077354A1 (zh) * 2019-10-24 2021-04-29 京东方科技集团股份有限公司 驱动基板及其制作方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090011261A (ko) * 2007-07-25 2009-02-02 삼성전자주식회사 표시장치용 어레이 기판 및 이의 제조 방법
CN107634086B (zh) * 2017-09-15 2020-03-03 京东方科技集团股份有限公司 一种柔性阵列基板及制备方法、显示装置
CN108598135A (zh) * 2018-06-06 2018-09-28 武汉华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN109256400B (zh) * 2018-11-16 2021-01-26 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
CN112908985B (zh) * 2021-01-27 2023-10-31 Tcl华星光电技术有限公司 一种阵列基板及显示面板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887416A (zh) * 2019-03-15 2019-06-14 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
WO2021077354A1 (zh) * 2019-10-24 2021-04-29 京东方科技集团股份有限公司 驱动基板及其制作方法、显示装置

Also Published As

Publication number Publication date
WO2023015579A1 (zh) 2023-02-16
US11984456B2 (en) 2024-05-14
CN113690250A (zh) 2021-11-23
US20240047479A1 (en) 2024-02-08

Similar Documents

Publication Publication Date Title
CN107331294A (zh) 显示面板及显示装置
US8107029B2 (en) Thin film transistor substrate
CN108874256B (zh) 显示面板和显示装置
CN101097928B (zh) 薄膜晶体管阵列基板及其制造方法
KR101270484B1 (ko) 어레이 기판 및 그 제조 방법
JP2002246605A (ja) 液晶表示用薄膜トランジスタの製造方法
KR20020024466A (ko) 액정 표시 장치용 어레이 기판 및 그의 제조 방법
CN111710726B (zh) 薄膜晶体管基板及薄膜晶体管基板的制备方法
CN113690250B (zh) 阵列基板及其制作方法
US20190221673A1 (en) Thin film transistor and manufacturing method therefor, array substrate, display panel and display device
CN116504791A (zh) 一种薄膜晶体管、栅极行驱动电路及阵列基板
US7582903B2 (en) Thin film transistor array panel
CN108062914A (zh) 显示基板及其制造方法、显示装置
CN207352892U (zh) 一种显示面板及显示装置
CN108461492A (zh) 薄膜晶体管阵列基板、显示面板以及显示装置
WO2014172957A1 (zh) 电路板、其制作方法以及显示装置
US10546882B2 (en) Array substrate and manufacturing method thereof, display panel and display device
WO2017020345A1 (zh) 阵列基板及其制作方法
WO2018205740A1 (zh) 薄膜晶体管结构及其制作方法、电路结构、显示基板及显示装置
CN205177844U (zh) 一种柔性导电线及设置有所述柔性导电性的柔性背板
CN1996618A (zh) 薄膜晶体管
TW202225796A (zh) 顯示面板
CN110010698B (zh) 薄膜晶体管及其制备方法、显示基板、显示装置
JP3202342B2 (ja) アレイ基板の製造方法
CN101330063A (zh) 有源元件阵列结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant