CN113628977A - Frame and copper sheet device packaging design method - Google Patents
Frame and copper sheet device packaging design method Download PDFInfo
- Publication number
- CN113628977A CN113628977A CN202110682635.4A CN202110682635A CN113628977A CN 113628977 A CN113628977 A CN 113628977A CN 202110682635 A CN202110682635 A CN 202110682635A CN 113628977 A CN113628977 A CN 113628977A
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- Prior art keywords
- frame
- area
- copper sheet
- chip
- arranging
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Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 30
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 30
- 239000010949 copper Substances 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims abstract description 17
- 230000001070 adhesive effect Effects 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000011159 matrix material Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000005520 cutting process Methods 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a packaging design method of a frame and a copper sheet device, which comprises the following steps: (1) manufacturing an upper leader framework: arranging a plurality of upper frame units which are arranged in a matrix and are square on a copper sheet; (2) making a lower leader framework: arranging a plurality of lower frame units which are arranged in a matrix and are square on the other copper sheet, wherein the central area of each lower frame unit is a lower frame chip bonding area, and a lower frame semi-etching area is arranged in the middle of each lower frame chip bonding area; a plurality of lower frame positioning holes are formed in the frame of the lower lead fram frame; (3) attaching the chip to an upper frame chip attaching area of an upper lead fram frame, and attaching the other side of the chip to a lower frame chip attaching area of a lower lead fram frame by using an adhesive material; (4) and putting the whole into a DFN/QFN die for plastic package. The method can simplify the processing procedure, improve the processing efficiency and reduce the processing cost.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a packaging design method for a frame and a copper sheet device.
Background
The existing packaging design of the frame and the copper sheet device has the problems of complex process, more process steps and the like, so that the improvement space exists. Therefore, more advanced frame and copper device package designs are necessary for mass production.
Disclosure of Invention
The invention aims to solve the problems and provides a packaging design method for a frame and a copper sheet device, which can simplify the processing procedure, improve the processing efficiency and reduce the processing cost.
The technical scheme of the invention is realized in such a way.
A frame and copper sheet device packaging design method is characterized by comprising the following steps:
(1) manufacturing an upper leader framework: arranging a plurality of upper frame units which are arranged in a matrix and are square in shape on a copper sheet, arranging an upper frame reserved cutting channel between every two adjacent upper frame units, respectively arranging 4 trapezoidal upper frame etching areas on four sides of each upper frame unit, and arranging an upper frame chip bonding area in the central area of each upper frame unit;
(2) making a lower leader framework: arranging a plurality of lower frame units which are arranged in a matrix and are square in shape on the other copper sheet, arranging a lower frame reserved cutting channel between every two adjacent lower frame units, respectively arranging 4 trapezoidal lower frame etching areas on four sides of each lower frame unit, wherein the central area of each lower frame unit is a lower frame chip bonding area, and the middle part of each lower frame chip bonding area is provided with a lower frame semi-etching area; a plurality of lower frame positioning holes are formed in the frame of the lower lead fram frame;
(3) the chip is attached to an upper frame chip attachment area of an upper lead fram frame, the other side of the chip is attached to a lower frame chip attachment area of a lower lead fram frame through an adhesive material, and the offset, the rotation angle and the inclination of the chip are controlled within a certain range in the attachment process.
(4) And putting the whole into a DFN/QFN die for plastic package.
Further, the sizes of the frame units, the reserved cutting path, the trapezoidal upper frame etching area and the chip attaching area of the upper lead frame and the lower lead frame are respectively equal.
Further, the outer dimension of the upper leadfram frame is 230mm 60mm and the thickness is 0.1mm, and the outer dimension of the lower leadfram frame is 258mm 78mm and the thickness is 0.5 mm.
Further, the size of the frame unit is 8mm by 8mm, and the width of the reserved cutting track is 0.3 mm.
Further, the size of the chip bonding area is 6mm by 6 mm.
Furthermore, the half-etched area is rectangular, the size is 5mm x 3mm, and the etching depth is 300 μm.
Furthermore, the adhesive material is conductive silver adhesive, and the thickness of the conductive silver adhesive is 40-50 μm.
The invention has the beneficial effects that: 1. the method can simplify the processing procedure when the chip is attached by improving the design of the copper sheet device before the chip is attached, and the design of the copper sheet device is batch production, thereby being beneficial to improving the processing efficiency and reducing the processing cost; 2. because the process is simplified, the processing quality of the product is favorably controlled, and the yield of the product is improved.
Drawings
FIG. 1 is a schematic diagram of the product structure of the upper leader framework used in the method of the present invention.
FIG. 2 is a schematic diagram of the product structure of the lower LEADFram framework used in the method of the present invention.
Fig. 3 is a schematic diagram of the first half of the prior art packaging method.
Fig. 4 is a process diagram of the second half of the prior art packaging method.
In the figure, 1, an upper lead fram frame, 11, an upper frame reserved cutting path, 12, an upper frame etching area, 13, an upper frame chip bonding area, 2, a lower lead fram frame, 21, a lower frame reserved cutting path, 22, a lower frame full etching area, 23, a lower frame chip bonding area, 24, a lower frame half etching area, 25, a lower frame positioning hole, 3, a chip, 4, an adhesive material, 5 and an adhesive material.
Detailed Description
The technical solution of the present invention will be further described in detail by the following examples and the drawings attached to the specification.
As shown in fig. 1-2, the method for designing the package of the frame and the copper sheet device of the present invention comprises the following steps:
(1) manufacturing an upper leader framework 1: arranging a plurality of upper frame units which are arranged in a matrix and are square on a copper sheet, arranging an upper frame reserved cutting channel 11 between every two adjacent upper frame units, respectively arranging 4 trapezoidal upper frame etching areas 12 on four sides of each upper frame unit, and arranging an upper frame chip bonding area 13 in the central area of each upper frame unit;
(2) making a lower leader framework 2: arranging a plurality of lower frame units which are arranged in a matrix and are square on the other copper sheet, arranging a lower frame reserved cutting channel 21 between every two adjacent lower frame units, respectively arranging 4 trapezoidal lower frame etching areas 22 on four sides of each lower frame unit, arranging a lower frame chip bonding area 23 in the central area of each lower frame unit, and arranging a lower frame half etching area 24 in the middle of each lower frame chip bonding area; a plurality of lower frame positioning holes 25 are formed in the frame of the lower leadfram frame;
(3) the chip is attached to the upper frame chip attachment area 13 of the upper lead fram frame 1, the other side of the chip is attached to the lower frame chip attachment area 23 of the lower lead fram frame 2 through the adhesive material 4, and the offset, the rotation angle and the inclination of the chip are controlled within a certain range in the attaching process.
(4) And putting the whole into a DFN/QFN die for plastic package.
The sizes of the frame units, the reserved cutting path, the trapezoidal upper frame etching area and the chip attaching area of the upper lead fram frame 1 and the lower lead fram frame 2 are respectively equal.
The outer dimension of the upper leadfram frame 1 is 230mm 60mm, the thickness is 0.1mm, the outer dimension of the lower leadfram frame 2 is 258mm 78mm, and the thickness is 0.5 mm.
The size of the frame unit is 8mm, and the width of the reserved cutting channel is 0.3 mm.
The size of the chip attaching area is 6mm by 6 mm.
The semi-etched area is rectangular, the size is 5mm x 3mm, and the etching depth is 300 mu m.
The adhesive material 4 is conductive silver adhesive, and the thickness of the conductive silver adhesive is 40-50 mu m.
As shown in fig. 3 and 4, the conventional packaging design method for the frame and copper sheet device includes the following steps:
the first half procedure:
(1) the thickness of the copper base plate 5 is 0.203mm, and only the lower frame positioning hole 25 corresponding to the 0.75mm DFN mould is processed on the copper base plate 5;
(2) attaching one side of the upper lead fram frame 1 with the chip 3 attached to the copper backing plate 5 by using an adhesive material 4;
(3) and putting the whole body into a die for plastic package.
The second half process:
(1) the thickness of the lower leader fram frame 2 is 0.5mm, and lower frame positioning holes 25 corresponding to 0.75mm DFN die are processed.
(2) After etching the lower leadfram frame 2, the die 3 is attached to the lower leadframe half etch 24 on the lower leadfram frame 2 with an adhesive material 4 (conductive silver paste).
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (7)
1. A frame and copper sheet device packaging design method is characterized by comprising the following steps:
(1) manufacturing an upper leader framework: arranging a plurality of upper frame units which are arranged in a matrix and are square in shape on a copper sheet, arranging an upper frame reserved cutting channel between every two adjacent upper frame units, respectively arranging 4 trapezoidal upper frame etching areas on four sides of each upper frame unit, and arranging an upper frame chip bonding area in the central area of each upper frame unit;
(2) making a lower leader framework: arranging a plurality of lower frame units which are arranged in a matrix and are square in shape on the other copper sheet, arranging a lower frame reserved cutting channel between every two adjacent lower frame units, respectively arranging 4 trapezoidal lower frame etching areas on four sides of each lower frame unit, wherein the central area of each lower frame unit is a lower frame chip bonding area, and the middle part of each lower frame chip bonding area is provided with a lower frame semi-etching area; a plurality of lower frame positioning holes are formed in the frame of the lower lead fram frame;
(3) attaching the chip to an upper frame chip attachment area of an upper lead fram frame, attaching the other side of the chip to a lower frame chip attachment area of a lower lead fram frame by using an adhesive material, and controlling the offset, the rotation angle and the inclination of the patch within a certain range in the attaching process;
(4) and putting the whole into a DFN/QFN die for plastic package.
2. The frame and copper sheet device package design method of claim 1, wherein: the sizes of the frame units, the reserved cutting path, the trapezoidal upper frame etching area and the chip attaching area of the upper lead fram frame and the lower lead fram frame are respectively equal.
3. The frame and copper sheet device package design method of claim 1, wherein: the outer dimension of the upper leadfram frame is 230mm 60mm, the thickness is 0.1mm, the outer dimension of the lower leadfram frame is 258mm 78mm, and the thickness is 0.5 mm.
4. The frame and copper sheet device package design method of claim 1, wherein: the size of the frame unit is 8mm, and the width of the reserved cutting channel is 0.3 mm.
5. The frame and copper sheet device package design method of claim 1, wherein: the size of the chip attaching area is 6mm by 6 mm.
6. The frame and copper sheet device package design method of claim 1, wherein: the semi-etched area is rectangular, the size is 5mm x 3mm, and the etching depth is 300 mu m.
7. The frame and copper sheet device package design method of claim 1, wherein: the adhesive material is conductive silver adhesive, and the thickness of the conductive silver adhesive is 40-50 mu m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110682635.4A CN113628977A (en) | 2021-06-21 | 2021-06-21 | Frame and copper sheet device packaging design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110682635.4A CN113628977A (en) | 2021-06-21 | 2021-06-21 | Frame and copper sheet device packaging design method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113628977A true CN113628977A (en) | 2021-11-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110682635.4A Pending CN113628977A (en) | 2021-06-21 | 2021-06-21 | Frame and copper sheet device packaging design method |
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| Country | Link |
|---|---|
| CN (1) | CN113628977A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489218B1 (en) * | 2001-06-21 | 2002-12-03 | Advanced Semiconductor Engineering, Inc. | Singulation method used in leadless packaging process |
| CN102629599A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Quad flat no lead package and production method thereof |
| CN105355619A (en) * | 2015-12-03 | 2016-02-24 | 日月光封装测试(上海)有限公司 | Lead frame bar |
| CN107195612A (en) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | One kind is based on pin QFN frameworks in lengthening half-etching arch and its encapsulation chip |
| CN206806329U (en) * | 2017-05-10 | 2017-12-26 | 深圳市三联盛科技股份有限公司 | A kind of novel high-density frame structure of semiconductor packages circuit |
| CN208923199U (en) * | 2018-11-15 | 2019-05-31 | 上海华友金裕微电子有限公司 | A kind of envelope examining system of semiconductor indium antimonide hall device |
| CN110661169A (en) * | 2018-06-28 | 2020-01-07 | 潍坊华光光电子有限公司 | Preparation method of small-size low-cost SMD (surface mounted device) packaged VCSEL (vertical surface emitting laser) |
| CN110690189A (en) * | 2019-10-24 | 2020-01-14 | 天水华天科技股份有限公司 | eHSOP5L lead frame of high-power drive circuit, packaging part and production method thereof |
| CN111403296A (en) * | 2020-03-30 | 2020-07-10 | 捷捷微电(上海)科技有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| CN111524868A (en) * | 2020-03-25 | 2020-08-11 | 长电科技（宿迁）有限公司 | Combined structure of lead frame and metal clamping piece and riveting and chip mounting process |
-
2021
- 2021-06-21 CN CN202110682635.4A patent/CN113628977A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489218B1 (en) * | 2001-06-21 | 2002-12-03 | Advanced Semiconductor Engineering, Inc. | Singulation method used in leadless packaging process |
| CN102629599A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Quad flat no lead package and production method thereof |
| CN105355619A (en) * | 2015-12-03 | 2016-02-24 | 日月光封装测试(上海)有限公司 | Lead frame bar |
| CN206806329U (en) * | 2017-05-10 | 2017-12-26 | 深圳市三联盛科技股份有限公司 | A kind of novel high-density frame structure of semiconductor packages circuit |
| CN107195612A (en) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | One kind is based on pin QFN frameworks in lengthening half-etching arch and its encapsulation chip |
| CN110661169A (en) * | 2018-06-28 | 2020-01-07 | 潍坊华光光电子有限公司 | Preparation method of small-size low-cost SMD (surface mounted device) packaged VCSEL (vertical surface emitting laser) |
| CN208923199U (en) * | 2018-11-15 | 2019-05-31 | 上海华友金裕微电子有限公司 | A kind of envelope examining system of semiconductor indium antimonide hall device |
| CN110690189A (en) * | 2019-10-24 | 2020-01-14 | 天水华天科技股份有限公司 | eHSOP5L lead frame of high-power drive circuit, packaging part and production method thereof |
| CN111524868A (en) * | 2020-03-25 | 2020-08-11 | 长电科技（宿迁）有限公司 | Combined structure of lead frame and metal clamping piece and riveting and chip mounting process |
| CN111403296A (en) * | 2020-03-30 | 2020-07-10 | 捷捷微电(上海)科技有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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