CN206806329U - A kind of novel high-density frame structure of semiconductor packages circuit - Google Patents

A kind of novel high-density frame structure of semiconductor packages circuit Download PDF

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Publication number
CN206806329U
CN206806329U CN201720513631.2U CN201720513631U CN206806329U CN 206806329 U CN206806329 U CN 206806329U CN 201720513631 U CN201720513631 U CN 201720513631U CN 206806329 U CN206806329 U CN 206806329U
Authority
CN
China
Prior art keywords
lead frame
chip carrier
conducting resinl
chip
novel high
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201720513631.2U
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Chinese (zh)
Inventor
陈林
郑天凤
朱仕镇
韩壮勇
朱文锋
吴富友
刘志华
刘群英
朱海涛
张团结
王鹏飞
曹丙平
周贝贝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Sanlian Polytron Technologies Inc
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Shenzhen Sanlian Polytron Technologies Inc
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Publication date
Application filed by Shenzhen Sanlian Polytron Technologies Inc filed Critical Shenzhen Sanlian Polytron Technologies Inc
Priority to CN201720513631.2U priority Critical patent/CN206806329U/en
Application granted granted Critical
Publication of CN206806329U publication Critical patent/CN206806329U/en
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Anticipated expiration legal-status Critical

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

It the utility model is related to technical field of semiconductor encapsulation, a kind of more particularly to novel high-density frame structure of semiconductor packages circuit, including multiple lead frame units, the lead frame unit is connected with each other by dowel, the lead frame cell surface is layers of copper, the lead frame unit includes chip carrier and pin, and chip is pasted onto on chip carrier by conducting resinl, and the chip carrier is provided with the excessive spilling for being used to prevent conducting resinl and hinders glue groove.The lead frame cell surface is layers of copper, and copper and plastic-sealed body associativity are fairly good, ensures adhesion from the selection of basic material, especially the semiconductor devices of one side encapsulation, and the adhesion of lead frame and plastic-sealed body seems more important;In addition on chip carrier set resistance glue groove, can prevent conducting resinl excessive spilling or conducting resinl in sovent diffusion, avoid stain lead frame unit, improve product reliability.

Description

A kind of novel high-density frame structure of semiconductor packages circuit
Technical field
It the utility model is related to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor packages circuit is new highly dense Spend frame structure.
Background technology
With the continuous development of semiconductor packaging industry, in the performance of product, size, cost reliability etc. requirement Improve constantly, when performance is higher, size is more thin smaller, and cost is lower, and the reliability of product is just more difficult to realize.It is good in order to realize Electrical property and heat dispersion, many products still more using lead frame be carrier packing forms, lead frame Arrangement also develops to high density direction, and the product of this classification has good advantage, but plastic packaging in price in performance, size The coefficient of thermal expansion differences of body and lead frame is very big, and associativity is poor, the wet system such as latitude, plating of being removed photoresist in the post-order process of encapsulation Steam caused by journey has an opportunity the faying face for invading lead frame and plastic-sealed body, and reliability but runs into very big challenge, and humidity is quick It is low to feel grade, easily produces layering, or even pulls bonding wire, forms electrical property failure;Other chip is by conductive adhesive in chip On seat, the electrical and thermal conductivity performance of conducting resinl can also have an impact to the reliability of product, and conducting resinl generally comprises solvent and host, Once conducting resinl excessive spilling or it is long when place sovent diffusion in conducting resinl, lead frame can be stain, reduce product can By property.
Utility model content
The purpose of this utility model is to provide a kind of associativity for improving plastic-sealed body and lead frame, the half of high reliability The novel high-density frame structure of conductor encapsulated circuit.
What the utility model was realized in:A kind of novel high-density frame structure of semiconductor packages circuit, including it is more Individual lead frame unit, the lead frame unit are connected with each other by dowel, and the lead frame cell surface is layers of copper, described to draw Wire frame unit includes chip carrier and pin, and chip is pasted onto on chip carrier by conducting resinl, and the chip carrier, which is provided with, to be used to prevent The only excessive spilling resistance glue groove of conducting resinl.
Wherein, the resistance glue groove section is V-type, depth 0.1mm, width 0.2-0.5mm.
Wherein, it is additionally provided with perforate on the chip carrier and pin.
Wherein, the edge of the chip carrier and pin is provided with groove.
Wherein, the chip carrier and pin surface are additionally provided with half corrosion region.
The beneficial effects of the utility model are:The main material with faying face of the adhesion of lead frame and plastic-sealed body faying face Expect relevant, the referred to herein as material of lead frame surface, for adhesion, copper and plastic-sealed body associativity are fairly good, and palladium Gold surface is taken second place, and silver surface then differs many, and lead frame cell surface described in the utility model is layers of copper, from the choosing of basic material Select guarantee adhesion, especially the semiconductor devices of one side encapsulation, the adhesion of lead frame and plastic-sealed body, which seems, more to be aggravated Will;In addition on chip carrier set resistance glue groove, can prevent conducting resinl excessive spilling or conducting resinl in sovent diffusion, avoid Lead frame unit is stain, improves product reliability.
Brief description of the drawings
Fig. 1 is the structural representation of the novel high-density frame structure embodiment of semiconductor packages circuit described in the utility model Figure;
Fig. 2 is the product diagrammatic cross-section after frame structure encapsulation described in the utility model.
Wherein, 1, lead frame unit;11st, chip carrier;12nd, pin;13rd, glue groove is hindered;14th, perforate;15th, groove;2nd, core Piece;3rd, plastic-sealed body.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining The utility model, it is not used to limit the utility model.
As the novel high-density frame structure embodiment of semiconductor packages circuit described in the utility model, such as Fig. 1 and Fig. 2 It is shown, including multiple lead frame units 1, the lead frame unit 1 be connected with each other by dowel, the table of lead frame unit 1 Face is layers of copper, and the lead frame unit 1 includes chip carrier 11 and pin 12, and chip 2 is pasted onto on chip carrier 11 by conducting resinl, The chip carrier 11 is provided with the excessive spilling for being used to prevent conducting resinl and hinders glue groove 13.
The adhesion of lead frame and plastic-sealed body faying face is mainly relevant with the material of faying face, referred to herein as lead frame The material on frame surface, for adhesion, copper and plastic-sealed body associativity are fairly good, and porpezite surface is taken second place, and silver surface then differs Many, the surface of lead frame unit 1 described in the utility model is layers of copper, ensures adhesion from the selection of basic material, especially The adhesion of the semiconductor devices of one side encapsulation, lead frame unit 1 and plastic-sealed body 3 seems more important;In addition in chip carrier 11 It is upper set resistance glue groove 13, can prevent conducting resinl excessive spilling or conducting resinl in sovent diffusion, avoid stain lead frame list Member 1, improve product reliability.The resistance glue groove section is V-type, and depth can be depending on the size of chip and chip carrier, preferably It is 0.1mm, width 0.2-0.5mm to be worth for depth.
In the present embodiment, perforate 14 is additionally provided with the chip carrier 11 and pin 12, it is described to open after chip 2 is packed Hole 14 forms lock glue hole, is provided with groove 15 in the edge of the chip carrier and pin, can correspondingly form lock glue groove, can be with Increase the surface of lead frame unit 1 and the adhesion of plastic-sealed body 3.
In the present embodiment, the chip carrier and pin surface are additionally provided with half corrosion region, and the surface of half corrosion region is more thick It is rough, the contact area of material can be increased, can also increase lead frame surface and the adhesion of plastic-sealed body.
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model Protection domain within.

Claims (5)

1. a kind of novel high-density frame structure of semiconductor packages circuit, including multiple lead frame units, the lead frame list Member is connected with each other by dowel, it is characterised in that the lead frame cell surface is layers of copper, and the lead frame unit includes core Bar and pin, chip are pasted onto on chip carrier by conducting resinl, and the chip carrier, which is provided with, to be used to prevent the excessive of conducting resinl Overflow resistance glue groove.
2. the novel high-density frame structure of semiconductor packages circuit according to claim 1, it is characterised in that the resistance glue Slot cross-section is V-type, depth 0.1mm, width 0.2-0.5mm.
3. the novel high-density frame structure of semiconductor packages circuit according to claim 1, it is characterised in that the chip Perforate is additionally provided with seat and pin.
4. the novel high-density frame structure of semiconductor packages circuit according to claim 1, it is characterised in that the chip The edge of seat and pin is provided with groove.
5. the novel high-density frame structure of semiconductor packages circuit according to claim 1, it is characterised in that the chip Seat and pin surface are additionally provided with half corrosion region.
CN201720513631.2U 2017-05-10 2017-05-10 A kind of novel high-density frame structure of semiconductor packages circuit Active CN206806329U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720513631.2U CN206806329U (en) 2017-05-10 2017-05-10 A kind of novel high-density frame structure of semiconductor packages circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720513631.2U CN206806329U (en) 2017-05-10 2017-05-10 A kind of novel high-density frame structure of semiconductor packages circuit

Publications (1)

Publication Number Publication Date
CN206806329U true CN206806329U (en) 2017-12-26

Family

ID=60739821

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201720513631.2U Active CN206806329U (en) 2017-05-10 2017-05-10 A kind of novel high-density frame structure of semiconductor packages circuit

Country Status (1)

Country Link
CN (1) CN206806329U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616462A (en) * 2018-12-04 2019-04-12 四川金湾电子有限责任公司 A kind of totally-enclosed symmetric packages lead frame
CN113628977A (en) * 2021-06-21 2021-11-09 江西万年芯微电子有限公司 Frame and copper sheet device packaging design method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616462A (en) * 2018-12-04 2019-04-12 四川金湾电子有限责任公司 A kind of totally-enclosed symmetric packages lead frame
CN113628977A (en) * 2021-06-21 2021-11-09 江西万年芯微电子有限公司 Frame and copper sheet device packaging design method

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