CN113540224A - N-substrate groove type GaN insulated gate bipolar transistor - Google Patents
N-substrate groove type GaN insulated gate bipolar transistor Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention relates to an N-substrate groove type GaN insulated gate bipolar transistor, and belongs to the field of power semiconductor devices. The transistor is of a bilateral symmetry structure, and the left half structure comprises a P + collector, an N-drift region, a P-channel region, an N + emitter substrate, an insulating medium layer, a grid metal contact region, a collector metal contact region, an emitter metal contact region I and an emitter metal contact region II. The invention is based on an N + type GaN substrate material, adopts a P/N/P/N groove type IGBT vertical device structure from top to bottom, and comprehensively improves the electrical characteristics of devices such as on-resistance, turn-off time and the like.
Description
Technical Field
The invention belongs to the field of power semiconductor devices, and relates to an N-substrate groove type GaN insulated gate bipolar transistor.
Background
The semiconductor material gallium nitride (GaN) material has many advantages such as large forbidden band width, high critical breakdown field strength, large electron packet and velocity, low dielectric constant, and high operating temperature. The method comprises the following steps that firstly, the forbidden band width is large, the forbidden band width is 3.39eV and is more than 3 times of the forbidden band width of a silicon material, so that the working temperature of a semiconductor device made of a GaN material can be higher than that of semiconductor materials such as GaAs and Si; the critical breakdown field intensity of the gallium nitride is as high as 3.4MV/cm, which is higher than Si and GaAs by one order of magnitude, so that the gallium nitride device can bear high voltage and high power; the high saturation electron migration velocity reaches 3 multiplied by 107cm/s, which is much larger than semiconductor materials such as GaAs, Si, 4H-SiC and the like, allows the GaN material to be used for manufacturing high-frequency electronic devices; the low dielectric constant, GaN, is smaller than GaAs, Si, and 4H-SiC, which allows the device to operate at high frequencies and speeds.
An Insulated Gate Bipolar Transistor (IGBT) is a Bipolar semiconductor power device in which a MOSFET and a BJT are combined, has the advantages of reduced on-state voltage, low driving power consumption, high operating frequency, and the like, is widely used in the fields of communication technology, new energy devices, and various consumer electronics, and is a core device of an electronic power system.
With the increasing demand in recent years, power electronic devices with higher operating frequencies, smaller cell sizes, and lower power consumption are in constant need of innovation. To date, AlGaN/GaN interface two-dimensional electron gas has been mostly used in HEMT devices because of its ultra-high electron mobility, but conventional HFET devices are depletion-mode (normally-on) devices. Researchers have proposed various solutions in device structures and processes so far, and commercial GaN power devices mainly adopt an enhancement type Si MOSFET and a depletion type GaN device to realize the enhancement type GaN device in a Cascode cascade mode. Other solutions mainly include a P-type gate structure, a thin barrier layer structure, a groove gate structure, a fluorine-based plasma processing technology, a groove MIS-HFET structure, a field tunneling structure and the like. The invention provides an N substrate groove type GaN IGBT structure only using GaN semiconductor materials, which aims to develop a GaN power switch device with larger output current and higher power and promote the GaN materials to be applied to the field of IGBT devices.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an N-substrate trench type GaN IGBT based on an N + type GaN substrate material, which uses a P/N/P/N trench type IGBT vertical device structure from top to bottom to comprehensively improve electrical characteristics of devices such as on-resistance and turn-off time.
In order to achieve the purpose, the invention provides the following technical scheme:
the utility model provides a N substrate slot type GaN insulated gate bipolar transistor, is bilateral symmetry structure, and the structure of left half includes: the device comprises a P + collector 1, an N-drift region 2, a P-channel region 3, an N + emitter substrate 4, an insulating dielectric layer 5, a grid metal contact region 6, a collector metal contact region 7, an emitter metal contact region I8 and an emitter metal contact region II 9;
the P + collector 1 is positioned on the lower surface of the collector metal contact region 7 and is in contact with the upper surface of the N-drift region 2, and the doped (P-type) impurity concentration of the P + collector 1 is 5 multiplied by 1017cm-3(ii) a The lower surface of the N-drift region 2 is in contact with the upper surface of the P-channel region 3, the right lower surface of the N-drift region is in contact with the left upper surface of the insulating medium layer 5, and the doped (N-type) impurity concentration of the N-drift region 2 is 1 multiplied by 1016cm-3(ii) a The lower surface of the P-channel region 3 is in contact with the upper surface of the N + emitter substrate 4 and the upper surface of the emitter metal contact region II 9, the right surface of the P-channel region is in contact with the middle part of the left surface of the insulating dielectric layer 5, and the doped (P-type) impurity concentration of the P-channel region 3 is 1 multiplied by 1017cm-3(ii) a The N + emitter substrate 4 is positioned on the lower surface of the P-channel region 3 and the lower surface of the insulating medium layer 5, the lower surface of the N + emitter substrate is in contact with the upper surface of the emitter metal contact region I8, and the doped (N-type) impurity concentration of the N + emitter substrate 4 is 2 multiplied by 1018cm-3(ii) a The left surface of the insulating medium layer 5 is in contact with the right lower surface of the N-drift region 2, the right surface of the P-channel region 3 and the upper and middle surfaces of the N + emitter substrate 4; the gate metal contact region 6 is positioned on the upper surface of the insulating medium layer 5Kneading; and the emitter metal contact area II 9 is embedded in the N + emitter substrate 4, the upper surface of the emitter metal contact area II is in contact with the lower surface of the P-channel area 3, and the lower surface of the emitter metal contact area II is in contact with the upper surface of the emitter metal contact area I8.
Further, the transistor also comprises an N-buffer layer 10, wherein the N-buffer layer 10 is positioned on the lower surface of the P + collector 1 and is in contact with the upper surface of the N-drift region 2.
Further, the transistor structure is suitable for a trench type MOS transistor, namely, the P + collector 1 is replaced by an N + drain region 11.
Further, the doping concentration of the N-buffer layer 10 is 17 th power.
Further, the N + drain region 11 is doped with an impurity concentration of 17 th power.
Further, the doping (P-type) impurity concentration of the P + collector 1 is 17 th power; the concentration of doped (N-type) impurities in the N-drift region 2 is 16 th power; the concentration of doped (P-type) impurities in the P-channel region 3 is 17 th power; the N + emitter substrate 4 is doped with an (N-type) impurity to a power of 18.
Further, the material of the collector metal contact region 7 includes, but is not limited to, Al, Au, or Pt.
Further, the material of the emitter metal contact region I8 comprises but is not limited to Ti/Al/Ti/Au alloy, Ti/Al/Ni/Au alloy or Ti/Al/Mo/Au alloy; the material of the emitter metal contact area II 9 comprises but is not limited to Ni/Ti laminated gold.
Further, the material of the insulating medium layer 5 includes, but is not limited to, SiN, AlN, MgO, Ga2O3、AlHfOxAnd HfSiON, or a combination of several of them.
Further, the transistor is formed based on GaN substrate material.
The invention has the beneficial effects that: the novel structure of the trench gate GaN IGBT is formed by taking the N-type GaN as the substrate and adopting a P/N/P/N sandwich structure, the novel structure of the IGBT can give full play to the advantages of wide-bandgap semiconductor GaN materials, improves the withstand voltage of the device and reduces the specific on-resistance of the device by reducing the doping concentration of the drift region, thereby improving the Baliga optimal value FOM of the device, and simultaneously improves the hole injection efficiency of a P + collector electrode, thereby improving the output current of the device, and the influence of the reduction of the concentration of the drift region on the turn-off speed of the device is not obvious. Compared with the GaN MOS tube with the same size, the GaN MOS tube can improve the output current of the IGBT, reduce the specific on-resistance and improve the FOM when the doping concentration of the drift region and the collector region (drain region) is consistent; meanwhile, the PN junction of the IGBT collector region and the drift region does not affect the withstand voltage thereof, and has the same withstand voltage as that of the MOS tube.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural view of an N-substrate trench-type GaN Insulated Gate Bipolar Transistor (IGBT) of embodiment 1;
FIG. 2 is a schematic structural view of an N-substrate trench type GaN insulated gate bipolar transistor (FS IGBT) with a buffer layer according to embodiment 2;
fig. 3 is a GaN MOS tube structure of example 3 (same size as example 1);
FIG. 4 is a graph showing the threshold voltage curves of the GaN MOS transistor of example 1(IGBT) and the same size;
FIG. 5 is a schematic view of an output characteristic curve of the IGBT of the embodiment 1;
FIG. 6 is a schematic view showing an output characteristic curve of a GaN MOS transistor according to example 3;
FIG. 7 shows the gate voltage V in the forward conduction modegThe electron concentration transverse distribution diagram of the N-substrate groove type GaN IGBT is respectively 5V, 6V, 7V, 8V and 9V within the range that the coordinate y is 9 mu m, the x is more than or equal to 9.92 mu m and less than or equal to 10.04 mu m (a straight line BB' in figure 1);
FIG. 8 shows the gate voltage V in the forward conduction modegAre respectively provided withThe coordinate y of the GaN MOS tube with the same size is 9 mu m, 9.92 mu m is less than or equal to x is less than or equal to 10.04 mu m when the GaN MOS tube with the same size is 5V, 6V, 7V, 8V and 9V (the straight line B in the figure 3)1B1') a transverse profile of electron concentration over the range;
FIG. 9 is a schematic diagram of the forward withstand voltage curves of the GaN MOS transistor of example 1(IGBT) and the same size;
FIG. 10 shows the doping concentration of the N-drift region of the GaN MOS transistor of example 1(IGBT) and the same size15cm-3To 4X 1016cm-3When the voltage changes, the device breakdown voltage changes and contrasts with the curve chart;
fig. 11 shows the x ═ 7.99 μm (line AA' in fig. 1 and line a in fig. 3) for example 1(IGBT) and a GaN MOS transistor of the same size1A1') electric field concentration profile at device breakdown;
FIG. 12 is a graph showing the turn-on voltage curve of the IGBT of example 1;
FIG. 13 is a graph showing the turn-on voltage curve of the MOS transistor of embodiment 3;
FIG. 14 shows that in the forward conduction mode, the gate voltage Vg is 11V, and the N-drift region doping concentration of the N-substrate trench type GaN IGBT is 5 × 1015cm-3To 4X 1016cm-3When the voltage changes, the conduction voltage drop curve of the device is changed;
FIG. 15 shows GaN MOS transistors of example 1(IGBT) and example 3 with N-drift doping concentration of 5 × 1015cm-3To 3X 1016cm-3When the variation is carried out, a variation curve diagram of the specific on-resistance of the device is obtained;
FIG. 16 shows the GaN MOS transistor of embodiment 1(IGBT) and embodiment 3 with the N-drift region doping concentration of 5 × 1015cm-3To 3X 1016cm-3When the variation is carried out, a variation curve chart of the device Baliga optimal value FOM is obtained;
fig. 17 is a schematic diagram of the turn-off characteristic curve of the embodiment 1 (IGBT);
FIG. 18 is a schematic view of the main process flow of embodiment 1 (IGBT);
reference numerals: the transistor comprises a 1-P + collector, a 2-N-drift region, a 3-P-channel region, a 4-N + emitter substrate, a 5-insulating dielectric layer, a 6-grid metal contact region, a 7-collector metal contact region, an 8-emitter metal contact region I, a 9-emitter metal contact region II, a 10-N-buffer layer and a 11-N + drain region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1:
as shown in fig. 1, the present embodiment provides an N-substrate trench GaN insulated gate bipolar transistor structure, which is bilaterally symmetric, and the left half structure includes: the device comprises a P + collector 1, an N-drift region 2, a P-channel region 3, an N + emitter substrate 4, an insulating dielectric layer 5, a grid metal contact region 6, a collector metal contact region 7, an emitter metal contact region I8 and an emitter metal contact region II 9.
The P + collector 1 is arranged between the lower surface of the collector metal contact region 7 and the upper surface of the N-drift region 2, and the thickness h of the P + collector 110.5 μm, width w1The P + collector 1 was doped with P-type impurities at a concentration of 5 × 10 ═ 8 μm17cm-3。
The N-drift region 2 is positioned on the lower surface of the P + collector 1 and is in contact with the upper surface of the right part of the P-channel region 3, the right lower surface is in contact with the upper left surface of the insulating medium layer 5, and the thickness h of the N-drift region 228 μm, width w1Not less than 8 μm, and the N-drift region 2 is doped with N-type impurity at a concentration of 1 × 1016cm-3。
The P-channel region 3 is arranged between the lower surface of the N-drift region 2 and the upper surface of the N + emitter substrate 4, the right surface is contacted with the left upper surface of the insulating medium layer 5, and the thickness h of the P-channel region 331 μm, width w210 μm, and the P-channel region 3 is doped with P-type impurities at a concentration of 1 × 1017cm-3。
The N + emitter substrate 4 is positioned on the lower surface of the P-channel region 3 and an insulating medium layer (Al)2O3)5 lower surface contacting with upper surface of the emitter electrode metal Ti/Al/Ti/Au contact region 8, and N + emitter electrode substrate 4 with thickness h 32 μm and a width of 2w1+w324 μm and the N + emitter substrate 4 doped with N-type impurities at a concentration of 2 × 1018cm-3。
The insulating medium layer 5 is in contact with the right lower surface of the N-drift region 2, the right surface of the P-channel region 3 and the upper and middle surfaces of the N + emitter substrate 4, and the thickness of the insulating medium layer is 0.1 mu m.
Example 2:
as shown in fig. 2, this embodiment provides an N-substrate trench GaN insulated gate bipolar transistor structure with a buffer layer, which is bilaterally symmetric, and includes a P + collector 1, an N-drift region 2, a P-channel region 3, an N + emitter substrate 4, an insulating dielectric layer 5, a gate metal Al contact region 6, a collector metal contact region 7, an emitter metal contact region i 8, an emitter metal contact region ii 9, and an N-buffer layer 10.
Specifically, in this embodiment, based on the structure of embodiment 1 (fig. 1), only the N-buffer layer 10 is added to the transistor structure, wherein the upper surface of the N-buffer layer 10 contacts the lower surface of the P + collector 1, and the lower surface thereof contacts the upper surface of the N-drift region 2. The N-buffer layer 10 has a thickness of 1 μm and a width of 8 μm, and the doping concentration of the N-buffer layer 10 is selected to be 17 th power.
Example 3:
as shown in FIG. 3, the trench MOS transistor structure with the same size as the IGBT of FIG. 1 has a bilateral symmetry, and the left half structure comprises an N + drain region 11, an N-drift region 2, a P-channel region 3, an N + emitter substrate 4, an insulating dielectric layer 5, a gate metal contact region 6, a collector metal contact region 7, an emitter metal contact region I8 and an emitter metal Ni/Al contact region 9.
Specifically, this embodiment is to replace the P + collector 1 in embodiment 1 (fig. 1) with the N + drain region 11 of the same size.
Fig. 4 shows that T is 300K at room temperature and the concentration in the drift region 2 is 1 × 1016cm-3The doping concentration of the channel region 3 is 1 multiplied by 1017cm-3In the case of the threshold voltage curves of the IGBT and the MOS transistor in example 1 (shown in fig. 4), the data result obtained by the silver simulation is plotted by the Origin tool, and as can be seen from fig. 4, when the concentration of the P-channel region 3 is the same, the threshold voltage of the IGBT is about 4V, the threshold voltage of the MOS transistor is about 5.5V, and the threshold voltage of the MOS transistor is higher than that of the IGBT by 1.5V.
Fig. 5 shows that T is 300K at room temperature and the concentration in the drift region 2 is 1 × 1016cm-3The doping concentration of the P-channel region 3 is 1 x 1017cm-3In the case of the output characteristic curve of the (IGBT) in example 1, the data result obtained by the Silvaco simulation is plotted by the Origin tool as shown in FIG. 5, and it can be seen from FIG. 5 that V isgWhen the device is started at 2V, an inversion layer is formed on one side of the channel layer at the contact surface of the channel region 3 and the insulating medium layer 5, so that the N-drift region 2 and the N + collector 4 are conducted, electrons move from the N + collector 4 to the N-drift region 2 to form electron current, and the electron current promotes the P + collector 1 to inject the electrons into the N-drift region 2And entering holes to form a conductance modulation effect. As can be seen from fig. 5, after the channel is turned on, the output current increases first and then gradually reaches saturation as the voltage of the P + collector region 1 increases, and the saturation current also gradually increases as the gate voltage increases. It can be seen from the figure that at VdWhen the voltage is less than 3V, no current is formed although the channel is opened, because a PN junction is formed between the P + collector 1 and the N-drift region 2, the current can be formed when the collector voltage is greater than the junction voltage of the PN junction.
FIG. 6 shows the concentration of 1 × 10 in the drift region at room temperature with T300K16cm-3The doping concentration of the channel region is 1 multiplied by 1017cm-3Meanwhile, the same-size groove MOS tube outputs a characteristic curve. It can be seen from fig. 6 that when the channel concentration and the drift region concentration of the IGBT and the MOS transistor of the same size are the same, the same voltage is applied to the gate and the collector, and the maximum output current of the IGBT is about 2.3 times the maximum output current of the MOS transistor, mainly because the IGBT has a P + collector region more than the MOS transistor, when the device is turned on, the IGBT P + collector 1 injects holes into the drift region 2, and a conductance modulation effect occurs in the drift region 2, thereby increasing the output current of the IGBT.
FIG. 7 shows the concentration of 1 × 10 in the drift region at room temperature with T300K16cm-3The doping concentration of the channel region 3 is 1 multiplied by 1017cm-3When the IGBT is under different gate voltages, the lateral distribution diagram of the electron concentration in the range of the coordinate y being 9 microns, the coordinate x being 9.92 microns and less than or equal to 10.04 microns (shown by a straight line AA' in figure 1), namely the electron concentration at the inversion layer of the channel. As is clear from analysis in conjunction with fig. 5, it is clear that the larger the voltage applied to the gate electrode is, the higher the concentration of electrons at the inversion layer is, and the wider the inversion layer is formed at the side of the channel layer at the boundary between the oxide layer 5 and the channel region 3, so that the larger the number of electrons passing through the channel region per unit time is, the larger the saturation current of electrons is.
Fig. 8 shows that T is 300K at room temperature and the concentration in the drift region 2 is 1 × 1016cm-3The doping concentration of the channel region 3 is 1 multiplied by 1017cm-3When the MOS tube is under different gate pressures, the coordinate y is 9 μm, and the x is more than or equal to 9.92 μm and less than or equal to 10.05 μm (the straight line A in the figure 8)1A1' shown) within the rangeThe electron concentration lateral profile, i.e. the electron concentration at the channel inversion layer. Obviously, the larger the voltage applied to the gate electrode is, the higher the electron concentration at the inversion layer is, and analysis in conjunction with fig. 6 shows that the higher the electron concentration at the inversion layer is, the larger the saturation current of electrons is. Comparing fig. 7 and fig. 8, it can be seen that, because the threshold voltage of the IGBT is 1.5V less than that of the MOS transistor, the IGBT has a higher electron concentration than the inversion layer at the channel of the MOS transistor under the same gate voltage, and V is the voltage of the inversion layergWhen the voltage is 9V, the electron concentration at the IGBT channel is about 1.8 times that of the MOS transistor, which is also a reason why the IGBT current is larger than that of the MOS transistor at the same gate voltage.
Fig. 9 is a graph showing the forward breakdown voltage of the example 1(IGBT) and the MOS transistor at room temperature with T300K. Collector region 1 is applied with a positive voltage, and PN junction J of collector region 1 and drift region 21Forward biased, PN junction J of drift region 2 and channel region 32Reverse bias, at J, since the channel region 3 has a higher doping concentration than the drift region 22The depletion region is expanded towards the drift region 2, and the withstand voltage of the device is mainly determined by the size and doping concentration of the drift region 2. As can be seen from fig. 9, as the collector voltage gradually increases, the collector current of the device suddenly and significantly increases at a certain point, at which the device avalanche breakdown occurs, and the doping concentration of the IGBT and the MOS transistor in the drift region 2 is 1 × 1016cm-3The concentration of the channel region 3 is 1 × 1017cm-3The withstand voltage can reach 1060V, and the withstand voltage level of the GaN material reaches 132.5V/mum.
Fig. 10 shows that T is 300K at room temperature, and the doping concentration in the channel region 3 is 1 × 1017cm-3The doping concentration of the drift region 2 is 1 multiplied by 1016cm-3When in BB' and B1B1' in example 1(IGBT) and MOS tube breakdown, the electric field concentration distribution curve. Comparing fig. 10(a) and fig. 10(b) in fig. 10, it can be seen that the electric field concentration of both the IGBT and the MOS transistor reaches the maximum value at y of 6.5 μm, and the breakdown phenomenon occurs, and the electric field maximum value is 3MV/μm. Breakdown occurs here because the structure proposed in this patent is where x is 8 μm and y is 6 μm at the corners of the drift region 2, resulting in a relatively concentrated electric field.
FIG. 11 shows T300K at room temperature in the channel region3 doping concentration of 1 × 1017cm-3The doping concentration of the drift region 2 is 5 multiplied by 1015cm-3To 4X 1016cm-3And (3) a change curve of the breakdown voltage of the GaN IGBT when the voltage is changed. As can be seen from fig. 11, the breakdown voltage decreases with increasing doping concentration of the drift region 2, and in the given data, the doping concentration in the drift region 2 has a minimum value of 5 × 1015cm-3When the breakdown voltage is maximum and reaches 1388V, the voltage-resistant level of the GaN material can reach 173.5V/mum, but the limit of the GaN material can not realize N-type doping with too low concentration, so the drift region 2 of the invention has the doping concentration of 1 × 1016cm-3. PN junction J of drift region 2 and channel region 3 with increasing concentration of drift region 22The depth of the diffusion towards the drift region 2 is gradually reduced, so that the withstand voltage of the device is gradually reduced.
Fig. 12 shows that T is 300K at room temperature, and the doping concentration in the channel region 3 is 1 × 1017cm-3The doping concentration of the drift region 2 is 1 multiplied by 1016cm-3In time, embodiment 1(IGBT) turn-on voltage curve. As can be seen from FIG. 12, the voltage is applied to the collector from the beginning to the voltage VcBefore reaching 3V, no collector current is output, mainly because the PN junction voltage of the collector 1 and the drift region 2 is influenced when V iscAfter more than 3V, the collector current IcThe current is increased rapidly and reaches 100A/cm for IGBT2When the device is on, V at this timedI.e., the on-state voltage drop of the IGBT, the turn-on voltage V of embodiment 1(IGBT)on1About 3.88V and the specific on-resistance of 0.88m omega/cm2。
Fig. 13 shows that T is 300K at room temperature, and the doping concentration in the channel region 3 is 1 × 1017cm-3The doping concentration of the drift region 2 is 1 multiplied by 1016cm-3And the turn-on voltage curve of the MOS transistor with the same size as that of the embodiment 1(IGBT) is obtained. As can be seen from fig. 13, for the MOS transistor, there is no PN junction between the drift region and the collector region of the IGBT inside the device, so that a current is output when a voltage is applied to the drain, and for the MOS transistor, the current reaches 20A/cm2The device is turned on, so that the turn-on voltage of the MOS transistorVon2About 0.32V and a specific on-resistance of 1.6m omega/cm2. Comparing the data in fig. 12 and fig. 13, it can be seen that the specific on-resistance of the embodiment 1(IGBT) is reduced by 45% compared with that of the MOS transistor with the same size.
Fig. 14 shows that T is 300K at room temperature, and the doping concentration in the channel region 3 is 1 × 1017cm-3The doping concentration of the drift region 2 is 5 multiplied by 1015cm-3To 4X 1016cm-3And (3) a change curve of the conduction voltage drop of the IGBT device during change. As can be seen from fig. 14, as the doping concentration of the drift region 2 increases, the turn-on voltage drop of the IGBT device decreases gradually, because as the concentration of the drift region 2 increases gradually, the amount of minority carriers injected into the drift region from the P + collector region during forward conduction also increases gradually, so that the conductance modulation effect in the IGBT is enhanced, the resistance of the drift region 2 is reduced, and the turn-on voltage drop of the device is reduced.
Fig. 15 shows the drift region 2 doping concentration of the IGBT device of example 1 and the MOS device of example 3 at 5.0 × 1015cm-3To 3X 1016cm-3Comparative graph of specific on-resistance between. As can be seen from fig. 15, the specific on-resistance of the GaN IGBT gradually decreases with the increase in the concentration of the drift region 2 when the doping concentration of the drift region is 3 × 1016cm-3The specific on-resistance of the GaN IGBT is 0.79 m.OMEGA.. cm2(ii) a In addition, as the concentration of the drift region 2 is increased, the specific on-resistance of the MOS is gradually reduced, but the influence of the concentration of the drift region on the specific on-resistance of the MOS transistor is not great, because the collector region 1 injects minority carriers into the drift region 2 during forward conduction, and a conductivity modulation effect occurs, which greatly reduces the specific on-resistance of the device, so that the specific on-resistance of the GaN IGBT in this concentration range is smaller than the specific on-resistance of the MOS transistor, and as the doping concentration of the drift region 2 is increased, the hole injection rate of the P + collector is reduced, the influence effect on the specific on-resistance of the GaN IGBT is weakened, and as the doping concentration of the drift region 2 is continuously increased, the specific on-resistance difference between the GaN IGBT and the MOS transistor is gradually reduced.
Fig. 16 shows the drift region 2 doping concentration of the IGBT device of example 1 and the MOS device of example 3 at 5 × 1015cm-3To 3X 1016cm-3Baliga figure of merit FOM comparison between. As can be seen from FIG. 16, the FOM of the N-substrate GaN trench gate IGBT device gradually decreases with the increase of the doping concentration of the drift region 2 when the doping concentration is 5 × 1015cm-3Maximum value of 2GW/cm is obtained2(ii) a The FOM of the MOS tube device with the same size is also reduced along with the increase of the doping concentration of the drift region 2 and is 5 multiplied by 1015cm-3Maximum value of 0.72GW/cm is obtained2From the figure, it can be known that FOM of the GaN IGBT is 2.78 times of that of the MOS tube with the same size.
Fig. 17 shows that T is 300K at room temperature and the concentration in the drift region 2 is 1 × 1016cm-3The doping concentration of the channel region 3 is 1 multiplied by 1017cm-3And meanwhile, drawing a data result obtained by Silvaco simulation through an Origin tool according to an IGBT turn-off characteristic curve. At time T2X 10-6At s, the gate voltage is decreased from 12V to 0V, and the collector voltage is decreased from 10V to 0V. As can be seen from fig. 17, when T is 2 × 10-6s, the gate voltage becomes 0V, the channel is closed, the collector current is rapidly reduced, the turn-off time is calculated by the time taken for the current to be reduced from 90% to 10% of the maximum current, and the turn-off time of the IGBT is 14.3 ns.
The invention provides an N-substrate groove type GaN insulated gate bipolar transistor structure, which takes a schematic diagram 1 as an example, the main process flow is shown in FIG. 18, and the main steps are as follows:
(1) forming an N-GaN layer in the emitter region through an ion implantation process;
(2) a layer of GaN material is further extended on the surface of the whole N-GaN layer, and then P-GaN is formed through an ion implantation process;
(3) a layer of GaN material is extended on the surface of the P-GaN again, and an N-GaN channel layer is formed through an ion implantation process;
(4) continuously extending a layer of GaN material on the surface of the whole N-GaN channel layer, and forming P-GaN by two ion implantation processes;
(5) etching the device and manufacturing a gate oxide layer;
(6) and depositing a metal electrode.
In the implementation process, according to the design requirements of specific devices, the substrate material of the N-substrate trench type GaN insulated gate bipolar transistor structure provided by the invention can be silicon carbide (SiC) material and can also be sapphire and other materials to replace bulk silicon carbide (SiC) during specific manufacturing.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (10)
1. The utility model provides a N substrate slot type GaN insulated gate bipolar transistor which characterized in that, this transistor is bilateral symmetry structure, and half structure on the left side includes: the transistor comprises a P + collector (1), an N-drift region (2), a P-channel region (3), an N + emitter substrate (4), an insulating dielectric layer (5), a grid metal contact region (6), a collector metal contact region (7), an emitter metal contact region I (8) and an emitter metal contact region II (9);
the P + collector (1) is positioned on the lower surface of the collector metal contact region (7) and is in contact with the upper surface of the N-drift region (2); the lower surface of the N-drift region (2) is in contact with the upper surface of the P-channel region (3), and the right lower surface of the N-drift region is in contact with the left upper surface of the insulating medium layer (5); the lower surface of the P-channel region (3) is in contact with the upper surface of the N + emitter substrate (4) and the upper surface of the emitter metal contact region II (9), and the right surface of the P-channel region is in contact with the middle part of the left surface of the insulating medium layer (5); the N + emitter substrate (4) is positioned on the lower surface of the P-channel region (3) and the lower surface of the insulating medium layer (5), and the lower surface of the N + emitter substrate is in contact with the upper surface of the emitter metal contact region I (8); the left surface of the insulating medium layer (5) is in contact with the right lower surface of the N-drift region (2), the right surface of the P-channel region (3) and the upper middle surface of the N + emitter substrate (4); the grid metal contact region (6) is positioned on the upper surface of the insulating medium layer (5); the emitter metal contact area II (9) is embedded in the N + emitter substrate (4), the upper surface of the emitter metal contact area II is in contact with the lower surface of the P-channel area (3), and the lower surface of the emitter metal contact area II is in contact with the upper surface of the emitter metal contact area I (8).
2. The N-substrate trench GaN igbt according to claim 1, further comprising an N-buffer layer (10), wherein the N-buffer layer (10) is located on the lower surface of the P + collector (1) and contacts the upper surface of the N-drift region (2).
3. The N-substrate trench GaN igbt according to claim 1, wherein the transistor structure is suitable for a trench MOS transistor, i.e. the P + collector (1) is replaced by an N + drain region (11).
4. The N-substrate trench GaN insulated gate bipolar transistor according to claim 2, wherein the N-buffer layer (10) is doped with an impurity concentration of 17 th power.
5. The N-substrate trench GaN IGBT according to claim 3, characterized in that the N + drain region (11) is doped with an impurity concentration of 17 x.
6. The N-substrate trench GaN igbt according to claim 1, wherein the P + collector (1) is doped with an impurity concentration of 17 th power; the doping impurity concentration of the N-drift region (2) is 16 th power; the doping impurity concentration of the P-channel region (3) is 17 th power; the doping impurity concentration of the N + emitter substrate (4) is 18 th power.
7. The N-substrate trench GaN insulated gate bipolar transistor according to claim 1, characterized in that the material of the collector metal contact region (7) comprises Al, Au or Pt.
8. The N-substrate trench GaN IGBT as defined in claim 1, wherein the material of the emitter metal contact region I (8) comprises a Ti/Al/Ti/Au alloy, a Ti/Al/Ni/Au alloy, or a Ti/Al/Mo/Au alloy; and the material of the emitter metal contact area II (9) comprises Ni/Ti laminated gold.
9. The N-substrate trench GaN IGBT according to claim 1, characterized in that the material of the insulating dielectric layer (5) comprises SiN, AlN, MgO, Ga2O3、AlHfOxAnd HfSiON, or a combination of several of them.
10. The N-substrate trench GaN IGBT as claimed in any of claims 1-9, wherein the transistor is formed based on GaN substrate material.
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