JP2005317828A - Method for manufacturing high voltage car-mounted semiconductor device for converting power and high voltage car-mounted semiconductor device for converting power - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an easily manufactured power semiconductor element having a low on-resistance and a high breakdown voltage. <P>SOLUTION: A method for manufacturing the power semiconductor element includes steps of: growing a highly-doped or an intermediately-doped n-type epitaxial layer on an n<SP>+</SP>-type Si substrate; forming a vertical columnar p-type region on both sides of the n-type epitaxial layer by forming a trench reaching the substrate or nearly reaching the substrate and by diffusing a p-type impurity from the trench; making a pnp structure along with itself; and filling the trench used for the diffusion with an insulator. An oxide film, a gate electrode, and a source electrode are applied over the pnp structure, and a drain electrode is applied to the bottom face of the Si substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power transistor used for driving an automobile or the like that operates with a high voltage and large current. The high voltage here is about 200V to 1000V and the power is about 30 kW to 100 kW, which is different from that for power generation such as power generation and transmission.

  In recent years, HEV (hybrid) vehicles have attracted attention as environmentally-friendly vehicles in the automobile industry. A motor is loaded in addition to the gasoline engine, and the engine and the motor are used complementarily. Since the motor runs on battery power, it has less environmental impact than a gasoline engine. It would be ideal to run with only a battery and a motor, but there is no cheap battery that can store enough power in a small volume, so an eclectic hybrid vehicle (HEV) consisting of a gasoline tank, engine, and battery / motor is expected. The In order to realize HEV, a battery having a small volume, a light weight and a large capacity is required. But there are other problems to solve.

  Using a DC motor that is easy to control as a motor is one option, but it has a large loss and a problem in terms of cost. Therefore, it will be used with an AC motor, but when an AC motor is used, the rotational speed is determined by the frequency, so an inverter is used for speed control. The speed of the AC motor is changed by converting the DC power of the battery to an appropriate frequency by an inverter and changing the frequency.

  The power converter at the final stage of the inverter is ideally provided with three sets of two complementary MOS transistors connected in series, and each is given a gate signal whose phase is shifted by 120 ° at the frequency f. It is good to make it. However, since there are still no transistors with low loss, such as p-type MOS and p-type FETs, in reality, an n-type MOS and n-type FET with low loss are used in series. Then, a three-phase alternating current can be created from the direct current power source. The number of rotations of the motor can be changed by changing the frequency with an inverter.

  As such, a combination of an IGBT (Insulated Gate Bipolar Transistor) and a reverse bias diode has been proposed as one candidate. FIG. 1 shows a set of three complementary MOS transistors using IGBTs. Such a power semiconductor chip is soldered onto an insulating substrate bonded on a heat sink (Cu, CuMo, etc.). This is not only proposed but also prototyped and put into practical use. The IGBT will be described later.

  Many proposals have been made, but some of them are aerospace theory that cannot be surely called conventional technology because there are doubts about the cost and the way of realization. But here are some new proposals for high-voltage, high-power devices.

In the past, power transistors were mainly used for audio, and silicon (Si) -bipolar transistors (Bipolar Transistors) were used. Decades ago, there were many excellent bipolar transistors with high reverse breakdown voltage (VB) and high speed. However, since the bipolar transistor has an npn structure and the collector-emitter voltage (V _CE ) remains even when it is on, the power loss is large when the current is large.

As a result, bipolar power devices have declined and are now almost replaced by Si-FETs (Field Effect Transistors). There are two types of FETs, a junction type (JFET type: Junction Field Effect Transistor) and a MOS type (Metal-Oxide Semiconductor). The improvement can be applied not only to Si but also to SiC. Further, both Si and SiC are provided with a structure applicable to the JFET type.

  The characteristics required for the power transistor are various such as on-time resistance, reverse withstand voltage, maximum current, calorific value, and on / off speed. The problem here is a semiconductor element for driving a motor of a hybrid vehicle. Since it is a power element that drives a vehicle-mounted motor, the voltage is about 200V to 1000V, which is not so high, but is much higher than transistors for communication, information processing, audio, and the like.

Since the motor of an automobile is driven, the on-state current is considerably large. Therefore, it is desired that the on-resistance is particularly low. In addition, a high drain-source maximum voltage (breakdown voltage, breakdown voltage V _B ) at the off time is also required. The on-resistance R _ON and the breakdown voltage V _B is in a relationship contradictory to each other. For the same structure and material, increasing the breakdown voltage decreases the on-resistance, and increasing the on-resistance decreases the breakdown voltage.

  Various ideas are made to overcome such an antagonistic relationship and enhance both. Many complicated structures that cannot be manufactured have been proposed. Due to the problem of manufacturing cost, it can be said that, in principle, both the breakdown voltage and the on-resistance can be increased.

The advantage of the wide band gap semiconductor is that the dielectric breakdown electric field E _B is an order of magnitude larger than that of Si. The fact that _EB is large means that when the breakdown voltage of the element is increased, the impurity concentration of the drift layer responsible for the breakdown voltage can be increased, and the distance can be shortened, so that the resistance can be decreased.
It is said that a semiconductor element made of SiC can be used at a high voltage and has low resistance when turned on. Since a large dielectric breakdown field E _B can increase the breakdown voltage. It is an ideal material for power transistors.

Proposals have been made that GaN transistors also have high electron mobility, so their on-resistance should be small. However, GaN transistors are actually in the research stage. Therefore, even though it can be said that a GaN transistor has a low _ON- state resistance RON and a high breakdown voltage, it is still a realization.

GaAs has a high electron mobility. GaAs transistors have been put into practical use and are feasible. However, even if the conflict between the on-resistance R _ON and the breakdown voltage V _B can be solved to some extent, it has to be low in cost to be used as a semiconductor device for automobiles and is not popularized.

At present, it is not practical unless it is a Si semiconductor. High-quality Si single crystal wafers are manufactured in large quantities and readily available, and peripheral technologies such as lithography, etching, resist, and oxidation are mature. Bipolar power transistors were often used in audio in the past. There is a drawback that V _CE does not become 0 even when it is on and the input resistance is low. Nowadays, almost no bipolar transistors are used in power devices.

  Power devices have been replaced by Si-MOSFETs. The elements such as the DRAM, SRAM, and CPU of the computer are also MOSFETs, but must be distinguished from power MOSFETs. The principle of operation is the same, but the voltage, current, speed, dimensions, etc. are very different. Signal processing products have features such as small current, low voltage, small size, high speed, and high density integration. A source electrode, a gate electrode, and a drain electrode are attached to the upper surface, and current flows laterally on the surface. Power products have features such as large current, high voltage, large size, low speed, low density / single element, and heat dissipation mechanism. The source electrode and the gate electrode are on the upper surface, but the drain electrode is on the lower side so that current flows in the vertical direction. That is, vertical elements are mainstream. In many cases, it is a single element with a cooling fin or the like.

In the MOSFET, the channel length L and the channel width W are important elements. The length L is the dimension of the portion sandwiched between the source and drain electrodes in the direction from the source electrode to the drain electrode (taken in the x direction) and includes the length of the gate electrode. The gate width W is a horizontal dimension perpendicular to the gate width W. In the case of an FET for processing a small amplitude and a small signal, since high-speed response is important, both L and W are required to be small. In the case of a power FET, since the current is large and the heat generation is remarkable, L × W must be increased. When L is increased, the speed is reduced, so W is increased. For Si _chip, the device channel width _{W Chip} to the N parallel, often the overall channel width _{W = W chip} × N.

  So in general, the width W is much larger than the length L.

  Si-MOSFET power devices have proven results and are easy to use, but there is a contradiction between on-time resistance and breakdown voltage. For automobile motors, higher withstand voltage and lower on-resistance are required than audio. When the breakdown voltage is increased, the on-resistance increases, and there is nothing that can be satisfied.

The n-channel Si-MOSFET power transistor has a structure as shown in FIG. An n-type Si epitaxial layer 2 is provided on an n ⁺ -type Si substrate 1, and p-type regions 3 are formed by diffusion on both sides of the n-type epi layer 2. An n-type region 4 is further formed in the p-type region 3 by diffusion. A gate electrode 6 is provided on the n-type region in the center via an insulating layer (SiO ₂ ) 5. Source electrodes 7 and 7 are provided on both sides across the p-type regions 3 and 3 and the n-type regions 4 and 4. An n electrode 8 is formed on the lower surface of the n ⁺ type Si substrate 1. When a voltage is applied to the gate, the portion in contact with the oxide film of the p-type well becomes the channel 10.

There can be two pn junctions. One is a pn junction 17 between the low concentration p-type region 3 and the high concentration n-type region 4, and the other is a pn junction 9 between the n-type epilayer 2 and the low concentration p-type region 3. Since the pn junction 17 is forward, there is no problem. The pn junction 9 between the n-type epi layer 2 and the p-type region 3 is important. FIG. 2 (2) shows the drain current _ID during on / off.

Here, the n ⁺ -type Si substrate 1 is drawn thin, but the substrate is actually the thickest. Substrate does not need to consider when considering with the on-resistance R _ON high n-type dopant is a high concentration is doped to the conductivity. So here it's drawn thinly. The on-resistance _RON is determined by the n-type epi layer 2 that follows the on-resistance RON. Since this is a low concentration dope, the on-resistance is increased. pn junction 9 gives the off state, n-type epitaxial layer 2 determines the on resistance _{R ON.} Therefore, what is important is the n-type epi layer 2 and the pn junction 9 which is the end thereof. Therefore, the n-type epi layer 2 is enlarged and illustrated.

It is assumed that the source electrode is grounded and a positive voltage _VDS is applied to the drain electrode. When the gate voltage V _G is not applied, no current flows because the pn junction 9 between the n-type epitaxial layer 2 and the p-type diffusion layer 3 is reverse biased. That is, the pn junction 9 between the p-type layer and the n-type epi layer is important. When a high voltage is applied to the pn junction 9, the depletion layer spreads over both the p-type region 3 and the n-type region 2. Maximum electric field at the pn junction. The maximum electric field exceeds the breakdown voltage E _br When element breakdown occurs. Therefore, it is necessary that the maximum electric field of the pn junction 9 is much smaller than the breakdown voltage _Ebr . Therefore, the depletion layer must be extended to both sides.

The thickness of the depletion layer is inversely proportional to the square root of the dopant concentration and proportional to the square root of the applied voltage. To widen the depletion layer, the dopant concentration must be lowered. So the acceptor concentration _{N A} of the upper p-type region 3 lower, n-type epitaxial layer 2 of the donor concentration _{N D} is low (e.g., ¹⁰ 14 order of ^{cm -3).} The reason why the p ⁻ and n ⁻ regions on both sides of the pn junction 9 are low in concentration is to widen the depletion layer and improve the withstand voltage.

Now the p-type layer 3 along the gate when a positive voltage V _G is applied to the gate electrode may inversion layer. The inversion layer is a thin electron layer induced in the p-type region by the gate voltage. Since the inversion layer is formed, the pn junction 9 loses deterrence, and electrons flow from the source (n-type region 4) to the inversion layer, the n-type epi layer 2, the n-type substrate 1, and the n-electrode 8. The drain current in the on state flows through the drift region (n-type epi layer 2). The resistance of the heavily doped substrate 1 is small, and the n-type regions 4 and 4 provided with the source electrode and the drain electrode are also highly doped so that the resistance is small. Therefore, it is almost this drift region (n-type epi layer 2) that determines the _ON resistance RON. As mentioned earlier, because the low individual donor concentration N _D of the on-resistance larger. Although the lower acceptor concentration N _A of the adjacent p-type region, here the time on low as because flowing electrons in the inversion layer is acceptor concentration N _A is less problem.

That is, the ON resistance _RON is increased by the low concentration doping of the n-type epi layer 2 (drift region). Increasing the donor concentration _{N D} of the n-type epitaxial layer 2 on-resistance _{R ON} is decreased. Although it is that so, raising the N _D of the n-type epitaxial layer 2 is the depletion layer decreases the thinning will withstand breakdown voltage V _B at the OFF time decreases. So no floor to not raise so much the donor concentration N _D of the n-type epitaxial layer. However, the _ON resistance RON does not decrease unless the donor concentration of the epi layer 2 is increased. As such, the breakdown voltage and the on-resistance of the FET are contradictory. Somehow this contradictory conflict must be resolved. Otherwise, a device with high breakdown voltage and low loss cannot be produced.

FIG. 3 shows a schematic structure of an IGBT (Insulated Gate Bipolar Transistor). A lightly doped n-type epi layer 2 is provided on a heavily doped n-type Si ⁺ substrate 1, and lightly doped p-type regions 3 (p ⁻ ) are formed on both sides of the n-type epi layer 2 by diffusion. A high-concentration n-type region 4 (n ⁺ ) is further provided inside the mold region 3. A gate electrode 6 is attached to the center via an insulating film 5. Source electrodes 7 and 7 are formed in the n-type regions 4 and 4 on both sides. When a voltage is applied to the gate, the portion in contact with the oxide film of the p-type well becomes the channel 10. The structure so far is the same as that of the vertical MOSFET shown in FIG. A little different from here. A heavily doped p ⁺ region 18 is provided on the back surface of the heavily doped Si substrate 1, and a drain electrode 8 is provided thereunder. In this way, the p ⁺ layer 18 is interposed between the drain electrode 8 and the n-type Si substrate. A new third pn junction 19 is generated between the p ⁺ layer 18 and the n-type substrate 1. Since the third pn junction 19 is forward-biased, no reverse bias is applied.

The newly added p layer 18 has many holes as majority carriers. When this is on, it becomes a carrier and plays an active role with electrons. Both electrons and holes flow. Therefore, the on-time current increases. At the time of ON, electrons entering from the source electrode flow in the n-type region 4, the inversion layer of the p-type region 3, the n-type epi layer 2, the n-type substrate 1, the p layer 18, and the drain electrode 8. On the other hand, holes present in a large amount in the p layer 18 flow to the n ⁺ -Si substrate 1 through the pn junction 19. Since the Si-n type substrate is highly doped, electrons exist as majority carriers. The inflowing holes recombine with the substrate and disappear. That is the current flow. The holes flow out from the p layer 18 and decrease, but the holes in the p layer 18 do not decrease because the holes are supplied from the drain electrode 8.

As described above, the current increases due to electrons flowing from the source electrode to the Si substrate and the flow of carriers in both directions flowing from the p layer 18 to the Si substrate. Compared with the MOSFET shown in FIG. 2, the IGBT is useful because it can increase the on-time current, although the number of steps of forming the p layer 18 by diffusion and epi-growth is increased on the back surface of the Si substrate.
In order to withstand the high voltage at the time of off, it is necessary to make the n-type epi layer 2 thicker than the MOSFET. Bipolar transistors are used because both electrons and holes are used as carriers, but current does not flow from the base to the emitter or current amplification. There is no concept of collector, emitter and base, but a combination of source, drain and gate. The gate is blocked from the p-type region by the insulating film 5. Therefore, it is called Insulated Gate, but it is natural to think of it as an FET. The IGBT is rather considered as a kind of MOSFET.

  As described above, the on-state current can be increased and the on-state resistance can be substantially reduced, but the IGBT has a problem in the operation at the time of turn-off as shown in FIG. Even if the gate voltage is lowered and the pn junction 9 of the gate is closed, a large number of electrons and holes (minority carriers) coexist in the wide n-type substrate 1, and currents continue to flow because they do not disappear immediately. In other words, the current pulls the tail. There is such a problem that there is such a tail current and the current is not immediately turned off even when the gate is turned off. IGBTs are not suitable when such operational delays are a problem.

  As a technique for solving the conflict between the on-resistance of the power FET and the breakdown voltage, a super junction (SJ) has been proposed.

USP 5,438,215 USP 5,216,275 Tatsuhiko Fujihira, “Theory of Semiconductor Superjunction Devices”, Jpn. J. et al. Appl. Phys. Vol. 36 (1997), pp 6254-6262, Part 1, no. 10, October 1997

Patent Document 1 proposes an FET in which an npnpnpnpn structure including four or more p layers in an n ⁻ layer is fabricated in the lateral direction. Such a structure is called a super junction.

However, there is no specific description on how to make such npnpnpnpn structures arranged in the horizontal direction, and it is not known. n ^- or intermediate to such n of layers, because to make a change to the layers of p to make the ion implantation? However, it is difficult to introduce the dopant so deeply in the ion implantation. I think that ion implantation would not be possible. In that case, it seems to be produced by diffusion, but it is difficult to produce a thin npnpnpnpn structure extending in the vertical direction by diffusion. That is, the super junction proposed by Patent Document 1 is theoretical, and its feasibility is poor from the viewpoint of manufacturing.

Patent Document 2 proposes a type of FET in which a CB layer (composite buffer layer) in which two layers (p ⁻ , n ⁻ ) of different conductivity types are combined like a honeycomb is inserted between a source electrode and a drain electrode. Yes. This also uses a super junction (SJ) structure in which different layers are arranged in the horizontal direction, such as npnpnpn. However, it is not clear why n-type layers and p-type layers are formed alternately. This is also not feasible from a manufacturing standpoint.

Non-Patent Document 1 theoretically analyzes a power device in which a large number of npnpnpnp structures are arranged in the horizontal direction and a source electrode and a drain electrode are attached on both sides thereof. The manufacturing method is not clear. The npnpnpnp structure extending horizontally on the p-type substrate by epitaxial growth, the epitaxial growth of which was next to the n ⁺ layer for the drain, saying things like that perform n ⁺ epitaxial growth for the source. However, the vertical device is more advantageous when handling high power. Many super junction FETs have been proposed. However, although the SJ structure is excellent in principle, it is difficult to produce an npnpnpnp multilayer structure in terms of manufacturing. Since there is a manufacturing limit instead of a physical limit, it is necessary to propose a device structure that realizes the SJ structure from the manufacturing aspect.

  A MOSFET named “CoolMOS” manufactured by Siemens Co., Ltd. has been realized as a device for reducing the on-state resistance and increasing the breakdown voltage without reducing the speed. It would have been named “col” because the on-resistance is low and the heat generated during on-time is small. This is also a kind of super junction (SJ). It has a 5-layer structure of npnpn in the horizontal direction. It was impossible to find a patent document that accurately corresponds to the CoolMOS. However, since the above-mentioned Patent Document 1 is from Siemens, there is a place similar to Patent Document 1.

The following is from Siemens Internet advertising. FIG. 4 (1) shows a cross section of a CoolMOS element, and FIG. 4 (2) shows a drain current at the time of ON / OFF change. FIG. 5 shows a cross section of the element at the time of OFF. In this process, the n-type epi layer 2 is formed on the n-type Si substrate 1, and two p layers 23 and 23 (p column layers) parallel to the n-type epi layer 2 are formed and the central portion is formed. It is divided into an n layer 22 and n layers 24 on both sides. The n-type epi layer 2 has a five-part structure such as n ⁻ (24) p ⁻ (23) n ⁻ (22) p ⁻ (23) n ⁻ (24) from left to right.

The newly added vertical p layers 23 and 23 are the features of CoolMOS. Epilayer is ^{n - p - n - p -} n - is 5 layer as. Electron conduction occurs only in the central n ^- layer 22.

Above the epi layer 22, p-type regions 3 and 3 are formed on both sides by diffusion, and n-layers 4 and 4 are formed in the p-type regions 3 and 3. Source electrodes 7 and 7 are provided on the n layer 4. A gate electrode 6 is formed in the central portion via an insulating layer 5. A wide drain electrode 8 is formed on the bottom surface of the Si substrate.

  Since two p layers (p column layers) 23 and 23 are added to the epi layer 2, four pn junctions can be newly formed. A pn junction between the central n layer 22 and the p column layer 23 and a pn junction between the p column layer 23 and the peripheral n layer 24.

An object is to provide a MOSFET having a low on-resistance and a high breakdown voltage. It is also an object to provide a junction type JFET. COOLMOS of the foregoing Siemens has lowered the on-resistance by increasing the doping concentration _{N D} of the n-layer by an epitaxial layer on npnpn structure. It is claimed that when the npnpn structure is reverse-biased by the applied voltage, the depletion layer expands, the electric field at the pn junction is lowered, and the on-resistance is lowered without lowering the breakdown voltage. However, the principle is not clear.

  As shown in FIGS. 4 and 5, the CoolMOS epilayer has the widest n layers 24, 24 on both sides. The central n layer 22 and p column layer 23 are the same and narrow. The p column layer has a height of about 30 μm to 60 μm. It is estimated that the width of the p column layer 23 is 10 μm to 30 μm, and the width of the central n layer 22 is also about 10 μm to 30 μm. How do you make such a deep p-column layer? That is the problem.

  Techniques for introducing impurities into the crystal include ion implantation, gas phase diffusion, solid diffusion, and epi growth.

  When an epi layer is formed and an ion beam is implanted and ion implantation is performed, a p layer can be formed only to a depth of about 1 μm at most by ion implantation. A p-column layer having a depth (height) of 30 μm to 60 μm cannot be formed.

  Even if the p-type region is formed by vapor phase diffusion, only one having a thickness of several μm at most can be formed by one diffusion.

  Epi-grown materials mixed with impurities can be made in any thickness as long as they have the same concentration in the horizontal direction and different concentrations in the vertical direction. However, since npnpn is arranged in the horizontal direction here, it cannot be formed by normal epi growth. It is impossible to epi-grow in the horizontal direction.

  Although details of the CoolMOS manufacturing method are not known, it will be as follows. The epi layer is grown in several steps. A resist mask is created each time the epi layer is grown, and a mask hole is formed at the place where the p column layer is to be formed by photolithography and etching. Phase diffusion. A p-layer is formed in part and is later thermally diffused. The mask is removed, an n-type epi layer is further grown, a mask is attached, a hole is formed in the p column layer portion by photolithography etching, and the p-type dopant is vapor-phase diffused. Will we repeat epi-growth and longitudinal diffusion of p-type dopant from the mask over and over again?

  Thermal diffusion is weak in direction and does not necessarily go downward. In addition, the diffusion distance is short and deep diffusion is not possible. So, narrow the mask, p-type doping from a narrow mask hole, shorten the diffusion depth once, thin the cycle of epi growth and p diffusion and repeat growth, photolithography, etching and diffusion over and over again. Various ideas are necessary.

  For example, it is conceivable to form a p-column having a height of about 45 μm by repeating epi-growth and thermal diffusion every 15 μm. Alternatively, an npnpn structure including two p-columns each having a height of about 50 μm may be formed by repeating epi-growth and thermal diffusion every 5 μm 10 times.

  Even in such a case, the p-type impurity diffuses to the surroundings each time it is heated, so that the p layer initially introduced will spread to the surroundings. Therefore, it is difficult to become a clean column as shown in FIG. It is very difficult to make a vertical p-column layer like that. Even with only 5 layers, it is difficult to actually make a super junction, and the manufacturing method of CoolMOS that has finally been realized is also complicated and not easy.

  The present invention proposes a technique for manufacturing a super junction structure in a feasible way. Non-Patent Document 1 aims to make the number of npnp... Np layers as large as 50 or 100, and based on this assumption, the maximum value of drain current, the value of on-resistance, etc. are estimated. However, it is still impossible to make such a multi-layer super junction structure. The only CoolMOS that can be realized has a five-layer structure.

  The present invention proposes a superjunction device manufacturing method and device structure that can be manufactured with some sacrifice in the number of layers.

  Thereby, a power semiconductor device having a low on-resistance and a high breakdown voltage can be produced.

In the present invention, an n-type epi layer is grown on an n ⁺ -substrate, deep holes (trench) are opened in the n-type epi layer, and both sides of the n-type layer are open spaces, and a diffusion source of gas, solid, liquid, etc. from the holes Is introduced into the crystal to convert the side of the crystal into p-type at once. That is, the vertical p layer is formed by thermal diffusion or ion implantation from the side. Thereby, a three-layer structure of pnp can be formed in the lateral direction. The hole for diffusion is filled with oxide or nitride. Thereafter, a p-type region, an n-type region, and an insulating film are formed above, a gate electrode and a source electrode are attached, and a drain electrode is attached to the n-type substrate at the bottom. By doing so, a vertical p-layer can be easily formed. It can be simply called the trench diffusion method. Since it is originally an n-type epi layer, a lateral pnp structure can be formed when p layers are formed on both sides thereof.

  It is much simpler than the manufacture of CoolMOS in which the above-described vertical diffusion must be repeated again and again. However, a npnpn horizontal five-layer change structure cannot be made as in CoolMOS. The present invention creates a lateral three-layer pnp structure. Even in the case of the horizontal three layers, the on-resistance can be lowered without lowering the breakdown voltage. More on that later.

What has been described above is an n-channel MOSFET in which an n-epi layer is grown on an n-Si substrate. However, the present invention can be made in the same way with the conductivity reversed. That p ⁺ -Si p on the substrate ^- - is grown epitaxial layer, p ^- - bored a trench in the epitaxial layer, the n vertical pillar-type layer by diffusing n-type impurity from the trench p ^- - both sides of the epitaxial layer Can be made. An n ^- well and a p ⁺ layer are formed thereon, and a gate oxide film, a gate electrode, and a source electrode are formed. Thus, the trench diffusion type p-channel MOSFET of the present invention can be obtained. The present invention can also be applied to JFETs.

When an n-channel trench diffusion MOSFET and a p-channel trench diffusion MOSFET are combined vertically, a CMOS (Complementary Metal Oxide Semiconductor) FET is formed. Such a pair of trench diffusion MOSFETs can be connected instead of the IGBT of FIG. 1 to constitute an inverter circuit to drive a motor of an automobile.

  Diffusion often used in normal semiconductor device manufacturing is always performed in the vertical direction. In the case of CoolMOS, a structure called npnpn is formed, so that a column structure is formed by repeating diffusion in the vertical direction over and over again.

Instead, the present invention drills an epi-layer trench to diffuse p-type impurities laterally from the trench. It can be said that the trench diffusion method. Unlike Patent Documents 1 and 2 and Non-Patent Document 1, which are difficult to manufacture, the present invention is a power device that can be manufactured.
The present invention is only an FET, and the source electrode is in ohmic contact with the p region, so that a forward current flows when a reverse voltage is applied. Therefore, there is no need for a diode for releasing the reverse current as in the IGBT (FIG. 1).

  In the present invention, an n-type epi layer is grown on a substrate, a hole (trench) is vertically formed in the n-type epi layer 22, and a p-type dopant is diffused laterally from the hole so as to extend vertically. And a pnp three-column structure (33; 22; 33) arranged in the lateral direction is manufactured.

  Since p-type impurities are diffused laterally from the trench, a vertical pn junction can be easily manufactured by one diffusion. Thereby, a pnp structure is formed. The holes used for diffusion are later filled with an insulator. A step for forming a buried layer made of an insulator is required, and if it is an inorganic insulator, it can be produced by sputtering, ion plating, CVD, or the like.

A pnp structure can be formed in the lateral direction, and this is reverse-biased when off, so that a depletion layer spreads from both sides. The electric field formed by the applied voltage in the vertical direction becomes small and ideally becomes zero. Therefore, the withstand voltage can be increased. It is possible to increase the dopant concentration N _D of the n-type epitaxial layer for this purpose. That can be to decrease the on-resistance R _ON without lowering the breakdown voltage V _B.

Consider the relationship of the distribution of the electric field E, voltage, space charge, etc. before and after the pn junction (for example, the pn junction 9 under the gate) with reference to FIG. The left is a p-type region and the right is an n-type region. The boundary line z = 0 is a pn junction, and depletion layers N _D and N _A are spread on both sides thereof. and there is a depletion layer thickness d _p to the p-side. The acceptor is a negative space charge. The space charge density because no holes in the depletion layer -q (q is an elementary charge) to the acceptor concentration N _A is multiplied by. Since z = −d _p and space charge is 0 (hole and acceptor concentration are equal), the electric field is 0.

When z is −d _p ˜0, an electric field E _z is generated, which is obtained by integrating −qN _A / ε. Integrate this with z on the p side,

p-side (z: _{negative) E z = -qN A (z} + d p) / ε (1)

However, at the pn junction, that is, z = 0, the electric field E _z is a negative maximum value.

_{E z = -E m = -qN A} d p / ε (2)

Take.
On the n side (z> 0), the donor N _D (positive) exists as a space charge, so

E _z = −qN _A d _p / ε + _q N _D z / ε (3)

It is. electric field _{E z} in the z = _{d n}

_{E z = -qN A d p /} ε + qN D d n / ε = 0 (4)

It becomes. So the thickness of the depletion layer _d p, _{d n} is

N _A d _p = N _D d _n
= ΕE _m / q (5)

Satisfies the balance law. position z = 0 of the pn junction is positioned to provide a maximum electric field _{E m.} This donor concentration N _D, the acceptor concentration N _A does not change even if any at. The pn junction always gives the maximum electric field. This is because the negative sign of space charge changes at the pn junction.

  From the formula (5), the thickness ratio is equal to the donor-acceptor concentration ratio. The ratio is determined by this, but what determines the sum of the thicknesses?

What determines the sum of the thicknesses is the reverse bias _Vr . Assuming that the voltage increase in the p-type region is φ _p , this is the result of integrating the electric field equation (1) with z (−d _p ˜0) and adding a negative sign.

^{_{φ p = qN A d p 2}} / 2ε (6)

If the voltage increase in the n-type region and phi _n, which are those of formula (3) of the electric field _{E z} and z in (0 to D _n) integration.

^{_{φ n = qN D d n 2}} / 2ε (7)

The sum is equal to the reverse bias V _r .

V _r = φ _p + φ _n
= QN _A d _p ² / 2ε + qN _D d _n ² / 2ε (8)

Using equations (2) and (5),

V _r = (d _p + d _n ) E _m / 2 (9)

It becomes. This is what multiplied by the maximum electric field _{E m} average of the depletion layer thickness _{(d n + d p) /} 2 is that it total reverse bias _{V r.} Alternatively, the sum of the depletion layer thickness _(d n + d _p) is obtained by dividing twice the reverse bias _{V r} at maximum electric field _{E m.}

_{d p + d n = 2V r} / E m (10)

Not only that, but from equations (5), (6), (7)

_{φ p / φ n = d p} / d n (11)

I understand that. What is it saying? Say, the total reverse bias voltage, the thickness d _p of the depletion layer of the p-type region and the n-type _region, is allocated in proportion to d _n (phi _p and phi _n), is that. The electric field takes the maximum value at the pn junction regardless of the concentration distribution, and it cannot be moved. However, the potential φ can be freely distributed depending on the thickness of the depletion layer. If the depletion layer is lengthened, the conductive region can absorb most reverse bias. That is the nature.

Maximum electric field E _m shall be no always less than the breakdown voltage E _br. The breakdown voltage is a value specific to the substance. If it is Si, it is determined to be a certain value.

E _m <E _br (12)

This limits the maximum electric field E _m. Since E _m is limited, it is necessary to increase the depletion layer from the equation (10) in order to increase the reverse bias V _r (drain-source voltage when OFF).

For example, if the depletion layer thickness is doubled, the reverse bias can be doubled. However in order to increase the depletion layer must be reduced donor concentration N _D, the acceptor concentration N _A from equation (5). If the maximum electric field is determined, in order to depletion of doubling, it must be reduced donor concentration N _D, the acceptor concentration N _A 1/2. In this way, the reverse bias _Vr can be increased by a factor of two. However, this will increase the on-resistance by a factor of two. ON-resistance is inversely proportional to the donor concentration N _D of the n-type epitaxial layer. On-resistance and breakdown voltage V _B is conflicting properties. This is a drawback of the conventional MOSFET.

  Expressing that relationship more simply (from (8), (5))

^{_{V r = qN A d p 2}} / 2ε + qN D d n 2 / 2ε
(13)
= ΕE _m ² / 2qN _A + εE _m ² / 2qN _D

It becomes. Maximum electric field _{E m} is that it is a fixed value, the maximum voltage _{V r is,} qN D, seen to be inversely proportional to qN _A. qN _D and qN _A give the conductivity and are the reciprocal of the resistance. Therefore, the ON resistance _RON and the maximum voltage (withstand voltage) _Vr are proportional. If the breakdown voltage is increased, the on-resistance increases. The breakdown voltage cannot be increased and the on-resistance cannot be decreased. Such relations can not escape as long as the form has been balanced before and after the one pn junction and _{(d p N A = d n} N D) acceptor concentration _{N A,} the donor concentration _{N D.}

The present invention is a structure of pnp (33,22,33) made in the lateral direction by increasing the donor concentration _{N D} of the n epitaxial region 22 to lower the on-resistance _{R ON,} moreover, as the breakdown voltage _{V B} is not reduced It is a thing.

  FIGS. 12 and 13 show the space charge structure of the electric field potential of the lateral pnp of the present invention, which has a pnp double pn junction (33, 22, 33) in the lateral direction. These are the structures in the x direction, and FIG. 11 shows the structure in the z direction. It must be distinguished.

The thickness of the p-type region is f, and the thickness of the n-type region is g. The p and n regions have an acceptor concentration N _A and a donor concentration N _D. Here, the n-type region means the n-type epi layer 22 and is the same as that in the above formulas (1) to (13), but the p-type region is different from the above formula. In the above equation, the p-type region means the p-type region 3 of the channel under the gate.

This time, the p-type region is the vertical p-column type layer 33. N _A and d _p are naturally different. Although N _D of the n-type region are common, different from the direction of enlargement of the depletion layer (x-direction) are different even n depletion d _n. Do not confuse. Therefore, the pn junction in question here is not the pn junction 9 of the channel as in the previous case, but the pn junction 42 that can be formed vertically. Electric field is _{E x} not be the _{E z.}

FIG. 12 shows a state where the reverse bias voltage is insufficient and is not saturated. Maximum electric field E _mx at the boundary (pn junction) 42 between the left p-type region and the n-type region

_{(X = -g / 2) E} x = -E mx = -qN A d p / ε = -qN D d n / ε (14)

I take the. Maximum electric field at the boundary between the right p-type region and the n-type region (pn junction 42)

_{(X = + g / 2)} E x = + E mx = qN A d p / ε = qN D d n / ε (15)

Take. Here because the maximum electric field E _mx is different from the maximum electric field E _m described earlier in the z direction. It must be distinguished.

In this case the depletion layer is incomplete, does not meet the overall n-type region 22, p-type region _{33 (2d n <g, d} p <g). It is the lateral reverse bias V _s that determines the size of the depletion layer. This reverse bias V _s is in the horizontal direction, and is distinguished from the above-described reverse bias V _{r in} the vertical direction (z direction).

^{_{V s = qN A d p 2}} / 2ε + qN D d n 2 / 2ε (16)

When the reverse bias V _s is increased, the depletion layers d _n and d _p are enlarged. n-type region eventually two depletion d _n, is d _n coalesce approaching from both sides. When d _n = g, the depletion layer coalesces in the n-type region. Because it is the time _{d p = gN D / N A} , the minimum voltage _{V ss} of n-type region becomes a depletion layer all the

^{_{V ss = qN D g 2 (}} 1 + N D / N A) / 2ε (17)

Given by. When the reverse bias V _s is larger than V _ss (V _s > V _ss ), the intermediate n-type epi layer 22 becomes a fully depleted layer as shown in FIG. It becomes a fully depleted layer not by the action of the vertical electric field but by the action of the horizontal electric field. Even if the n-type epi layer 22 becomes a depletion layer due to the action in either direction, free charge does not exist there. The lack of free charge means that it becomes an insulator. That is important.

What gives the lateral reverse bias V _s ? That is, since the source electrode 7 and the p-type region 3 and the p-type region 33 are at the same potential when turned off, and the drain electrode 8 and the n-type epi layer 22 are at the same potential, the drain-source voltage itself is applied to the pn junction 42. It takes. That is, the drain-source voltage V _DS is applied to the pn junction 42 and is used to deplete the n-type epi layer 22. Therefore, the reverse bias V _r and V _s applied to the pn junction 9 of the channel 10 are both the drain-source voltage V _DS .

  What is good when the n-type epi layer 22 is depleted?

  It is Gauss's theorem in the n-type epilayer

∂E _x / ∂x + ∂E _z / ∂z = qN _D / ε (18)

Is two-dimensionally satisfied. In short, that is what it is. Previously described (3) said it _{E z = -qN A d p /} ε + qN D z / ε in formula.
Since it is E _x = 0 in the pn junction 9 described above (conventional example), the previous term ∂E _x / の_{x in the} equation (18) does not exist and ∂E _z / ∂z = qN _D / ε must be satisfied. I couldn't. So the above-mentioned case, _{E z} had to assume all of the _{N D} so that _qN D z / _ε. This forced an abrupt increase in the electric field E _z , which lowered the breakdown voltage V _B.
It was necessary to lower the N _D in order to increase the breakdown voltage V _B. It is the only had lowered _{N D} to avoid enlargement of the _E x = 0 So _{∂E z / ∂z = qN D /} ε is holds _{E z.}

However, when forming the pnp (33,22,33) Structure lateral direction (x direction) as in the present invention, (18) is holds, the ∂E _x / ∂x in the qN _D of the right side left side first term Convenient relationship of absorption.
∂E x _/ ∂x in the most right side of the N _D left first term us to absorb. Then, the second term ∂E _z / ∂z on the left side can be a very small value.
If the reverse bias in the lateral direction is sufficiently large, ∂E _x / ∂x = qN _D / ε holds, and the increase in the electric field in the z direction is zero.

  This is exactly what the lateral pnp structure of the present invention is. Equation (18) can be separated as follows.

∂E _x / ∂x = qN _D / ε (19)
∂E _z / ∂z = 0 (20)

And Equation (20) is important. Sonaruto increment becomes zero electric field at the n-type epitaxial layer of the E _z takes a large constant value of absolute values. The increase in potential is simply φ _n = E _m z in the _n -type epi layer. Since the value of the electric field is large, many voltages can be absorbed. This greatly increases the withstand voltage when off.

Here, we return to the problem of the vertical electric field E _z that can be formed in the pn junction 9 of the channel. FIG. 14 vertically shows changes in z-direction space charges N _A , N _D , electric field E, potentials φ _p , φ _{n and the} like inside the p-well 3 and the n-type epi layer 22. Although it corresponds to the conventional example of FIG. 11, it is drawn vertically to show that it is in the vertical direction. As a result, the characteristics of the electric field and potential change in the n-type epilayer of the present invention are well understood.

p-well is z = -d p _~0 a is because they become depletion acceptor concentration N _A in the same space charge (Taresotsu) has occurred. It is the same as FIG. However, a long depletion layer equal to the height H is formed in the n-type epi22, and a space charge N _D (tunnela) equal to the donor concentration is formed. Nevertheless, the electric field does not change. I will explain in order.

When z is −d _p ˜0 (p-type well 3), an electric field E _z is generated due to space charge −qN _A (talents). It becomes -qn _A is obtained by integrating the _{E z = -qN A (z +} d p) / ε of (Ok) is the same as equation (1).

pn junction 9: take in (z = 0 h), the maximum negative value field _{E z} is _{E z = -E m = -qN A} d p / ε (Equation 2). This also does not change.

However, the behavior in the n-type epi layer 22 is different. In the n-type epi layer 22, the electric field E _z is constant and zero.

E _z = −E _m (21)

It is. In spite of the presence of space charge N _D , N _D is not integrated to reduce the absolute value of the electric field. Space charge N _D does not come into the integration of the z direction because disappear effective in the integration of the x-direction. In n-type epi22, the potential increase φ (z) of (z = 0 to H) is

φ (z) = E _m z (22)

It is. In that way the electric field is a constant value (Kuyamake) -E _m, moreover the absolute value _{E m.} Not only is the electric field large, but the length here is H, which is long. Therefore, the increase of φ becomes large (Asaki Yume). φ is the withstand voltage when off. That is, the breakdown voltage is large. The potential increase at z = H (end of n-type epilayer; me) is

φ _n = E _m H (23)

It is. Since the relationship so far does not change on the p-type well side of the pn junction 9,

^{_{φ p = qN A d p 2}} / 2ε, E m = qN A d p / ε (24)

(Φ _p = Tetsu: E = Ok).
It is much larger of φ than the _p φ _n. The total of the off-state voltage V _r is

V _r = φ _p + φ _{n
^{= QN A d p 2 / 2ε}} + E m H
= E _m {(d _p / 2) + H} (25)

It becomes. (25) What does the expression say?
That the reverse bias voltage V _r applied to the pn junction 9 is {(d _p + d _n ) / 2} times the constant E _m has increased to {(d _p / 2) + H}. It is. Moreover, E _m is determined by the properties (N _A , d _p ) of the p-type well 3 on the left side of the pn junction 9 and is not dependent on the properties (N _D , H) of the n-type epi layer on the right side. It can be determined freely donor concentration N _D of the n-type epitaxial layer that is that. That is, it was released from equation (5).

Since d _p is the width of the p-type well 3, that is, the channel width, it is as short as about 1 μm to 2 μm. Since the relative dielectric constant of Si is 8, and the dielectric constant of Si is 8 × 8.85 × 10 ⁻¹⁴ F / cm (8 × 8.85 × 10 ⁻¹² F / m), from the right equation of Equation (24) _{E m = qN D d n /} ε becomes, for example, is calculated as _{E m = 0.3MV / cm, d} n be an n-type epitaxial layer is ¹⁰ 15 ^{cm -3} as low doped in 10μm~20μm It must be. Reduced to 20nm~30nm when let alone increasing donor concentration _{N D} of the n-type epitaxial layer to ¹⁰ 18 ^{cm -3.} Since it has a pnp structure and a reverse bias V _s is applied to the pn junction 42, the drain-source voltage V _r can be increased to {(d _p / 2) + H} times E _m which is a constant. Since the height H of the drift layer is several tens of μm,

_{(D p / 2 + H)} / (d p / 2 + d n / 2) = 20~40 (26)

It will be about. If the maximum electric field E _m is limited by being smaller than the breakdown electric field E _br , and E _m is a constant, it means that V _r can be increased 20 to 40 times that of the conventional MOSFET. V _r is not still the sum of the voltage phi _n applied to the voltage phi _p and n-type epitaxial layer 22 applied to the p-type well, the case of the present invention, most of the V _r phi _n is overwhelmingly large Is applied to the n-type epi layer. This allows for an increase in V _r while keeping E _m constant. That the present invention may be greatly increased the breakdown voltage V _B.

The on-resistance _RON is mostly the resistance of the drift region (n-type epi layer 22).

_{R ON = H / qμN D Wg} (27)

Given by. W is the channel width and the total width of the n-type epi layer, g is the thickness of the n-type epi layer, and H is the height of the n-type epi layer. Although the expression on-resistance / area is also used, the area of the drift region is Wg.

On resistance and area = H / qμN _D (28)

It is. Since conventional MOSFET had constraints of formula (5), the donor concentration _{N D} of the n-type epitaxial layer had to gulp low concentration of about ¹⁰ 13 ^~10 14 ^{cm -3.}
But _{E z} regardless of the _{N D} n-type epitaxial layer in the case of the present invention takes a constant value _-E m (determined by the p-type well), the _{N D} for example be in ¹⁰ 15 ^~10 17 ^{cm -3} it can.
Since the on-resistance is inversely proportional to N _D, it is possible to reduce the on-resistance if so.
As such the present invention can be achieved reduction in on-resistance, a second object of the of increased breakdown voltage V _B.

In the present invention, a vertical hole is dug in an n-type epitaxial layer grown on an n ⁺ -substrate, a p-type doping is performed therefrom to form a vertical p-column layer, and a hole for diffusion is filled with an insulator. This is a MOSFET having a lateral pnp structure that allows the n-type epi layer to be a fully depleted layer when turned off by reverse bias.
The n-type epi layer no longer needs to be low in concentration.
Although the conditions to become a complete depletion layer in reverse bias, not the conditions for restraining the donor concentration N _D of the n-type epitaxial layer otherwise.

concentration _{N D} of the n-type epitaxial layer is a freely can take a middle density ^{(10 14 ~10 15 cm -3)} , a high concentration ^{(10 15 ~10} 16 ^{cm -3)} or more high density .
The vertical p-column type layer should also have a medium concentration (10 ¹⁴ to 10 ¹⁵ cm ^-3 ) and a high concentration (10 ¹⁵ to 10 ¹⁶ cm ^-3 ) instead of a low concentration (10 ¹⁴ cm ^-3 or less). Can do. Therefore, from now on, it will be written as n, p, not n ⁻ or p ⁻ .

  Some vertical p-pillar layers extend to the Si substrate and some do not extend to the Si substrate. Further, the conductivity is reversed, and a vertical hole (trench) is dug in the p-type epitaxial layer grown on the p-substrate, and n-type doping is performed therefrom to form a vertical n-column layer. Good. Both polar FETs can be connected in series to form a CMOS structure.

  Here, two examples in which the vertical p-columnar layer is in contact with the substrate and one example in which the vertical p-column type layer does not reach the substrate will be described.

[First embodiment (vertical p-column type layer substrate contact: horizontal channel: FIG. 6)]
FIG. 6 shows a first embodiment of the present invention in which the vertical p-columnar layer reaches the substrate. A number of equivalent devices are fabricated on a Si wafer, which represents a portion of the device repetition. Many of the same are produced on the left and right. Elements for one chip are used in parallel with electrodes connected in common. Here, one unit is described. On the n ⁺ -Si substrate 1 doped with an n-type impurity at a high concentration, a vertical, medium-concentration, high-concentration n-type epi layer 22 is provided at the center of the element unit. On both sides of the n-type epi layer 22, medium-concentrated doped vertical p-columnar layers 33, 33 are formed by lateral diffusion. A pn junction 42 is formed between the vertical p-column type layer 33 and the n-type epi layer 22.

There is a wide gap between adjacent p-type layers 33 and 33 between adjacent elements, and insulators 35 and 36 are embedded in the gap. The insulator is SiO ₂ , SiN, an organic insulator, or the like. Actually, a hole is formed in the n-type epi layer, lateral diffusion is performed therefrom, a vertical p-column type layer is formed by horizontal diffusion, and then an insulator is embedded. The manufacturing process will be described later.

Since there are vertical p-columnar layers 33, 33 on both sides of the n-type epi layer 22, the structure is pnp in the horizontal direction. The n-type epi layer 22 becomes a drift region.
Above the n-type epi layer 22 and the vertical p-columnar layers 33 and 33, there are low-concentration p ⁻ -type regions (p-wells) 3 and 3, high-concentration n ⁺ -type regions 4 and 4, and high-concentration p ⁺ -type regions 56. It is manufactured in a symmetrical position by diffusion. An insulating film 5 (gate oxide film) is formed so as to cover both p ⁻ -type regions 3 and 3, and a gate electrode 6 is provided thereon. Source electrode 7 is formed so as to straddle p ⁺ type region 56 and n ⁺ type region 4. The pn junction 9 between the p-type well 3 and the n-type epi layer 22 is reverse-biased when off. The channel is a short horizontal space between the gate insulating film 5 and the p-type well 3. A wide drain electrode 8 is provided on the back surface of the n ⁺ -Si substrate 1.

  Since many elements are connected in parallel in the chip, the source electrode 7, the drain electrode 8, and the gate electrode 6 are all common. In this figure, the gate electrode 6 appears to be separated, but it is common between elements in the direction perpendicular to the paper surface, and is structured to be gathered at the end face.

In this example, the source electrode 7 is Al and protrudes from the upper surface, but an insulator 39 exists between the source electrode 7 and the gate electrode. The side insulators 38 and 39 are the same material (SiO ₂ , SiN, organic insulator) made in the same process. Since the hole for the source electrode 7 was drilled, the same insulator was separated. This also shows some of the adjacent elements. Since many equivalent elements are used in parallel, many of the same units are included in one chip.

When viewed as a unit of FET, it has a pnp structure in the lateral direction at the center. The n-type epi layer 22 is in contact with the p-type well 3 through the pn junction 9 at the upper side and is in contact with the Si substrate 1 through the junction 41 at the lower side. The vertical p column type layer 33 is in contact with the p ⁻ type well 3 (p type region) in the upper part and in contact with the n ⁺ -Si substrate 1 through the pn junction 40 in the lower part. A pn junction 42 is formed between the vertical p-column type layer 33 and the n-type epi layer 33.

  When off, the pn junction 9 is reverse-biased. In addition, at the time of OFF, the pn junction 42 is reverse-biased, and the depletion layer extends in the lateral direction in both the n-type epi layer 22 and the vertical p-columnar layer 33. A long depletion layer is formed in the n-type epi layer 22. A depletion layer extends from the side to fill the n-type epi layer 22.

  That is, electrons are excluded from the n-type epilayer as free carriers. This is possible even if the n-type epi layer 22 is doped at a considerably high concentration. That is, the n-type epi layer 22 can be doped at a considerably high concentration.

This has the effect of reducing the _ON resistance _RON . In addition, since the depletion layer is extended by the reverse bias in the lateral direction at the time of OFF, the n-type epi layer 22 is filled with the depletion layer, and the electric field E generated at the pn junction 9 between the p-type well 3 and the n-type epi layer 22 is reduced. Therefore, the breakdown voltage V _B also remains large. It is possible to reduce the on-resistance R _ON while keeping a large breakdown voltage V _B in this way.

[Second Embodiment (Vertical p-columnar layer reaches the substrate: vertical channel: FIG. 7)]
FIG. 7 shows a second embodiment of the present invention of a vertical channel. This shows about 1.5 units of the element, but the same repetitions are actually continuous from side to side. On the heavily doped n ⁺ -Si substrate 1, a vertical, middle and lightly doped n-type epi layer 22 is provided at the center. On both sides, there are medium heavily doped vertical p-pillar layers 33, 33 made by lateral diffusion. A pn junction 42 extending in the vertical direction is formed between the vertical p-column type layer 33 and the n-type epi layer 22. A pn junction 40 is also formed between the vertical p-columnar layer 33 and the n ⁺ -Si substrate 1. junction 41 between the n-type epitaxial layer 22 and the n-Si substrate 1 becomes discontinuous surface of the donor concentration _{N D} instead of pn junction.

Between adjacent elements, there is a wide gap between the vertical p-columnar layers 33, 33, and insulators 37, 37 are embedded in the gap. The insulator is SiO ₂ , SiN, an organic insulator, or the like. Actually, the vertical p-column type layer 33 is formed by cutting a part of the n-type epi layer to make a hole and thermally diffusing the p-type dopant from the hole. The insulator 37 filled the hole.

On both sides of the n-type epi layer 22, there are vertical p-columnar layers 33, 33, which have a pnp structure in the horizontal direction. The n-type epi layer 22 becomes a drift region. Above the n-type epi layer 22 and the vertical p-columnar layers 33 and 33, low-concentration p ⁻ -type regions (p ⁻ ; p-wells) 3 and 3, high-concentration n ⁺ -type regions 4 and 4, and high-concentration p ⁺ -type Region 56 is fabricated in the vertical position. A hole is dug in the center of n ⁺ type region 4 and p ⁻ type region 3 to form oxide film 5 by thermal oxidation, and gate (G) electrode 6 is buried.

  The p-type region 3 extends laterally and forms a pn junction 9 extending laterally between the lower n-type epi layer 22. This is a pn junction that supports the voltage when turned off. A channel 10 is formed between the gate insulating film 5 and the p-type well 3.

An insulating layer 39 is provided on the gate electrode 6, and an aluminum (Al) source (S) electrode 7 is formed thereon. Source electrode 7 is in contact with n ⁺ region 4 and p ⁺ type region 56. A drain (D) electrode 8 is formed on the back surface of the n ⁺ -Si substrate 1.

  This is because the gate electrode G is vertical, and the contact portion between the gate electrode G and the p-type region 3 is also vertical. That is, the channel 10 exists in the vertical direction.

  Since many equivalent elements are used in parallel, many of the same units are included in one chip. When viewed as a unit of FET, it has a pnp structure in the lateral direction at the center. In that respect, it is the same as the previous example. The outside of the vertical p-column type layer 33 is an insulator 37, and its boundary 44 is not a pn junction. No voltage or current flows through the boundary 44.

  When off, the pn junction 42 is reverse-biased, and the depletion layer extends laterally on both sides of the vertical p-columnar layer 33 and the n-type epilayer 22. A long depletion layer is formed in the n-type epi layer 22. A depletion layer extends from the side to fill the n-type epi layer 22. That is, electrons are excluded from the n-type epilayer as free carriers. This is possible even if the n-type epi layer 22 is doped at a considerably high concentration.

That is, the n-type epi layer 22 can be doped at a considerably high concentration. This has the effect of reducing the _ON resistance _RON .
In addition, since the depletion layer is extended by the reverse bias in the lateral direction at the time of OFF, the n-type epi layer 22 is filled with the depletion layer, and the electric field E that can be formed in the n-type epi layer 22 becomes constant. This can absorb most of the reverse bias V _r . Therefore, the breakdown voltage V _B also remains large. Moreover, since a large number of equivalent elements are used in parallel, a large current can be obtained at the time of ON.

[Third embodiment (vertical p-columnar layer ends halfway: horizontal channel: FIG. 8)]
A third embodiment of the present invention in which the vertical p-columnar layer does not reach the substrate will be described with reference to FIG. This also shows 1.5 elements. The same structure is repeated from front to back and from side to side.

In the upper central portion of the element unit of the heavily doped n ⁺ -type Si substrate 1, a vertical middle and heavily doped n-type epi layer 22 is provided. On the both sides, medium-concentration vertical p-column regions 32 and 32 are formed by diffusion. A pn junction 42 extending vertically is formed between the n-type epi layer 22 and the vertical p-columnar layer 32. Adjacent vertical p columnar layers 32, 32 are bent laterally at the lower end and connected to each other. This is because the n-type epi layer 22 was formed and then both sides were etched away to form holes, but this was because a part of the n-type portion was left in the middle of the adjacent element. The remaining n-type epi layer 22 and the interface 43 in the vertical direction of the p layer 32 also form a pn junction.

The other points are the same as those in FIG. A p ⁻ layer (p well) 3, an n ⁺ type region 4 and a p ⁺ type region 56 are provided on the n type epi layer 22 and the vertical p column type layer 32. A source (S) electrode 7 is formed on the p layer 3, the n layer 4 and the p ⁺ layer 56. An insulating film 5 and a gate (G) electrode 6 are provided on the p layer (p well) 3. This is similar to that of FIG. This is the portion where the gate oxide film 6 and the p-type well 3 are in contact.

Although the drift region is the n-type epi layer 22, the pn junction 42 is reverse-biased when off because the vertical p-columnar layer is adjacent. The n-type epitaxial layer for the reverse bias becomes a depletion layer, wherein the electric field Ez takes a constant value, it can be increased V _r, the breakdown voltage V _B is enhanced.

  Although the vertical power device of the present invention is also characterized by its structure, the manufacturing method is rather remarkable. 6 will be described in order with reference to FIGS. These figures are sectional views of about 1.5 units of the element. Only then can you see the repetition. Actually, many identical element units are manufactured on the entire Si wafer. Therefore, many of these are arranged side by side on the Si wafer. A set of a plurality of units becomes one chip, and a plurality of chips are manufactured on one Si wafer.

FIG. 9 (1): Generation of n-type epi layer An n ⁺ -Si substrate 1 doped with n-type impurities at a high concentration is prepared. A heavily doped n-type epi layer 2 is epitaxially grown on the n ⁺ -Si substrate 1. The thickness of the n-type epi layer 2 is about 40 μm to 60 μm and is quite thick. In order to sufficiently increase the breakdown voltage at the time of off, such a thickness is necessary. However, this is not as low as n = 10 ¹⁴ cm ⁻³ as in the conventional MOSFET of FIG. 2, but can be increased to about 10 ¹⁵ to 10 ¹⁷ cm ⁻³ .

FIG. 9B: Oxide film generation and oxide film hole formation A part of the upper portion of the n-epi layer 2 is oxidized to form an oxide film (SiO ₂ ) 29. A hole is formed in a part of the oxide film 29 by photolithography and etching. The position where the hole is made is the position where the trench for diffusion should be made.

FIG. 9C: Trench formation The n-type epi layer 2 is etched in the vertical direction using the oxide film as a mask. A deep hole (trench) 27 having a high aspect ratio is formed by RIE. This is a feature of the present invention. This trench becomes a hole for diffusion. The trench 27 may reach the n ⁺ -substrate 1 (first and second embodiments), and may not reach the n ⁺ -substrate 1 (third embodiment).

  By the trench 27, the n-epi layer 2 becomes an isolated hill (protrusion), and the side surface is exposed. P-type impurities are diffused from the side. The diffusion may be either gas phase diffusion (using diborane gas) or solid diffusion (boron-doped SOG), but here an example of solid diffusion is shown.

FIG. 9 (4): Filling trench with solid diffusion layer Solid diffusion layer 30 containing boron is applied to the entire wafer, and trench 27 is filled with solid diffusion layer 30. For example, a B-doped SOG solution is spin coated on the entire wafer.

FIG. 9 (5): Lateral diffusion of p-type impurities The Si wafer is heated to an appropriate temperature. When heated, the diffusion coefficient increases. A p-type impurity is laterally diffused from the solid diffusion layer 30 to the n-type epi layer 2 to generate a vertical p-columnar layer 33. Thus, the most characteristic feature of the present invention is that a vertical p-columnar layer is formed at once from a deep trench by lateral diffusion. As a result, a lateral pnp structure including the central n-epi layer 22 and the vertical p-columnar layers 33 on both sides is formed. If n layers can be generated outside the p layers on both sides, a more complete SJ structure can be obtained, but this cannot be done. The trench portions on both sides can no longer be made of Si crystal and are filled with an insulator.

FIG. 9 (6): Solid diffusion layer removal, oxide film removal, insulation coating Once the vertical p-columnar layer is formed, the solid diffusion layer is no longer necessary. The solid diffusion layer 30 is removed and the oxide film 29 is removed. The trench 27 and the raised portion (pnp) are exposed. The surface is wet-oxidized, and the raised portion and the trench side surface are covered with an oxide film (insulator 35). The trench 27 still remains between the oxide films 35 and 35. In thermal oxidation or wet oxidation, the trench is not filled because only a part of Si becomes SiO ₂ .

FIG. 9 (7): Filling the trench Then, an insulator 36 is introduced into the trench to fill it. For example, the trench 28 is filled with TEOS. Since the trench is buried, the surface becomes flat. The vertical p-columnar layer of the adjacent element is triple-insulated by the insulators 33 and 36. As such, the insulator has a double structure. The same applies to the second and third embodiments, but in FIGS. 7 and 8, the double structure of the insulator is simply expressed for the sake of simplicity.

  However, it is not always necessary to strictly insulate between adjacent vertical p-column type layers. Since equivalent element units are used in parallel, the vertical p-columnar layers of adjacent elements have the same potential. In the third embodiment, adjacent vertical p-columnar layers are connected near the bottom.

Fig. 9 (8): Removal of the upper insulator and residual oxide film on the gate. Resist is applied on the entire surface and exposed using a mask that exposes only the portion that will become the source electrode, and the resist on the gate and the insulator is removed. The remaining resist to be the source electrode is removed. The insulator is etched away by RIE (Reactive Ion Etching). The oxide film 50 in the portion that becomes the gate remains, and the pnp upper surface 52 in the portion that becomes the source is exposed.

FIG. 9 (9): Generation of p-type well 3 A p-type impurity (boron) is introduced into the pnp upper surface 52 by ion implantation or diffusion. This creates a low concentration p-type region 3 (p-well). Since the oxide film 50 is present on the gate, the p-type region (p well) 3 is not formed in the gate portion. The n-type epi region 22 remains just under the gate. This created the part that should become the channel. It is still necessary to create an n ⁺ − region for ohmic contact with the source electrode.

FIG. 9 (10): Generation of gate oxide film The oxide mask 50 in the gate portion for generating the p-well is removed, and the upper ends of the p-well 3 and the n-type epi layer 22 are made flat. Further, the surface is thermally oxidized to form an oxide film 5. Because of thermal oxidation, an oxide film is formed on the entire p well 3 and n-epi layer 22 where the Si crystal is exposed.

FIG. 9 (11): Generation of polysilicon gate film A polysilicon film is attached to the whole. Resist is applied, baked, exposed and developed using a mask. Resist remains only in the gate portion. The polysilicon is etched away by RIE. Polysilicon remains only at the gate portion. The resist is removed (ashing) to form a polysilicon gate electrode 6.

FIG. 9 (12): Formation of n ⁺ -region 4 Using the polysilicon gate electrode 6 as a mask, ions of n-type impurities (boron and arsenic) are implanted to form n ⁺ -regions 4 on the left and right sides of the gate electrode 6. The ion beam penetrates the oxide film 5 and enters the p-type regions 3 and 3 to form a shallow n ⁺ -region 4. Such a method is known as self-alignment. The n-type region 4 is a portion where the source electrode is to be ohmic-joined. However, the source electrode must be connected not only to the n ⁺ -region but also to the p-type region. Therefore, it is necessary to make a p-type region right next to the n ⁺ -region.

FIG. 10 (1): Application of resist A resist 54 is applied to the entire surface. This covers the oxide film 5, the gate electrode 6, and the upper surfaces of the insulating portions 35 and 36.

FIG. 10 (2): Generation of photolithography gate film, generation of p ⁺ -region A resist film 55 covering the top and the periphery of the gate electrode is formed by aligning the mask and exposing and developing. In this state, p-type impurities are ion-implanted to form a p ⁺ -type region 56 in a part of the n ⁺ -region 4 not covered with the mask.

FIG. 10 (3): Removal of resist film, oxide film etching The resist film covering the gate is removed (ashing). The gate electrode 6 is exposed. Using this polysilicon gate as a mask, the oxide film 5 is etched. The portion of the oxide film covering n ⁺ -region 4 and p ⁺ -region 56 is removed. Only the oxide film 5 immediately below the gate 6 remains.

FIG. 10 (4): Interlayer film coating The gate electrode and the source electrode must be insulated. Therefore, an interlayer film 59 is attached to the whole by CVD. The whole of the gate electrode 6 and the insulators 35 and 36 is covered. This is SiO ₂ , SiN or the like.

FIG. 10 (5): Partial removal of interlayer film A resist is coated on the interlayer film, exposed to a mask, and developed. Only the resist on the gate electrode and the insulating portion remains. The interlayer film is etched by RIE using the resist as a mask. This exposes only the tops of the n- and p-type regions. There is a recess 62. The interlayer film on the gate electrode and the insulator remains.

FIG. 10 (6): Generation of source electrode Aluminum is sputtered on the entire surface. Aluminum also wraps around the recess 62. Aluminum is also deposited on the gate and on the interlayer film on the insulating portion. A portion that enters the recess 62 and is joined to the n-type region 4 and the p-type region 56 becomes the source electrode 7. An aluminum electrode is attached to the back surface of the n ⁺ -Si substrate by sputtering. This is the drain electrode 8 (D).

  A number of similar element units are arranged side by side, but the drain electrode and the source electrode are common, and these elements are used in parallel connection. Similarly, the gate electrodes are connected together.

[Specific numerical example (design withstand voltage 800V)]
For example, the device of the present invention can be manufactured by the following numerical examples. This will be described with reference to FIG.
Let's calculate on-resistance, on-resistance / area, channel resistance, depletion layer thickness, etc. at such values.

A. Horizontal thickness of vertical p-columnar layer (33) f = 1 μm
A. Impurity concentration of vertical p columnar layer (33) N _A = 1 × 10 ¹⁶ cm ⁻³
C. Lateral thickness of n-type epi layer (22) g = 2 μm
D. Impurity concentration of n-type epilayer (22) N _D = 1 × 10 ¹⁶ cm ⁻³
E. Drift layer length (height of 22) H = 30 μm = 3 × 10 ⁻³ cm
F. Electron mobility μ _e = 300 cm ² / Vs
G. Insulation layer lateral thickness d ₃ = 4 μm
H. Horizontal thickness of element unit d _c = g + 2f + d ₃ = 8 μm = 8 × 10 ⁻⁴ cm
I. Chip size 11mm x 7mm
E. Channel width W = (chip length / d _c ) × chip width
= (7mm / 8μm) x 11mm
= 9625mm = 962.5cm (29)

The total cross-sectional area of the drift layer (n-type epi layer 22) is W × g, and the length (height in the vertical direction) is H (30 μm).

Drift layer total cross-sectional area S = 9625 mm × 2 μm = 0.925 cm ² (30)
Total resistance of the drift layer _{= H / qN D Sμ = 0.0324Ω} = 32mΩ (31)
Resistance / area = 32 mΩ × 0.1925 cm ² = 6 mΩcm ²
(32)
It is.

The published value of resistance and area of CoolMOS is about 50 mΩcm ² . The device of the present invention can reduce the on-resistance and area to about 1/10 of the device. It can be seen that the object of the present invention of reducing on-resistance is achieved.

Next, let's calculate the channel resistance.
Sa. Gate oxide thickness T = 0.1 μm = 0.1 × 10 ⁻⁶ m
Ii. Channel length L = 1μm = 10 ⁻⁴ cm
And Since the total channel width is W = 9625 mm and the length is L = 1 μm according to the above calculation, the channel area is S _c = WL = 0.09625 cm ² = 9.625 × 10 ⁻⁶ m ² (33)
It is.

  If the dielectric constant of the insulating film is 4, the capacitance C is

C = 4 × 8.85 × 10 ⁻¹² F / m × 9.625 × 10 ⁻⁶ m ² /0.1×10 ⁻⁶ m
= 3400pF (34)

It is. When the gate voltage is V _g and the threshold voltage is V _t , the effective voltage applied to the gate is V _g −V _t . When V _t = 4V and V _g = 10V, a voltage of 6V is applied to the gate electrode. Since the gate has a capacitance C of the above value, the amount of charge Q induced is
Q = C (V _g −V _t ) = 20400 pC = 2.04 × 10 ⁻⁸ C (35)
It is.

The electron surface mobility and μ = 300cm ² / Vs. The reciprocal of the current value when a voltage of 1 V is applied to the channel is the resistance value. When a voltage of 1V is applied to the channel, it produces a 1 / L electric field. The charge per unit length in the channel is given by Q / L. that is

Q / L = 2.04 × 10 ⁻⁸ C / 10 ⁻⁴ cm
= 2.04 × 10 ⁻⁴ C · cm ⁻¹ (36)

When a voltage of 1 V (10 ⁴ V / cm) is applied to the channel, the current that flows is

I = (Q / L) μ (1 / L)
= 2.04 × 10 ⁻⁴ C · cm ⁻¹ × 300 cm ² V ⁻¹ s ⁻¹ × 10 ⁴ Vcm ⁻¹
= 600C · s ^-1 = 600A (37)

It is. That is, the resistance of the channel is 1/600 = 1.7 mΩ. The resistance value is sufficiently low. It doesn't matter much. Therefore, most of the on-state resistance comes from the resistance of the drift layer (n-epi layer).

  The next problem is the formation of a depletion layer at the off time. When off, the pn junctions 9, 42, 40 are all reverse biased. The super junction (SJ) is a structure for forming a depletion layer in the lateral direction of the pnp structure.

The thickness of the vertical p columnar layer 33 is f = 1 μm = 10 ⁻⁴ cm. The voltage φ _p necessary for this to become a depletion layer is assumed to have a relative dielectric constant of 8,

_{φ p = qN A f / 2ε} = 1.6 × 10 -19 C × 10 16 cm -3 × 10 -8 cm 2 /(2×8×8.85×10 -14 F / cm) = 11V
(38)

The thickness of the n-type epi layer is g = 2 μm = 2 × 10 ⁻⁴ cm. The voltage φ _n necessary for this all to become a depletion layer is

_{^{φn = qN D g 2 /2ε=1.6×10 -19}} C × 10 16 cm -3 × 4 × 10 -8 cm 2 /(2×8×8.85×10 -14 F / cm) = 45V (39)

It is. That is, if a total voltage of 56 V is applied between the drain and source, the pnp layers on both sides of the pn junction 42 are all depleted layers. This element is assumed to be used at 200V to 800V. Therefore, the vertical p-columnar layer 33 and the n-epi layer 22 are always fully depleted layers at the off time.

Since such a condition is satisfied at the time of off, thereby increasing the donor concentration N _D of the n- epitaxial layer. N _D is as large as possible to reduce the on-resistance _{R ON} as described above.

The partial circuit diagram of the inverter part containing six IGBT (Insulated Gate Bipolar Transistor) for driving the motor of a hybrid vehicle.

FIG. 2 is a schematic cross-sectional view (1) of one unit of a vertical MOSFET generally used in a power device and a drain current characteristic diagram (2) at the time of turn-off.

A schematic cross-sectional view (1) for one unit of an IGBT element and a drain current characteristic diagram (2) at the time of turn-off.

A cross-sectional view (1) corresponding to one unit when the Siemens CoolMOSFET is turned on and a drain current characteristic diagram (2) when the device is turned off.

Sectional drawing for showing the breadth of the depletion layer at the time of OFF of Siemens CoolMOSFET.

1 is a cross-sectional view of a unit of 1.5 elements showing a first embodiment of a vertical power device of the present invention.

Sectional drawing for the element 1.5 unit which shows 2nd Example of the vertical power device of this invention.

Sectional drawing for the element 1.5 unit which shows 3rd Embodiment of the vertical power device of this invention.

The first half of the manufacturing process figure of the vertical power device element of this invention. (1) is a diagram showing an n-epi layer epitaxially grown on an n ⁺ -Si substrate. (2) is the figure which shows the state which made the oxide film on the n-epi layer and opened the hole in part by photolithography and etching. (3) is a diagram showing a process of forming a deep hole (trench) by etching the n-epi layer in the vertical direction using the oxide film as a mask. (4) is a diagram showing a state in which the entire oxide film and trench are covered with a solid diffusion layer containing p-type impurities (such as boron) and the trench is filled with the solid diffusion layer. (5) is a diagram showing a state in which a vertical p-columnar layer is generated by heating and diffusing p-type impurities laterally from the solid diffusion layer to the n-epi layer. (6) is the figure which shows the state which removed the solid diffusion layer and coat | covered the trench and the protruding part with the insulator. (7) is a diagram showing a state in which the trench is filled with an insulator. (8) is a diagram showing a state in which a part of the insulator is removed and the upper surface of the vertical p-columnar layer and the upper part of the n-epi layer are exposed. (9) A view showing a state in which a p-type well (p-type region) is formed by thermal diffusion in an n-epi layer and a vertical p-column type layer in which p-type impurities are exposed. (10) is a view showing a state where the upper surfaces of the p-type well and the n-epi layer are covered with an oxide film. (11) is a state in which a gate electrode is attached on the oxide film. (12) is a diagram showing a state in which an n ⁺ -region is formed by ion implantation of an n-type impurity using a gate electrode as a mask.

The latter half of the manufacturing process figure following FIG. 9 of the vertical type power device element of this invention. (1) is a view showing a state in which a resist is applied on an n ⁺ -region, a source portion where a p-type well is formed, and a gate portion. (2) is a diagram showing a state where a p ⁺ -type region is formed in a part of an n ⁺ -region by ion-implanting p-type impurities in a state where the gate portion is left and the resist is removed. (3) is a diagram showing a state in which the oxide film is etched using the gate electrode as a mask except for the resist covering the gate to expose the n-region and the p-region before and after the gate. (4) is a diagram showing a state in which an interlayer film is formed on the entire upper surface by CVD. (5) is a diagram showing a state in which an n-region and a p-region are exposed by removing a portion to be a source electrode while leaving a portion of an interlayer film on a gate electrode and an insulator. (6) is a diagram showing a source electrode 7 brought into contact with an n-region and a p-region exposed by sputtering Al.

Explanatory drawing which shows the breadth of a depletion layer, an electric field, and voltage distribution when reverse bias _Vr is applied before and behind a pn junction.

In the device of the present invention having a pnp structure arranged side by side, a depletion layer is generated and spreads from a pn junction when a reverse bias V _r is applied in a pnp structure formed by an n-epi layer and vertical p-columnar layers on the left and right sides thereof. Explanatory drawing for showing going. The reverse bias is small and the n-type epi layer is not completely depleted.

In a device of the present invention having a pnp structure arranged side by side, a depletion layer is formed from a pn junction when a sufficiently large reverse bias V _r is applied in a pnp structure formed by an n-epi layer and vertical p-columnar layers on the left and right sides thereof. It shows a state in which the n-type epi layer is formed and spreads on both sides and is completely depleted.

The figure which shows the vertical space charge distribution, electric field distribution, and voltage distribution in the element of this invention which has a structure where a pnp is located in a line at the time of OFF when the n-type epi layer turned into a complete depletion layer for reverse bias. Although written vertically to emphasize the vertical direction (z direction), it corresponds to FIG.

Explanation of symbols

1 n ⁺ -Si substrate
2 n ⁻ -epi layer
3 p ^- type well
4 n ⁺ type region 5 Gate insulating layer 6 Gate electrode (G)
7 Source electrode (S)
8 Drain electrode (D)
9 pn junction
10 channels
17 pn junction
18 p ⁺ layer
19 pn junction
22 n-type epi layer
23 Vertical p-column type layer
24 n-type epi layer
27 Trench
29 Oxide film
30 Solid diffusion layer
33 p-type diffusion layer
35 Insulator
36 Insulator
37 Insulator
38 Insulator
39 Insulator
40 pn junction
41 nn junction
42 pn junction
43 pn junction
44 ip junction
50 Oxide film 54 Resist 55 Resist film 56 p ⁺ type region 62

Claims (17)

A high-concentration or medium-concentration doped n-type epi layer 2 is epitaxially grown on the high-concentration n ⁺ -type Si substrate 1, and the n ⁺ -type Si substrate is vertically formed on the portions corresponding to both sides of the element unit of the n-type epi layer 2 A trench 27 is formed, and p-type impurities are diffused laterally into the n-type epilayer 2 by vapor phase diffusion or solid phase diffusion from the trench 27 to reach the n ⁺ -type Si substrate 1 in a portion in contact with the trench 27. Forming high-concentration or medium-concentration vertical p-columnar layers 33, 33, leaving the n-type epi layer 22, forming pnp structures aligned in the horizontal direction and pn junctions 42, 42 extending vertically, and removing the diffusion source from the trench; A trench 27 between adjacent element units is buried with insulating layers 35 and 36, and lightly doped p ⁻ type regions (p type wells) 3 and 3 are diffused on the n type epi layer 22 and the vertical p column type layer 33. Or shape by ion implantation Form, a low concentration p ^- inside the upper mold region 3, 3 provided by diffusion or ion implantation of high concentration ^{n +} -type regions 4, the low-concentration p ^{- p +} heavy type in the interior of the mold region 3, 3 The region is formed by diffusion or ion implantation, and the gate insulating film 5 and the gate electrode 6 are formed in the vertical direction in the n-type epi layer 22 so that the gate electrode 6 is directly bonded to the high concentration p ⁺ type region in the horizontal direction. And a source electrode 7 is formed on the p ⁻ -type regions 3 and 3 and the n ⁺ -type regions 4 and 4, and a drain electrode 8 is formed on the back surface of the n ⁺ -type Si substrate 1. A method of manufacturing a semiconductor device for power conversion. A high-concentration or medium-concentration n-type epi layer 2 is epitaxially grown on the high-concentration n ⁺ -type Si substrate 1, and the n ⁺ -type Si substrate is vertically formed on the portions of the n-type epi layer 2 corresponding to both sides of the element unit. A trench 27 having a depth that does not reach is drilled, and p-type impurities are diffused laterally into the n-type epilayer 2 from the trench 27 by vapor phase diffusion or solid phase diffusion, and n ⁺ -type Si is formed in a portion in contact with the trench 27. A high-concentration or medium-concentration vertical p-column type layer 33, 33 reaching the substrate 1 is formed, leaving the n-type epi layer 22, generating a pnp structure aligned in the horizontal direction and a vertically extending pn junction 42, 42 to generate a diffusion source from the trench The trench 27 between the adjacent element units is buried with the insulator layers 35 and 36, and the low concentration p ⁻ type region (p type well) 3 is formed on the n type epi layer 22 and the vertical p column type layer 33. 3 diffusion or ion implantation Formed by low-concentration p ^- provided by diffusion or ion implantation of high concentration ^{n +} -type region 4, 4 inside the upper mold region 3,3, a low concentration p ^- a high concentration in the interior of the mold region 3, 3 ^{p +} A type region is formed by diffusion or ion implantation, and a gate insulating film 5 and a gate electrode 6 are formed in the n-type epi layer 22 in the vertical direction, and the gate electrode 6 is directly bonded to the high concentration p ⁺ type region in the horizontal direction. Thus, a source electrode 7 is formed on the p ⁻ type regions 3 and 3 and the n ⁺ type regions 4 and 4, and a drain electrode 8 is formed on the back surface of the n ⁺ type Si substrate 1. A method for manufacturing a semiconductor device for in-vehicle power conversion. A high-concentration or medium-concentration n-type epi layer 2 is epitaxially grown on the high-concentration n ⁺ -type Si substrate 1, and the n ⁺ -type Si substrate is vertically formed on the portions of the n-type epi layer 2 corresponding to both sides of the element unit. A trench 27 is formed, and p-type impurities are diffused laterally into the n-type epi layer 2 by vapor phase diffusion or solid phase diffusion from the trench 27 to reach the n ⁺ -type Si substrate 1 at a portion in contact with the trench 27. Forming high-concentration or medium-concentration vertical p-columnar layers 33, 33, leaving the n-type epi layer 22, forming pnp structures aligned in the horizontal direction and pn junctions 42, 42 extending vertically, and removing the diffusion source from the trench; A trench 27 between adjacent element units is buried with insulating layers 35 and 36, and lightly doped p ⁻ type regions (p type wells) 3 and 3 are diffused on the n type epi layer 22 and the vertical p column type layer 33. Or shape by ion implantation Form, a low concentration p ^- inside the mold areas 3 provided by diffusion or ion implantation of high concentration ^{n +} -type regions 4, the low-concentration p ^- high concentration ^{p +} -type region in the interior of the mold region 3, 3 Is formed by diffusion or ion implantation, the gate electrode 6 is formed directly on the p ⁺ type region, the source electrode 7 is formed on the p ⁻ type regions 3 and 3 and the n ⁺ type regions 4 and 4, and n ^A method for manufacturing a semiconductor device for high-voltage on-vehicle power conversion, wherein a drain electrode 8 is formed on the back surface of a ⁺ -type Si substrate 1. A high-concentration or medium-concentration doped n-type epi layer 2 is epitaxially grown on the high-concentration n ⁺ -type Si substrate 1, and the n ⁺ -type Si substrate is vertically formed on the portions corresponding to both sides of the element unit of the n-type epi layer 2. A trench 27 having a depth that does not reach is drilled, and p-type impurities are diffused laterally into the n-type epilayer 2 from the trench 27 by vapor phase diffusion or solid phase diffusion, and n ⁺ -type Si is formed in a portion in contact with the trench 27. A high-concentration or medium-concentration vertical p-column type layer 33, 33 reaching the substrate 1 is formed, leaving the n-type epi layer 22, generating a pnp structure aligned in the horizontal direction and a vertically extending pn junction 42, 42 to generate a diffusion source from the trench The trench 27 between the adjacent element units is buried with the insulator layers 35 and 36, and the low concentration p ⁻ type region (p type well) 3 is formed on the n type epi layer 22 and the vertical p column type layer 33. 3 diffusion or ion implantation Formed by low-concentration p ^- provided within the mold region 3 by diffusion or ion implantation of high concentration n ⁺ -type regions 4, the low-concentration p ^- a high-concentration p ⁺ -type region in the interior of the mold region 3, 3 Formed by diffusion or ion implantation, the gate electrode 6 is formed directly on the p ⁺ -type region, the source electrode 7 is formed on the p ⁻ -type regions 3, 3 and the n ⁺ -type regions 4, 4, and n ⁺ A method of manufacturing a semiconductor device for high-voltage on-vehicle power conversion, wherein a drain electrode 8 is formed on the back surface of a Si substrate 1. On the heavily doped p ⁺ -type Si substrate, a high density or medium doped p-type epitaxial layer is epitaxially grown, the trenches extending in the vertical direction in a portion which corresponds to both sides of the element unit of the p-type epitaxial layer on the p ⁺ -type Si substrate A high-concentration or medium-concentration vertical n-pillar that penetrates and diffuses laterally from the trench into the p-type epi layer by vapor phase diffusion or solid-phase diffusion, and reaches the p ⁺ -type Si substrate at the portion in contact with the trench Forming a p-type layer and leaving a p-type epi layer, forming a laterally aligned npn structure and a vertically extending pn junction, removing the diffusion source from the trench, and embedding the trench between adjacent element units with an insulator layer; A low concentration n ⁻ type region (n type well) is formed on the p type epi layer and the vertical n columnar layer by diffusion or ion implantation, and a high concentration p ⁺ type region is formed above the low concentration n ⁻ type region. Diffusion or ion implantation Thus provided, a low concentration the n ^- high concentration n ⁺ -type region is formed by diffusion or ion implantation in the interior of the mold region, the gate electrode to form a gate insulating film and a gate electrode in the longitudinal direction in the p-type epitaxial layer is high and wherein the forming a source electrode on the type region and the p ⁺ -type region to form a drain electrode on the back surface of the p ⁺ -type Si substrate ^- to be bonded directly to the concentration n ⁺ -type region and lateral, n A method for manufacturing a semiconductor device for high-voltage in-vehicle power conversion. On the heavily doped p ⁺ -type Si substrate, a high density or medium doped p-type epitaxial layer is epitaxially grown, the depth does not reach the longitudinal direction at the site which corresponds to both sides of the element unit of the p-type epitaxial layer on the p ⁺ -type Si substrate The n-type impurity is laterally diffused into the p-type epi layer by vapor phase diffusion or solid phase diffusion from the trench, and a high concentration or medium reaching the p ⁺ -type Si substrate in the portion in contact with the trench. Concentration vertical n-column type layer is formed, p-type epi layer is left, npn structure arranged in the horizontal direction and pn junction extending vertically are formed, the diffusion source is removed from the trench, and the trench between adjacent element units is insulated A low-concentration n ⁻ -type region (n-type well) is formed by diffusion or ion implantation on the p-type epi layer and the vertical n-columnar layer, and a high-concentration p is formed inside the low-concentration n ⁻ -type region. ⁺ -type region diffusion or Provided by an on implantation, a low concentration the n ^- high concentration n ⁺ -type region is formed by diffusion or ion implantation in the interior of the mold region, the gate electrode to form a gate insulating film and a gate electrode in the longitudinal direction in the p-type epitaxial layer that forming a source electrode on the type region and the p ⁺ -type region to form a drain electrode on the back surface of the p ⁺ -type Si substrate ^- is to be bonded directly to the high-concentration n ⁺ -type region and lateral, n A method of manufacturing a semiconductor device for high-voltage on-vehicle power conversion, which is characterized. On the heavily doped p ⁺ -type Si substrate, a high density or medium doped p-type epitaxial layer is epitaxially grown, the trenches extending in the vertical direction in a portion which corresponds to both sides of the element unit of the p-type epitaxial layer on the p ⁺ -type Si substrate A high-concentration or medium-concentration vertical n-pillar that penetrates and diffuses laterally from the trench into the p-type epi layer by vapor phase diffusion or solid-phase diffusion, and reaches the p ⁺ -type Si substrate at the portion in contact with the trench Forming a p-type layer and leaving a p-type epi layer, forming a laterally aligned npn structure and a vertically extending pn junction, removing the diffusion source from the trench, and embedding the trench between adjacent element units with an insulator layer; A low-concentration n ⁻ -type region (n-type well) is formed on the p-type epi layer and vertical n-columnar layer by diffusion or ion implantation, and a high-concentration p ⁺ -type region is diffused inside the low-concentration n ⁻ type region. Or by ion implantation Te provided, the low-concentration n ^- -type region a high concentration n ⁺ -type region is formed by diffusion or ion implantation in the interior of, directly formed gate electrode on the n ⁺ -type region, n ^- type region and the p ⁺ -type region A method for manufacturing a semiconductor device for high-voltage on-vehicle power conversion, comprising forming a source electrode on the substrate and forming a drain electrode on the back surface of the p ⁺ -type Si substrate. On the heavily doped p ⁺ -type Si substrate, a high density or medium doped p-type epitaxial layer is epitaxially grown, the depth does not reach the longitudinal direction at the site which corresponds to both sides of the element unit of the p-type epitaxial layer on the p ⁺ -type Si substrate The n-type impurity is laterally diffused into the p-type epi layer by vapor phase diffusion or solid phase diffusion from the trench, and a high concentration or medium reaching the p ⁺ type Si substrate in the portion in contact with the trench. Concentration vertical n-column type layer is formed, p-type epi layer is left, npn structure arranged in the horizontal direction and pn junction extending vertically are formed, the diffusion source is removed from the trench, and the trench between adjacent element units is insulated A low concentration n ⁻ type region (n type well) is formed by diffusion or ion implantation on the p type epi layer and the vertical n columnar layer, and a high concentration p ⁺ is formed inside the low concentration n ⁻ type region. Diffusion or ion mold area Provided by infusion, low concentration the n ^- high concentration n ⁺ -type region is formed by diffusion or ion implantation in the interior of the mold area, to form a direct gate electrode on the n ⁺ -type region, n ^- -type region and the p ⁺ -type A method of manufacturing a semiconductor device for high-voltage on-vehicle power conversion, comprising forming a source electrode on a region and forming a drain electrode on a back surface of a p ⁺ -type Si substrate. An n ⁺ type Si substrate 1, a vertically extending high concentration or medium concentration n type epi layer 22 provided on the n ⁺ type Si substrate 1, and n generated by lateral diffusion on both sides of the n type epi layer 22. High-concentration or medium-concentration vertical p-columnar layers 33 and 33 reaching the ⁺ -type Si substrate 1, insulator layers 35 and 36 filling vertical p-columnar layers of adjacent elements, n-type epilayer 22, and vertical p-layer Low-concentration p ⁻ -type regions (p-type wells) 3 and 3 generated on the columnar layer 33 and high-concentration n ⁺ -type regions 4 and 4 generated inside the low-concentration p ⁻ -type regions 3 and 3. Then, the gate oxide film 5 that is in contact with the high-concentration p ⁺ -type regions 56 and 56 generated inside the low-concentration p ⁻ -type regions 3 and 3 and the high-concentration n ⁺ -type regions 4 and 4 and extends vertically. When a high concentration directly joined to the high-concentration p ⁺ -type region and laterally extends longitudinally provided inside the gate oxide film 5 n ⁺ -type regions 4 A gate electrode 6 facing laterally, p ^- -type region 3, 3 and the source electrode 7 formed on the high concentration n ⁺ -type region 4, 4, provided on the rear surface of the n ⁺ -type Si substrate 1 The drain electrode 8 is included, and the depletion layer extends in the lateral direction to the vertical p-column type layer 33 and the n-type epi layer 22 by the drain-source voltage when off, so that the n-type epi layer 22 is filled with the depletion layer. A high-voltage on-vehicle power conversion semiconductor device characterized by the above. An n ⁺ type Si substrate 1, a vertically extending high concentration or medium concentration n type epi layer 22 provided on the n ⁺ type Si substrate 1, and n generated by lateral diffusion on both sides of the n type epi layer 22. High-concentration or medium-concentration vertical p-columnar layers 33 and 33 that do not reach the ⁺ -type Si substrate 1, insulator layers 35 and 36 that fill vertical p-columnar layers of adjacent elements, an n-type epitaxial layer 22, and a vertical p-layer Low-concentration p ⁻ -type regions (p-type wells) 3 and 3 generated on the columnar layer 33 and high-concentration n ⁺ -type regions 4 and 4 generated inside the low-concentration p ⁻ -type regions 3 and 3. Then, the gate oxide film 5 that is in contact with the high-concentration p ⁺ -type regions 56 and 56 generated inside the low-concentration p ⁻ -type regions 3 and 3 and the high-concentration n ⁺ -type regions 4 and 4 and extends vertically. When the gate extends vertically provided inside the oxide film 5 is bonded directly to the high-concentration p ⁺ -type region and the lateral high-concentration n ⁺ -type region 4, And a gate electrode 6 facing laterally, p ^- -type region 3, 3 and the source electrode 7 formed on the high concentration n ⁺ -type regions 4, provided on the back surface of the n ⁺ -type Si substrate 1 In the off state, a depletion layer extends laterally to the vertical p-columnar layer 33 and the n-type epi layer 22 by the drain-source voltage so that the n-type epi layer 22 is filled with the depletion layer. A high-voltage on-vehicle power conversion semiconductor device characterized by the above. An n ⁺ type Si substrate 1, a vertically extending high concentration or medium concentration n type epi layer 22 provided on the n ⁺ type Si substrate 1, and n generated by lateral diffusion on both sides of the n type epi layer 22. High-concentration or medium-concentration vertical p-columnar layers 33, 33 reaching the ⁺ -type Si substrate 1, insulator layers 35, 36 filling between the vertical p-columnar layers 33, 33 of adjacent elements, and an n-type epilayer 22. Low concentration p ⁻ type regions (p type wells) 3 and 3 generated on the vertical p column type layer 33 and high concentration n ⁺ type generated inside the low concentration p ⁻ type regions 3 and 3 and regions 4, the low-concentration p ^- a high-concentration ^{p +} -type region 56, 56 is generated inside the mold areas 3, a gate electrode 6 provided directly on the ^{p +} -type region, p ^- a source electrode 7 formed on the mold region 3, 3 and ^{the n +} -type regions 4, provided on the rear surface of the ^{n +} -type Si substrate 1 drain The electrode 8 includes a depletion layer extending in the lateral direction to the vertical p-column type layer 33 and the n-type epi layer 22 by the drain-source voltage in the off state, and the n-type epi layer 22 is filled with the depletion layer. A semiconductor device for high-voltage in-vehicle power conversion, which is characterized. An n ⁺ type Si substrate 1, a vertically extending high concentration or medium concentration n type epi layer 22 provided on the n ⁺ type Si substrate 1, and n generated by lateral diffusion on both sides of the n type epi layer 22. High-concentration or medium-concentration vertical p-columnar layers 33 and 33 that do not reach the ⁺ -type Si substrate 1, insulator layers 35 and 36 that fill vertical p-columnar layers of adjacent elements, an n-type epitaxial layer 22, and a vertical p-layer Low-concentration p ⁻ -type regions (p-type wells) 3 and 3 generated on the columnar layer 33 and high-concentration n ⁺ -type regions 4 and 4 generated inside the low-concentration p ⁻ -type regions 3 and 3. When low-concentration p ^- a high-concentration ^{p +} -type region 56, 56 is generated inside the mold areas 3, a gate electrode 6 provided directly on the ^{p +} -type region, p ^- -type region 3, 3 and the n ⁺ -type source electrode 7 formed on a region 4, 4, n ⁺ -type Si drain electrode 8 provided on the back surface of the substrate 1 The depletion layer extends in the lateral direction to the vertical p-column type layer 33 and the n-type epi layer 22 by the drain-source voltage when off, and the n-type epi layer 22 is filled with the depletion layer. A semiconductor device for high-voltage in-vehicle power conversion. p ⁺ -type Si substrate and, p ⁺ -type Si high density or medium density p-type epi layer, p-type p ⁺ -type Si substrate produced by the lateral diffusion on both sides of the epitaxial layer that extends vertically provided on the substrate High-concentration or medium-concentration vertical n-columnar layer that reaches N, an insulating layer that fills the vertical n-columnar layers of adjacent elements, a p-type epi layer, and a low-concentration n generated on the vertical n-columnar layer ^- -type region (n-type well), the low-concentration n ^- and the high-concentration p ⁺ -type region that is generated in the interior of the mold region, low-concentration n ^- and the high-concentration n ⁺ -type region that is generated in the interior of the mold area, the high concentration p ⁺ -type region and a laterally contact a gate oxide film extending vertically, a high concentration n ⁺ -type region and laterally directly bonded high density p ⁺ -type region extends longitudinally provided inside the gate oxide film And a source electrode formed on the n ⁻ -type region and the high-concentration p ⁺ -type region, p ^And a drain electrode provided on the back surface of the ⁺ -type Si substrate, and when it is off, a depletion layer extends laterally to the vertical n-columnar layer and the p-type epi layer by the drain-source voltage, and the p-type epi layer is formed by the depletion layer. A high-voltage in-vehicle power conversion semiconductor device characterized by being satisfied. p ⁺ -type Si substrate and, p ⁺ -type Si high density or medium density p-type epi layer, p-type p ⁺ -type Si substrate produced by the lateral diffusion on both sides of the epitaxial layer that extends vertically provided on the substrate High-concentration or medium-concentration vertical n-columnar layer that does not reach N, an insulating layer that fills the vertical n-columnar layers of adjacent elements, a p-type epi layer, and a low-concentration n generated on the vertical n-columnar layer ^- -type region (n-type well), the low-concentration n ^- and the high-concentration p ⁺ -type region that is generated in the interior of the mold region, low-concentration n ^- and the high-concentration n ⁺ -type region that is generated in the interior of the mold area, the high concentration p ⁺ -type region and a laterally contact a gate oxide film extending vertically, a high concentration n ⁺ -type region and laterally directly bonded high density p ⁺ -type region extends longitudinally provided inside the gate oxide film And a source electrode formed on the n ⁻ type region and the high concentration p ⁺ type region, and a drain electrode provided on the back surface of the p ⁺ -type Si substrate. When turned off, a depletion layer extends laterally to the vertical n-column type layer and the p-type epi layer by the drain-source voltage, and the p-type epi layer is a depletion layer. A semiconductor device for high-voltage on-vehicle power conversion characterized by being satisfied by the above. p ⁺ -type Si substrate and, p ⁺ -type Si high density or medium density p-type epi layer, p-type p ⁺ -type Si substrate produced by the lateral diffusion on both sides of the epitaxial layer that extends vertically provided on the substrate High-concentration or medium-concentration vertical n-columnar layer that reaches N, an insulating layer that fills the vertical n-columnar layers of adjacent elements, a p-type epi layer, and a low-concentration n generated on the vertical n-columnar layer ^- -type region (n-type well), the low-concentration n ^- and the high-concentration p ⁺ -type region that is generated in the interior of the mold region, low-concentration n ^- and the high-concentration n ⁺ -type region that is generated in the interior of the mold area, a gate electrode provided directly on the n ⁺ type region, a source electrode formed on the n ⁻ type region and the p ⁺ type region, and a drain electrode provided on the back surface of the p ⁺ type Si substrate. When off, a drain-source voltage extends a depletion layer in the vertical direction to the vertical n-columnar layer and the p-type epi layer. High-voltage onboard power conversion semiconductor device characterized by pin layer has to be filled with the depletion layer. p ⁺ -type Si substrate and, p ⁺ -type Si high density or medium density p-type epi layer, p-type p ⁺ -type Si substrate produced by the lateral diffusion on both sides of the epitaxial layer that extends vertically provided on the substrate High-concentration or medium-concentration vertical n-columnar layer that does not reach N, an insulating layer that fills the vertical n-columnar layers of adjacent elements, a p-type epi layer, and a low-concentration n generated on the vertical n-columnar layer ^- -type region (n-type well), the low-concentration n ^- and the high-concentration p ⁺ -type region that is generated in the interior of the mold region, low-concentration n ^- and the high-concentration n ⁺ -type region that is generated in the interior of the mold area, a gate electrode provided directly on the n ⁺ type region, a source electrode formed on the n ⁻ type region and the p ⁺ type region, and a drain electrode provided on the back surface of the p ⁺ type Si substrate. When off, a depletion layer extends laterally to the vertical n-columnar layer and the p-type epi layer by the drain-source voltage. High-voltage onboard power conversion semiconductor device epitaxial layer is characterized in that so as to be filled with the depletion layer. The n-type semiconductor device according to any one of claims 9 to 12 and the p-type semiconductor device according to any one of claims 13 to 16 are connected in series by coupling a drain and a source. A high-voltage on-vehicle power conversion semiconductor device characterized by the above.

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