CN113517219B - Method for preventing metal corrosion after metal etching - Google Patents

Method for preventing metal corrosion after metal etching Download PDF

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Publication number
CN113517219B
CN113517219B CN202010276306.5A CN202010276306A CN113517219B CN 113517219 B CN113517219 B CN 113517219B CN 202010276306 A CN202010276306 A CN 202010276306A CN 113517219 B CN113517219 B CN 113517219B
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China
Prior art keywords
metal
etching
layer
substrate
corrosion
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CN202010276306.5A
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Chinese (zh)
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CN113517219A (en
Inventor
金宗范
周娜
李俊杰
杨涛
李俊峰
王文武
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure discloses a method for preventing metal corrosion after metal etching, comprising: providing a substrate, wherein a metal layer is arranged on one side surface of the substrate; etching the metal layer; and forming an oxide film on the metal surface. In the method, after metal etching, the oxide film formed on the metal surface can block the reaction of water vapor in the atmosphere with the residual chlorine component on the metal surface and in the metal surface, so that the occurrence of metal corrosion after metal etching is prevented.

Description

Method for preventing metal corrosion after metal etching
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a method for preventing metal corrosion after metal etching.
Background
In semiconductor manufacturing processes, in order to prevent corrosion of metal after an etching process of metal (e.g., aluminum), chlorine (Cl) components on the surface of the metal (e.g., aluminum) must be removed by forming a plasma with water vapor (H 2 O gas) in a stripping process chamber in the same equipment system. However, after the metal etching and wet removal processes, if equipment failure is encountered, the wafer needs to stand by in the factory for a certain period (typically 72 hours), and the Cl component remaining on the wafer reacts with water vapor existing in the factory atmosphere, so that corrosion is generated on the metal. How to prevent the Cl component remained after the metal etching from corroding the metal is a problem to be solved by those skilled in the art.
Disclosure of Invention
The present disclosure solves at least to some extent the above-mentioned technical problems in the related art. To this end, the present disclosure proposes a method of preventing migration of metal ions, after metal etching, depositing a silicon dioxide (SiO 2) film on the metal surface; the formed oxide film can prevent the reaction of water vapor in the atmosphere with the Cl component remained on the surface and in the metal, and prevent the occurrence of metal corrosion.
To achieve the above object, one aspect of the present disclosure provides a method of preventing metal corrosion after metal etching, comprising:
Providing a substrate, wherein a metal layer is arranged on one side surface of the substrate;
Etching the metal layer; and
And forming an oxide film on the surface of the metal.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method comprising using the method of preventing metal corrosion after metal etching as described in any one of the above.
The present disclosure has the following beneficial effects: in the method for preventing metal corrosion after metal etching, after the metal etching process is carried out, in order to prevent wafers from waiting in a factory for a long time (generally 72 hours), metal reacts with water vapor in the atmosphere of the factory to generate corrosion, a plasma reaction is generated in a stripping chamber by utilizing silane (SiH 4) gas and oxygen (O 2), and a silicon dioxide (SiO 2) film is deposited on the surface of the metal; the formed oxide film can prevent the reaction of water vapor in the atmosphere with the Cl component remained on the surface and in the metal, and prevent the occurrence of metal corrosion.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 illustrates a schematic structural view of a substrate and a pre-etched pattern on the substrate according to one embodiment of the present disclosure;
FIG. 2 shows a schematic diagram of the structure of FIG. 1 after etching of a metal layer thereon;
FIG. 3 is a schematic view showing the structure of FIG. 2 after ashing and removal of chlorine content from the metal surface;
Fig. 4 shows a schematic structure of forming an oxide film on the metal surface of the structure shown in fig. 3.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The metal aluminum is the most commonly used wire material in the preparation of semiconductors, and has the advantages of low resistance, easiness in deposition and etching and the like. Aluminum etching typically uses a chloride-based gas with the addition of a halide, most commonly BCl 3. Because aluminum is easily oxidized on the surface at normal temperature to generate aluminum oxide, the aluminum oxide prevents the normal etching, and BCl 3 can reduce a natural oxide layer to ensure the etching, and BCl 3 can easily react with oxygen and water to absorb water vapor and oxygen in a reaction cavity, so that the generation rate of the aluminum oxide is reduced.
In order to prevent corrosion of aluminum after etching the metal aluminum, a plasma must be formed in a stripping process chamber in the same equipment system using water vapor (H 2 O gas) to remove chlorine (Cl) components on the surface of the metal aluminum. However, after the aluminum etching and wet removal processes, if equipment failure is encountered, the wafer needs to stand by in the factory for a certain period (typically 72 hours), and the Cl component remaining on the wafer reacts with water vapor existing in the factory atmosphere, so that corrosion is generated on the metal aluminum.
One embodiment of the present disclosure provides a method for preventing metal corrosion after metal etching, comprising:
a: referring to fig. 1, a substrate 10 is provided, and a metal layer 20 is formed on one side surface of the substrate 10 by a physical vapor deposition (physical vapordeposition, PVD) process, a CVD process, or other suitable process.
A photoresist layer 30 having a pre-etched pattern is formed on a side surface of the metal layer 20 facing away from the substrate 10 using a deposition (e.g., a chemical vapor deposition (chemical vapor deposition) fabrication process or a spin-on-coating (spin-on) fabrication process), photolithography, etching (e.g., dry etching or wet etching), and the like.
The base 10 may be, for example, a bulk Silicon substrate, a Silicon-On-Insulator (abbreviated as SOI) substrate, a Germanium-On-Insulator (abbreviated as GOI) substrate, a Silicon Germanium substrate, a group III-V compound semiconductor substrate or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SELECTIVE EPITAXIAL GROWTH, abbreviated as SEG), or a dielectric layer material On the substrate, such as Silicon dioxide or other low dielectric constant material, etc., although not limited thereto.
The material of the metal layer 20 may be aluminum.
B: referring to fig. 2, the metal layer 20 is etched by using the photoresist layer 30 as an etching mask to form a desired pattern of the metal layer 20. After etching the metal layer 20, a large amount of chlorine components exist on the metal surface, and the chlorine components easily react with water vapor existing in the factory atmosphere, thereby corroding the metal.
An ashing process may then be used to remove the remaining photoresist layer 30. A specific ashing process is to utilize oxygen and nitrogen to react with the remaining photoresist layer 30 in a plasma.
Alternatively, after etching the metal layer 20 to expose the substrate 10, the over-etching of the substrate 10 may be continued.
In some embodiments, as shown in fig. 3, after etching of the metal layer 20, a substantial amount of chlorine content of the metal surface may be removed first to reduce the risk of metal corrosion. Specifically, the removing chlorine on the metal surface after etching the metal layer 20 includes: a plasma is formed using water vapor (H 2 O gas) to remove chlorine from the metal surface.
Wherein the metal may be aluminum.
C: referring to fig. 4, an oxide film 40 is formed on the metal surface using a deposition (e.g., chemical vapor deposition (chemical vapor deposition, CVD) fabrication process.
Wherein, the process of removing the residual photoresist layer 30, removing the chlorine on the metal surface after metal etching and forming the oxide film 40 on the metal surface is performed in the same stripping chamber; forming a silicon dioxide (SiO 2) film on the metal surface by utilizing plasma reaction of silane (SiH 4) gas and oxygen (O 2); the metal may be aluminum (Al).
Specifically, silane (SiH 4) gas and oxygen (O 2) are introduced into a stripping chamber installed in an Al etching system, a silicon dioxide (SiO 2) film is deposited on the surface of Al after a power supply is turned on, and a silicon dioxide (SiO 2) film is formed on the surface of Al so as to block the reaction of water vapor in the atmosphere with Cl components remained on the surface and inside of Al and prevent corrosion to Al.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method including a method of preventing metal corrosion after etching using a metal as described above.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Without departing from the scope of the present disclosure, various alternatives and modifications can be devised by those skilled in the art, such alternatives and modifications are intended to fall within the scope of the present disclosure.

Claims (5)

1. A method for preventing corrosion of a metal after etching the metal, comprising:
Providing a substrate, wherein a metal layer is arranged on one side surface of the substrate;
Etching the metal layer;
Removing the residual photoresist layer through an ashing process;
Forming plasma by using water vapor (H 2 O gas) to remove chlorine (Cl) components on the metal surface after the metal layer is etched; and
Forming an oxide film on the surface of the metal;
The forming of the oxide film on the metal surface comprises the following steps: forming a silicon dioxide (SiO 2) film on the metal surface by utilizing plasma reaction of silane (SiH 4) gas and oxygen (O 2);
the process of removing the residual photoresist layer, removing the chlorine component on the metal surface after the metal layer is etched and forming the oxide film on the metal surface is performed in the same stripping chamber.
2. The method of claim 1, wherein the material of the metal layer is aluminum.
3. The method of claim 1, wherein a photoresist layer is coated on a surface of the metal layer facing away from the substrate, and a predetermined pattern is etched on the surface of the metal layer using a photolithography process.
4. The method of claim 1 wherein the ashing process is a plasma reaction with the remaining photoresist layer using oxygen and nitrogen.
5. A method for manufacturing a semiconductor device, characterized in that the method comprises a method for preventing metal corrosion after etching using the metal according to any one of claims 1 to 4.
CN202010276306.5A 2020-04-09 2020-04-09 Method for preventing metal corrosion after metal etching Active CN113517219B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030531A (en) * 2006-02-27 2007-09-05 应用材料股份有限公司 Method for controlling corrosion of a substrate
CN110911353A (en) * 2019-12-05 2020-03-24 上海华虹宏力半导体制造有限公司 Method for forming conductive interconnection line

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244260B1 (en) * 1997-01-24 2000-03-02 김영환 Process for fabricating interconnector of semiconductor device
US6121130A (en) * 1998-11-16 2000-09-19 Chartered Semiconductor Manufacturing Ltd. Laser curing of spin-on dielectric thin films
KR100484896B1 (en) * 2002-09-18 2005-04-22 동부아남반도체 주식회사 Method for preventing metal-corrosion in the metal-etch process
KR100859480B1 (en) * 2006-12-29 2008-09-24 동부일렉트로닉스 주식회사 Semiconductor Device and Method of Fabricating the same
CN101740473B (en) * 2008-11-18 2012-12-12 中芯国际集成电路制造(上海)有限公司 Interlayer dielectric layer, interconnection structure and manufacturing method thereof
CN102082115B (en) * 2009-12-01 2014-03-19 无锡华润上华半导体有限公司 Aluminum interconnection structure and method for forming aluminum interconnection structure
CN102136451A (en) * 2010-01-27 2011-07-27 中芯国际集成电路制造(上海)有限公司 Method for forming metal interconnection
CN103474390B (en) * 2012-06-07 2015-09-09 无锡华润上华科技有限公司 A kind of manufacture method of aluminum metal lines

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030531A (en) * 2006-02-27 2007-09-05 应用材料股份有限公司 Method for controlling corrosion of a substrate
CN110911353A (en) * 2019-12-05 2020-03-24 上海华虹宏力半导体制造有限公司 Method for forming conductive interconnection line

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