CN101740473B - Interlayer dielectric layer, interconnection structure and manufacturing method thereof - Google Patents
Interlayer dielectric layer, interconnection structure and manufacturing method thereof Download PDFInfo
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- CN101740473B CN101740473B CN 200810202961 CN200810202961A CN101740473B CN 101740473 B CN101740473 B CN 101740473B CN 200810202961 CN200810202961 CN 200810202961 CN 200810202961 A CN200810202961 A CN 200810202961A CN 101740473 B CN101740473 B CN 101740473B
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Abstract
The invention discloses an interlayer dielectric layer, an interconnection structure and a manufacturing method thereof. The manufacturing method of the interlayer dielectric layer in a complementary metal-oxide semiconductor (CMOS) image sensor comprises the following steps of: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; reducing the thickness of the dielectric layer to a preset thickness; and forming a second dielectric layer and an anti-reflection layer on the thinned dielectric layer, wherein the dielectric layer does not contain fluorine. In the invention, the dielectric layer without fluorine is adopted for the interlayer dielectric layer, the diffusion of the fluorine of the fluorine-containing oxide in the prior art is avoided, and a first oxide layer for separation and a fourth oxide layer for repairing defects are unnecessary to add. The invention has advantages of less interlayer dielectric layers, simple structure, low cost, reduction of the light reflection and dispersion among layers and high transmittance. In addition, due to few layers, the stress among the layers is little, and cracking can not easily casued.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the interlayer dielectric layer in the cmos image sensor, interconnection structure and manufacturing approach thereof.
Background technology
In semi-conductor industry; Interconnection structure is used to be provided at device and the wiring between the whole encapsulation on the IC chip; In this technology; At first form the for example device of field-effect transistor (FET), then at postchannel process (BEOL, back-end-of-line) the middle interconnection structure that forms at semiconductor substrate surface.Common interconnection structure comprises at least a dielectric material, wherein is embedded with the metallic pattern of via hole and/or circuit form.
Prior art discloses a kind of postchannel process of semiconductor device; With reference to shown in Figure 1; Comprise: Semiconductor substrate 100 is provided; Be formed with device layer in the said Semiconductor substrate, on Semiconductor substrate 100, form undoped silicate glass oxide layer (USG) 110, be used for stoping from silicate glass oxide layer (FSG) fluorine of mixing fluorine on upper strata diffusing to other layer.Then; On undoped silicate glass oxide layer 110, form metal line pattern 120; Then; Form the silicate glass oxide layer 130 of mixing fluorine on the metal wire 120 with on the undoped silicate glass oxide layer 110, adopting chemical machinery equipment or etch-back technics (etch-back) to polish, last; Mixing formation undoped silicate glass oxide layer 140 on the silicate glass oxide layer 130 of fluorine; For between the silicate glass oxide layer 130 that prevents to mix fluorine and the undoped silicate glass oxide layer 140 because the difference of material causes that interfacial stress is excessive, and prior art also adopts siliceous or oxygen containing ion to bombard, so that discharge the stress in the silicate glass oxide layer 130 of mixing fluorine and the undoped silicate glass oxide layer 140.Then; On doped silicate glasses oxide layer 140, form upper strata metal wire 122, and upper strata FSG metal intermetallic dielectric layer 132, simultaneously; Between the metal wire 120 of upper strata metal wire 122 and lower floor, form contact hole 124 so that double layer of metal is interconnected; At last, on upper strata FSG metal intermetallic dielectric layer 132, form upper strata USG oxide layer 142, and adopt siliceous or oxygen containing ion to bombard to discharge stress.
, application number can also find more information relevant in being 11/841038 U.S. Patent application with technique scheme.
Prior art also discloses interconnection structure in a kind of postchannel process that forms cmos image sensor and forming method thereof; Please with reference to Fig. 2; Semiconductor substrate 201 is provided, is formed with device layer in the said Semiconductor substrate 201, be formed with metal interconnecting wires 203 on the said semiconductor lining 201; On metal interconnecting wires 203, form first oxide layer 204; Said first oxide layer 204 is that (silicon rich oxide SRO), is used for stopping that the diffusion of the follow-up fluorine-containing oxide layer fluorine that forms erodes in the metal interconnecting wires 203 above that to silicon rich oxide layer; On first oxide layer 204, form second oxide layer 205; Said second oxide layer 205 is used to fill the space between the metal interconnecting wires 203; Said second oxide layer 205 adopts high-density plasma CVD to form usually, can fill the space preferably, and is fluorine-containing in said second oxide layer 205; On second oxide layer 205, form the 3rd oxide layer 206, said the 3rd oxide layer 206 using plasmas strengthen CVD and form, and said the 3rd oxide layer 206 contains fluorine.Said second oxide layer 205 and the 3rd oxide layer 206 are referred to as oxide layer 207.The purpose that forms said the 3rd oxide layer 206 is further to reduce the rough and uneven in surface degree on second oxide layer, 205 surfaces, and convenient follow-up thinning process can reduce cost simultaneously.Because the technology cost of high-density plasma CVD is higher, therefore adopts this technology can not form the second enough thick oxide layer 205 usually, but adopt comparatively cheap technology to form the 3rd thicker oxide layer 206 again such as plasma enhanced CVD.
Then; With reference to Fig. 3; Adopt chemical-mechanical polisher to carry out attenuate and polishing; For chemical machinery equipment; Its polishing scope for oxide layer is
minute; Therefore usually be about
time and just stopped when throwing oxide layer 207, prevented to throw the device layer that causes destroying lower floor, the oxide layer 207 of this moment forms oxide layer 207a.
Then; With reference to Fig. 4; Employing is eat-back (etch-back) method and is continued etching; Usually be etched to oxide layer 207a and be about
time and stop, at this moment, oxide layer 207a forms oxide layer 207b.
At last, with reference to Fig. 5, on oxide layer 207b, form the 4th oxide layer 208, anti-reflecting layer 209 and the 5th oxide layer 210 successively; Said the 4th oxide layer 208 does not contain fluorine; Using plasma strengthens CVD and forms, and in blanket of nitrogen, handles simultaneously, repairs with the defective to the surface; The effect of said the 4th oxide layer is mainly to be isolated the oxide layer 207b of lower floor and upper strata anti-reflecting layer 209, prevents that the fluorine among the oxide layer 207b from diffusing into the upper strata; Said anti-reflecting layer 209 adopts silicon oxynitride usually; Said the 5th oxide layer 210 is plain silica, and said the 5th oxide layer 210 is used to protect anti-reflecting layer 209, prevents that anti-reflecting layer 209 is exposed to the airborne steam of absorption in the air.
In technique scheme, said interlayer dielectric layer adopts the oxide layer 207b that mixes fluorine, owing to the fluorine in the oxide of mixing fluorine spreads easily; Need increase by first oxide layer 204 betwixt and isolate, simultaneously, need growth regulation four oxide layers 208 to isolate and repair-deficiency; The interlayer dielectric layer that causes formation like this causes the increase of production cost and the complicacy of technology, simultaneously too much with blocked up; Because the layer that piles up is more, causes that the stress between the layer is bigger, easy of crack; And between layer and the layer reflection of light and scattering are increased, transmitance is low.
Summary of the invention
The problem that the present invention solves provides a kind of intermetallic interconnection layer and forming method thereof, to reduce interface layer reflection and scattering, improves light transmittance, reduces the technology cost simultaneously.
For addressing the above problem, the invention provides the manufacturing approach of the interlayer dielectric layer in a kind of cmos image sensor, comprising: Semiconductor substrate is provided; Form dielectric layer on the Semiconductor substrate; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively; Do not contain fluorine in the said dielectric layer.
Said dielectric layer comprises not fluorine-containing high-density oxide layer; Said high-density oxide layer adopts the high density plasma CVD device to form, the thickness range of said high-density oxide layer be 4500 to 6000
Said dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the high-density oxide layer, the thickness range of said silicate oxide layer be 8000 to 9000
Said the dielectric layer attenuate is comprised chemico-mechanical polishing, the said thickness range that is chemically mechanically polished to dielectric layer be 3500 to 4500
Eat-back the said dielectric layer attenuate is also comprised, the said thickness range that is etched back to dielectric layer be 1500 to 2500
Said anti-reflecting layer is a silicon oxynitride, and said second dielectric layer is a silica.
Also be formed with metal pickup layer and metal interconnecting wires on the said Semiconductor substrate successively, said metal interconnecting wires thickness range be 1800 to 3000
said metal pickup layer be 100 to 150
The present invention also provides the interlayer dielectric layer in a kind of as above prepared cmos image sensor.
The present invention also provides the manufacturing approach of the interconnection structure in a kind of cmos image sensor, comprising: Semiconductor substrate is provided, is formed with metal pickup layer and metal interconnecting wires on the said Semiconductor substrate successively; On Semiconductor substrate, form dielectric layer; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form second dielectric layer and anti-reflecting layer; Form opening in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate and expose metal interconnecting wires; Filled conductive material in opening; Form second metal interconnecting wires at second dielectric layer facing to aperture position; Do not contain fluorine in the said dielectric layer.
Said dielectric layer comprises not fluorine-containing high-density oxide layer; Said high-density oxide layer adopts the high density plasma CVD device to form, the thickness range of said high-density oxide layer be 4500 to 6000
Said dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the said high-density oxide layer, the thickness range of said silicate oxide layer be 8000 to 9000
Said the dielectric layer attenuate is comprised chemico-mechanical polishing, the said thickness range that is chemically mechanically polished to dielectric layer be 3500 to 4500
Eat-back the said dielectric layer attenuate is also comprised, the said thickness range that is etched back to dielectric layer be 1500 to 2500
Said metal interconnecting wires thickness range be 1800 to 3000
said metal pickup layer be 100 to 150
Interconnection structure in a kind of cmos image sensor that comprises as above manufacturing.
Compared with prior art; The present technique scheme has the following advantages: interlayer dielectric layer adopts not fluorine-containing dielectric layer; Avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily, need not to increase betwixt that first oxide layer is isolated and repair-deficiency is carried out in the 4th oxidation, the interlayer dielectric layer number of plies of formation is few; Simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced, transmitance is high; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Description of drawings
Fig. 1 is interconnection structure in the postchannel process (BEOL) of the semiconductor device of prior art and forming method thereof;
Fig. 2 to Fig. 5 is interconnection structure in the postchannel process of cmos image sensor in the prior art and forming method thereof;
Fig. 6 is the schematic flow sheet of formation interlayer dielectric layer of the present invention;
Fig. 7 to Figure 10 is the structural representation of the formation interlayer dielectric layer in the cmos image sensor technology of the present invention;
Figure 11 is the sketch map of formation interconnection structure of the present invention.
Embodiment
Interlayer dielectric layer of the present invention adopts not fluorine-containing dielectric layer; Avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily; Need not to increase betwixt that first oxide layer is isolated and the 4th oxide layer is carried out repair-deficiency; The interlayer dielectric layer number of plies that forms is few, simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced, transmitance is high; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Below through describing specific embodiment in detail according to accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:
With reference to Fig. 6, the present invention at first provides the manufacturing approach of the interlayer dielectric layer in a kind of cmos image sensor, comprising: Semiconductor substrate is provided; Execution in step S11 forms dielectric layer on Semiconductor substrate, do not contain fluorine in the said dielectric layer; Execution in step S13 is thinned to predetermined thickness with dielectric layer; Execution in step S15 forms second dielectric layer and anti-reflecting layer on the dielectric layer behind the attenuate.
With reference to Fig. 7 to Figure 10 the technology of the interlayer dielectric layer in the formation cmos image sensor of the present invention is described in detail below.
At first, Semiconductor substrate 301 to be provided, to be formed with device layer in the said Semiconductor substrate 301, in order simplifying, not add diagram here with reference to Fig. 7.
Be formed with discrete metal interconnecting wires 302 on the said Semiconductor substrate 301, said metal interconnecting wires 302 is used for the device in the Semiconductor substrate 301 of lower floor is drawn and is electrically connected to the output of rear end.Has the space between the said metal interconnecting wires 302.Generally, said metal interconnecting wires 302 is metal A l or Cu.
Simultaneously; Also be formed with the metal pickup layer on the Semiconductor substrate 301; Said metal interconnecting wires thickness range be 1800 to 3000
, said metal pickup layer be 100 to 150
If metal interconnecting wires 302 is Cu; Then form technology and adopt the different of metal A l, need to adopt damascene structure, concrete technology is such as being elder generation's formation dielectric layer; In dielectric layer, form through hole (via) and groove (trench) then, in groove and through hole, fill metal Cu then.
On the metal interconnecting wires 302 of separation and the Semiconductor substrate 301 that exposes, form dielectric layer 305 therebetween, do not contain fluorine in the said dielectric layer 305.Among the present invention; Said dielectric layer 305 comprises not fluorine-containing high-density oxide layer 303, the thickness range of said high-density oxide layer 303 be 4500 to 6000
In the prior art; Usually adopt the silicate glass oxide (FSG) of mixing fluorine as dielectric layer; Mainly be to utilize high temperature to form the higher hole ability of filling out of the silicate glass oxide of mixing fluorine; And the silicate glass oxide (USG) of not mixing fluorine adopts the preparation of high density plasma CVD method usually, when filling out the hole, occurs easily filling the cavity that not exclusively causes, thereby is not adopted by those skilled in the art.The present inventor passes through to improve metal interconnecting wires and metal pickup layer, and thickness is optimized to realize the object of the invention.The application inventor is through discover in a large number: will be thinned to as the metal aluminium lamination of metal interconnecting wires 1800 to 3000
as the thickness of the Ti/TiN layer of metal pickup layer also be thinned to 100 to 150
the silicate glass oxide (USG) of not mixing fluorine can realize the high-quality hole ability of filling out; So both made the slit between the metal interconnecting wires fill fully; And can not influence the resistance value of metal interconnecting wires, can adopt it as metal intermetallic dielectric layer.
And; Owing to do not contain fluorine in the high-density oxide layer 303; Therefore need not to resemble the oxide layer that needs at first on metal interconnecting wires 302 and the Semiconductor substrate 301 that exposes, to form Silicon-rich therebetween of prior art and isolate, spread in the metal interconnecting wires 302 that corrodes lower floor with the fluorine in the fluorine-containing layer that prevents follow-up formation.
The technology that forms said high-density oxide layer 303 is technology as well known to those skilled in the art, does not add detailed description at this.
Said dielectric layer 305 also comprises not fluorine-containing silicate oxide layer 304; The purpose that forms said not fluorine-containing silicate oxide layer 304 is further to reduce the rough and uneven in surface degree on high-density oxide layer 303 surface; Convenient follow-up thinning process can reduce cost simultaneously.Said silicate oxide layer 304 using plasma strengthen CVD and form; Because the technology cost of high-density plasma CVD is higher; Therefore the high-density oxide layer 303 that adopts this technology to form usually can be very not thick; But adopt comparatively cheap technology to thicken such as plasma enhanced CVD, form silicate oxide layer 304.Can polish through existing polishing technology then, thus the surface of formation substantially flat.
Said silicate oxide layer 304 thickness range be 8000 to 9000
Therefore equally, do not contain fluorine in the mesosilicic acid salt oxide skin(coating) 304 of the present invention, need not to resemble the oxide layer that needs to form earlier Silicon-rich of prior art, corrode the metal interconnecting wires 302 of lower floor to prevent the fluorine diffusion in the fluorine-containing dielectric layer.
Then; With reference to Fig. 8; Need dielectric layer 305 be thinned to predetermined thickness; Among the present invention; Said dielectric layer 305 attenuates are comprised chemical-mechanical polishing step; The said thickness range that is chemically mechanically polished to dielectric layer be 3500 to 4500
such as can for 4000
for chemical machinery equipment; Its polishing scope for oxide skin(coating) is
therefore usually when throw dielectric layer 305 be about 4000
time just stopped; To prevent to throw the device layer that causes destroying lower floor; Through polishing, dielectric layer 305 forms dielectric layer 305a.
With reference to Fig. 9; In order further to improve the transmitance of light; Need be with the further attenuate of dielectric layer 305a; Eat-back said dielectric layer 305a attenuate is also comprised; The said thickness range that is etched back to dielectric layer be 1500 to 2500
such as can for 2000
through after eat-backing, dielectric layer 305a forms dielectric layer 305b.
With reference to Figure 10; On the process dielectric layer 305b of attenuate, form anti-reflecting layer 306; Said anti-reflecting layer 307 adopts silicon oxynitrides usually, the thickness range of said anti-reflecting layer 306 be 600
Then, on anti-reflecting layer 306, form second dielectric layer 307, said second dielectric layer 307 adopts not fluorine-containing silica, absorbs airborne steam so that be absorbed in the photoetching process in the air because anti-reflecting layer 306 is exposed to, and is used to protect anti-reflecting layer 306.The thickness of said second dielectric layer 307 be 200
The interlayer dielectric layer adopts not fluorine-containing silicate oxide layer 304 among the present invention, and the 4th not fluorine-containing oxide layer 208 that need not to resemble among the Fig. 5 of formation of prior art is isolated, though the 4th oxide layer 208 also has the effect of reparation blemish; But because its counter productive of bringing is the thickness that has increased dielectric layer, cause light path elongated, be unfavorable for seeing through of light; Its shortcoming is compared with its advantage; Shortcoming is greater than advantage, so among the present invention, do not form this layer.Simplified technology like this, cost reduces, and the number of plies reduces, and helps seeing through of light.
Form the interlayer dielectric layer in the cmos image sensor of the present invention through above-mentioned technology, with reference to Figure 10, comprising: be positioned at dielectric layer 305b, anti-reflecting layer 306 and second dielectric layer 307 on the Semiconductor substrate 301 successively; Do not contain fluorine in the said dielectric layer 305b.
Said anti-reflecting layer 306 is a silicon oxynitride, and said second dielectric layer 307 is a silica.
Form interlayer dielectric layer of the present invention through above-mentioned technology; The thickness of the dielectric layer 305b of said interlayer dielectric layer only have 1500 to 2500
compared with prior art; Thickness reduces greatly, helps improving the transmitance of light; Simultaneously, because the number of plies is few, stress is little, the cracking phenomena of prior art can not occur.
Simultaneously, the present invention gives the manufacturing approach of the interconnection structure in a kind of cmos image sensor, comprising: Semiconductor substrate is provided, is formed with discrete interconnect metallization lines on the said Semiconductor substrate; On Semiconductor substrate, form dielectric layer; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer; Same position in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate forms opening and exposes interconnect metallization lines; Filled conductive material in opening; On second dielectric layer, form second interconnect metallization lines facing to aperture position; Do not contain fluorine in the said dielectric layer.
The manufacturing approach of the interconnection structure in the said cmos image sensor comprises the technology of aforesaid manufacturing interlayer dielectric layer, and concrete technology is please with reference to Fig. 7 to Figure 10.
Then, please continue, form opening in the dielectric layer 305b behind second dielectric layer 307, anti-reflecting layer 306 and attenuate and expose interconnect metallization lines 302 with reference to Figure 11; Filled conductive material 308 in opening; On second dielectric layer 307, form second interconnect metallization lines 309 facing to aperture position, said second interconnect metallization lines 309 is electrically connected with metal interconnecting wires 302 through electric conducting material 308; Do not contain fluorine in the said dielectric layer 305b.
Then; On second metal interconnecting wires 309 and second dielectric layer 307, form the 3rd dielectric layer 310; Said the 3rd dielectric layer 310 does not contain fluorine, with reference to aforementioned same technology, on the 3rd dielectric layer 310, forms second anti-reflecting layer 311 and the 4th dielectric layer 312 successively.
In semi-conductive interconnection process, also possibly comprise more interlayer dielectric layer and metal interconnecting wires layer, only explain at this with double layer of metal and two layers of dielectric layer, should too much not limit protection scope of the present invention at this.
Based on above-mentioned technology, formed the interconnection structure in the cmos image sensor of the present invention, with reference to Figure 11, comprising: be positioned at dielectric layer 305b, anti-reflecting layer 306 and second dielectric layer 307 behind the attenuate on the Semiconductor substrate 301 successively; Be positioned at the opening of the dielectric layer 305b behind second dielectric layer 307, anti-reflecting layer 306 and the attenuate and the electric conducting material 308 that is filled in opening; Be positioned at second metal interconnecting wires 309 on second dielectric layer 307; Be positioned at the 3rd dielectric layer 310, second anti-reflecting layer 311 and the 4th dielectric layer 312 on second metal interconnecting wires 309 and second dielectric layer 307 successively; Do not contain fluorine in said dielectric layer 305b and the 3rd dielectric layer 310.
Interlayer dielectric layer of the present invention adopts not fluorine-containing dielectric layer 305b and the 3rd dielectric layer 310; Avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily; Need not to increase betwixt that first oxide layer is isolated and the 4th oxide layer is carried out repair-deficiency; The interlayer dielectric layer number of plies that forms is few, simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced, transmitance is high; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (13)
1. the manufacturing approach of the interlayer dielectric layer in the cmos image sensor comprises:
Semiconductor substrate is provided;
On Semiconductor substrate, form dielectric layer;
Dielectric layer is thinned to predetermined thickness;
On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively;
It is characterized in that, do not contain fluorine in the said dielectric layer;
Also be formed with metal pickup layer and metal interconnecting wires on the said Semiconductor substrate successively, the formation step of the said metal interconnecting wires of attenuate thickness range to 1800 to
said metal pickup layer thickness of attenuate scope to 100 to
said dielectric layer is after the formation step of metal pickup layer and metal interconnecting wires; The thickness range of the said dielectric layer of attenuate is to
2. the manufacturing approach of interlayer dielectric layer according to claim 1; It is characterized in that; Said dielectric layer comprises not fluorine-containing high-density oxide layer; Said high-density oxide layer adopts the high density plasma CVD device to form, and the thickness range of said high-density oxide layer is 4500 to
3. the manufacturing approach of interlayer dielectric layer according to claim 2; It is characterized in that; Said dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the said high-density oxide layer, and the thickness range of said silicate oxide layer is 8000 to
4. the manufacturing approach of interlayer dielectric layer according to claim 1; It is characterized in that; Said the dielectric layer attenuate is comprised chemico-mechanical polishing, the said thickness range that is chemically mechanically polished to dielectric layer is 3500 to
5. according to the manufacturing approach of claim 1 or 4 described interlayer dielectric layers, it is characterized in that eat-back the said dielectric layer attenuate is also comprised.
6. the manufacturing approach of interlayer dielectric layer according to claim 1 is characterized in that, said second dielectric layer is a silica, and said anti-reflecting layer is a silicon oxynitride.
7. one kind like the interlayer dielectric layer in the cmos image sensor of each manufacturing in the claim 1 to 6.
8. the manufacturing approach of the interconnection structure in the cmos image sensor comprises:
Semiconductor substrate is provided, is formed with metal pickup layer and metal interconnecting wires on the said Semiconductor substrate successively;
On Semiconductor substrate, form dielectric layer;
Dielectric layer is thinned to predetermined thickness;
On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively;
Form opening in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate and expose interconnect metallization lines;
Filled conductive material in opening;
On anti-reflecting layer, form second metal interconnecting wires facing to aperture position;
It is characterized in that, do not contain fluorine in the said dielectric layer;
Thinning the metal interconnect wire thickness range up to 1800 to
thinning the metal adhesive layer thickness range up to 100 to
thinning the dielectric layer thickness range to
9. the manufacturing approach of interconnection structure according to claim 8; It is characterized in that; Said dielectric layer comprises not fluorine-containing high-density oxide layer; Said high-density oxide layer adopts the high density plasma CVD device to form, and the thickness range of said high-density oxide layer is 4500 to
10. the manufacturing approach of interconnection structure according to claim 9; It is characterized in that; Said dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the said high-density oxide layer, and the thickness range of said silicate oxide layer is 8000 to
11. the manufacturing approach of interconnection structure according to claim 10; It is characterized in that; Said the dielectric layer attenuate is comprised chemico-mechanical polishing, the said thickness range that is chemically mechanically polished to dielectric layer is 3500 to
12. according to Claim 8 or the manufacturing approach of 11 described interconnection structures, it is characterized in that eat-back the said dielectric layer attenuate is also comprised.
13. one kind like the interconnection structure in the cmos image sensor of each manufacturing in the claim 8 to 11.
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| CN102820256A (en) * | 2011-06-08 | 2012-12-12 | 无锡华润上华半导体有限公司 | Method for preparing inter-metal dielectric layer |
| CN103094194B (en) * | 2011-11-01 | 2016-01-13 | 无锡华润上华科技有限公司 | The formation method of metal interlayer medium and metal interlayer medium structure |
| US8629559B2 (en) | 2012-02-09 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus with an inverted cup-shaped layer |
| KR20200016472A (en) * | 2018-08-07 | 2020-02-17 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| CN113517219A (en) * | 2020-04-09 | 2021-10-19 | 中国科学院微电子研究所 | Method for preventing metal corrosion after metal etching |
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| CN1447414A (en) * | 2002-03-27 | 2003-10-08 | 三洋电机株式会社 | Mfg. method of semiconductor device with opening portion |
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