CN101740473A - Interlayer dielectric layer, interconnection structure and manufacturing method thereof - Google Patents
Interlayer dielectric layer, interconnection structure and manufacturing method thereof Download PDFInfo
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- CN101740473A CN101740473A CN200810202961A CN200810202961A CN101740473A CN 101740473 A CN101740473 A CN 101740473A CN 200810202961 A CN200810202961 A CN 200810202961A CN 200810202961 A CN200810202961 A CN 200810202961A CN 101740473 A CN101740473 A CN 101740473A
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Abstract
The invention discloses an interlayer dielectric layer, an interconnection structure and a manufacturing method thereof. The manufacturing method of the interlayer dielectric layer in a complementary metal-oxide semiconductor (CMOS) image sensor comprises the following steps of: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; reducing the thickness of the dielectric layer to a preset thickness; and forming a second dielectric layer and an anti-reflection layer on the thinned dielectric layer, wherein the dielectric layer does not contain fluorine. In the invention, the dielectric layer without fluorine is adopted for the interlayer dielectric layer, the diffusion of the fluorine of the fluorine-containing oxide in the prior art is avoided, and a first oxide layer for separation and a fourth oxide layer for repairing defects are unnecessary to add. The invention has advantages of less interlayer dielectric layers, simple structure, low cost, reduction of the light reflection and dispersion among layers and high transmittance. In addition, due to few layers, the stress among the layers is little, and cracking can not easily casued.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the interlayer dielectric layer in the cmos image sensor, interconnection structure and manufacture method thereof.
Background technology
In semi-conductor industry, interconnection structure is used to be provided at device on the IC chip and the wiring between the whole encapsulation, in this technology, at first form for example device of field-effect transistor (FET) at semiconductor substrate surface, then at postchannel process (BEOL, back-end-of-line) the middle interconnection structure that forms.Common interconnection structure comprises at least a dielectric material, wherein is embedded with the metallic pattern of via hole and/or circuit form.
Prior art discloses a kind of postchannel process of semiconductor device, with reference to shown in Figure 1, comprise: Semiconductor substrate 100 is provided, be formed with device layer in the described Semiconductor substrate, on Semiconductor substrate 100, form undoped silicate glass oxide layer (USG) 110, be used for stoping from silicate glass oxide layer (FSG) fluorine of mixing fluorine on upper strata diffusing to other layer.Then, on undoped silicate glass oxide layer 110, form metal line pattern 120, then, forming the silicate glass oxide layer 130 of mixing fluorine on the metal wire 120 and on the undoped silicate glass oxide layer 110, adopt chemical machinery equipment or etch-back technics (etch-back) to polish, at last, mixing formation undoped silicate glass oxide layer 140 on the silicate glass oxide layer 130 of fluorine, for between the silicate glass oxide layer 130 that prevents to mix fluorine and the undoped silicate glass oxide layer 140 because the difference of material causes that interfacial stress is excessive, prior art also adopts siliceous or oxygen containing ion to bombard, so that the silicate glass oxide layer 130 of fluorine and the stress in the undoped silicate glass oxide layer 140 are mixed in release.Then, on doped silicate glasses oxide layer 140, form upper strata metal wire 122, and upper strata FSG metal intermetallic dielectric layer 132, simultaneously, between the metal wire 120 of upper strata metal wire 122 and lower floor, form contact hole 124 so that double layer of metal is interconnected, at last, on upper strata FSG metal intermetallic dielectric layer 132, form upper strata USG oxide layer 142, and adopt siliceous or oxygen containing ion to bombard to discharge stress.
In being 11/841038 U.S. Patent application, application number can also find more information relevant with technique scheme.
Prior art also discloses interconnection structure in a kind of postchannel process that forms cmos image sensor and forming method thereof, please refer to Fig. 2, Semiconductor substrate 201 is provided, be formed with device layer in the described Semiconductor substrate 201, be formed with metal interconnecting wires 203 on the described semiconductor lining 201, on metal interconnecting wires 203, form first oxide layer 204, described first oxide layer 204 is silicon rich oxide layer (silicon rich oxide, SRO), be used for stopping that the diffusion of the follow-up fluorine-containing oxide layer fluorine that forms erodes in the metal interconnecting wires 203 thereon; On first oxide layer 204, form second oxide layer 205, described second oxide layer 205 is used to fill the space between the metal interconnecting wires 203, described second oxide layer 205 adopts high-density plasma CVD to form usually, can fill the space preferably, and is fluorine-containing in described second oxide layer 205; Form the 3rd oxide layer 206 on second oxide layer 205, described the 3rd oxide layer 206 using plasmas strengthen CVD and form, and described the 3rd oxide layer 206 contains fluorine.Described second oxide layer 205 and the 3rd oxide layer 206 are referred to as oxide layer 207.The purpose that forms described the 3rd oxide layer 206 is further to reduce the rough and uneven in surface degree on second oxide layer, 205 surfaces, and convenient follow-up thinning process can reduce cost simultaneously.Because the technology cost of high-density plasma CVD is higher, therefore adopts this technology can not form the second enough thick oxide layer 205 usually, but adopt comparatively cheap technology to form the 3rd thicker oxide layer 206 again such as plasma enhanced CVD.
Then, with reference to Fig. 3, adopt chemical-mechanical polisher to carry out attenuate and polishing, for chemical machinery equipment, its polishing scope for oxide layer is
/ minute, therefore be about when throwing oxide layer 207 usually
In time, just stopped, and prevented to throw the device layer that causes destroying lower floor, and the oxide layer 207 of this moment forms oxide layer 207a.
Then,, adopt and eat-back (etch-back) method continuation etching, be etched to oxide layer 207a usually and be about with reference to Fig. 4
In time, stop, and at this moment, oxide layer 207a forms oxide layer 207b.
At last, with reference to Fig. 5, on oxide layer 207b, form the 4th oxide layer 208, anti-reflecting layer 209 and the 5th oxide layer 210 successively, described the 4th oxide layer 208 does not contain fluorine, using plasma strengthens CVD and forms, and handles in blanket of nitrogen simultaneously, repairs with the defective to the surface, the effect of described the 4th oxide layer is mainly to be isolated the oxide layer 207b of lower floor and upper strata anti-reflecting layer 209, prevents that the fluorine among the oxide layer 207b from diffusing into the upper strata; Described anti-reflecting layer 209 adopts silicon oxynitride usually; Described the 5th oxide layer 210 is plain silica, and described the 5th oxide layer 210 is used to protect anti-reflecting layer 209, prevents that anti-reflecting layer 209 is exposed to the airborne steam of absorption in the air.
In technique scheme, described interlayer dielectric layer adopts the oxide layer 207b that mixes fluorine, owing to the fluorine in the oxide of mixing fluorine spreads easily, need increase by first oxide layer 204 betwixt isolates, simultaneously, need growth regulation four oxide layers 208 to isolate and repair-deficiency, the interlayer dielectric layer that causes formation like this is too much with blocked up, cause the increase of production cost and the complexity of technology, simultaneously, because the layer that piles up is more, cause that the stress between the layer is bigger, between cracking, and layer easily and the layer reflection of light and scattering are increased, transmitance is low.
Summary of the invention
The problem that the present invention solves provides a kind of intermetallic interconnection layer and forming method thereof, to reduce interface layer reflection and scattering, improves light transmittance, reduces the technology cost simultaneously.
For addressing the above problem, the invention provides the manufacture method of the interlayer dielectric layer in a kind of cmos image sensor, comprising: Semiconductor substrate is provided; Form dielectric layer on the Semiconductor substrate; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively; Do not contain fluorine in the described dielectric layer.
Described dielectric layer comprises not fluorine-containing high-density oxide layer, and described high-density oxide layer adopts the high density plasma CVD device to form, the thickness range of described high-density oxide layer be 4500 to
Described dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the high-density oxide layer, the thickness range of described silicate oxide layer be 8000 to
Described the dielectric layer attenuate is comprised chemico-mechanical polishing, the described thickness range that is chemically mechanically polished to dielectric layer be 3500 to
Eat-back the described dielectric layer attenuate is also comprised, the described thickness range that is etched back to dielectric layer be 1500 to
Described anti-reflecting layer is a silicon oxynitride, and described second dielectric layer is a silica.
Also be formed with metal pickup layer and metal interconnecting wires on the described Semiconductor substrate successively, described metal interconnecting wires thickness range be 1800 to
Described metal pickup layer be 100 to
The present invention also provides the interlayer dielectric layer in a kind of as above prepared cmos image sensor.
The present invention also provides the manufacture method of the interconnection structure in a kind of cmos image sensor, comprising: Semiconductor substrate is provided, is formed with metal pickup layer and metal interconnecting wires on the described Semiconductor substrate successively; On Semiconductor substrate, form dielectric layer; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form second dielectric layer and anti-reflecting layer; Form opening in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate and expose metal interconnecting wires; Filled conductive material in opening; Form second metal interconnecting wires at second dielectric layer facing to aperture position; Do not contain fluorine in the described dielectric layer.
Described dielectric layer comprises not fluorine-containing high-density oxide layer, and described high-density oxide layer adopts the high density plasma CVD device to form, the thickness range of described high-density oxide layer be 4500 to
Described dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the described high-density oxide layer, the thickness range of described silicate oxide layer be 8000 to
Described the dielectric layer attenuate is comprised chemico-mechanical polishing, the described thickness range that is chemically mechanically polished to dielectric layer be 3500 to
Eat-back the described dielectric layer attenuate is also comprised, the described thickness range that is etched back to dielectric layer be 1500 to
Described metal interconnecting wires thickness range be 1800 to
Described metal pickup layer be 100 to
Interconnection structure in a kind of cmos image sensor that comprises as above manufacturing.
Compared with prior art, the technical program has the following advantages: interlayer dielectric layer adopts not fluorine-containing dielectric layer, avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily, need not to increase betwixt that first oxide layer is isolated and repair-deficiency is carried out in the 4th oxidation, the interlayer dielectric layer number of plies that forms is few, simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced the transmitance height; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Description of drawings
Fig. 1 is interconnection structure in the postchannel process (BEOL) of the semiconductor device of prior art and forming method thereof;
Fig. 2 to Fig. 5 is interconnection structure in the postchannel process of cmos image sensor in the prior art and forming method thereof;
Fig. 6 is the schematic flow sheet of formation interlayer dielectric layer of the present invention;
Fig. 7 to Figure 10 is the structural representation of the formation interlayer dielectric layer in the cmos image sensor technology of the present invention;
Figure 11 is the schematic diagram of formation interconnection structure of the present invention.
Embodiment
Interlayer dielectric layer of the present invention adopts not fluorine-containing dielectric layer, avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily, need not to increase betwixt that first oxide layer is isolated and the 4th oxide layer is carried out repair-deficiency, the interlayer dielectric layer number of plies that forms is few, simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced the transmitance height; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Below describe specific embodiment in detail by the foundation accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:
With reference to Fig. 6, the present invention at first provides the manufacture method of the interlayer dielectric layer in a kind of cmos image sensor, comprising: Semiconductor substrate is provided; Execution in step S11 forms dielectric layer on Semiconductor substrate, do not contain fluorine in the described dielectric layer; Execution in step S13 is thinned to predetermined thickness with dielectric layer; Execution in step S15 forms second dielectric layer and anti-reflecting layer on the dielectric layer behind the attenuate.
Below with reference to Fig. 7 to Figure 10 the technology of the interlayer dielectric layer in the formation cmos image sensor of the present invention is described in detail.
At first, to provide Semiconductor substrate 301, be formed with device layer in the described Semiconductor substrate 301, in order simplifying, not add diagram herein with reference to Fig. 7.
Be formed with discrete metal interconnecting wires 302 on the described Semiconductor substrate 301, described metal interconnecting wires 302 is used for the device in the Semiconductor substrate 301 of lower floor is drawn and is electrically connected to the output of rear end.Has the space between the described metal interconnecting wires 302.Generally, described metal interconnecting wires 302 is metal A l or Cu.
Simultaneously, also be formed with the metal pickup layer on the Semiconductor substrate 301, described metal interconnecting wires thickness range be 1800 to
Described metal pickup layer be 100 to
If metal interconnecting wires 302 is Cu, then form technology and adopt the different of metal A l, need to adopt damascene structure, concrete technology is such as being elder generation's formation dielectric layer, in dielectric layer, form through hole (via) and groove (trench) then, in groove and through hole, fill metal Cu then.
On discrete metal interconnecting wires 302 and the Semiconductor substrate 301 that exposes, form dielectric layer 305 therebetween, do not contain fluorine in the described dielectric layer 305.Among the present invention, described dielectric layer 305 comprises not fluorine-containing high-density oxide layer 303, the thickness range of described high-density oxide layer 303 be 4500 to
In the prior art, usually adopt and mix the silicate glass oxide (FSG) of fluorine as dielectric layer, mainly be to utilize high temperature to form the higher hole ability of filling out of the silicate glass oxide of mixing fluorine, and the silicate glass oxide (USG) of not mixing fluorine adopts the preparation of high density plasma CVD method usually, when filling out the hole, occur easily filling the cavity that not exclusively causes, thereby do not adopted by those skilled in the art.The present inventor passes through to improve metal interconnecting wires and metal pickup layer, and thickness is optimized to realize purpose of the present invention.The present application people is through discovering in a large number: will be thinned to as the metal aluminium lamination of metal interconnecting wires 1800 to
As the thickness of the Ti/TiN layer of metal pickup layer also be thinned to 100 to
Do not mix the silicate glass oxide (USG) of fluorine and can realize the high-quality hole ability of filling out, so both made that the slit between the metal interconnecting wires was filled fully, and can not influence the resistance value of metal interconnecting wires, can adopt it as metal intermetallic dielectric layer.
And, owing to do not contain fluorine in the high-density oxide layer 303, therefore the oxide layer that need not to resemble prior art needs at first to form Silicon-rich therebetween on metal interconnecting wires 302 and the Semiconductor substrate 301 that exposes is isolated, and spreads in the metal interconnecting wires 302 that corrodes lower floor with the fluorine in the fluorine-containing layer that prevents follow-up formation.
The technology that forms described high-density oxide layer 303 is technology as well known to those skilled in the art, does not add detailed description at this.
Described dielectric layer 305 also comprises not fluorine-containing silicate oxide layer 304, the purpose that forms described not fluorine-containing silicate oxide layer 304 is further to reduce the rough and uneven in surface degree on high-density oxide layer 303 surface, convenient follow-up thinning process can reduce cost simultaneously.Described silicate oxide layer 304 using plasma strengthen CVD and form, because the technology cost of high-density plasma CVD is higher, therefore the high-density oxide layer 303 that adopts this technology to form usually can be very not thick, but adopt comparatively cheap technology to thicken such as plasma enhanced CVD, form silicate oxide layer 304.Can polish by existing polishing technology then, thus the surface of formation substantially flat.
Described silicate oxide layer 304 thickness range be 8000 to
Therefore equally, do not contain fluorine in the mesosilicic acid salt oxide skin(coating) 304 of the present invention, need not to resemble the oxide layer that needs to form earlier Silicon-rich the prior art, to prevent the metal interconnecting wires 302 of the fluorine diffusion corrosion lower floor in the fluorine-containing dielectric layer.
Then,, dielectric layer 305 need be thinned to predetermined thickness, among the present invention, described dielectric layer 305 attenuates be comprised chemical-mechanical polishing step with reference to Fig. 8, the described thickness range that is chemically mechanically polished to dielectric layer be 3500 to
Such as can for
For chemical machinery equipment, its polishing scope for oxide skin(coating) is
Therefore be about when throwing dielectric layer 305 usually
In time, just stopped, and to prevent to throw the device layer that causes destroying lower floor, through polishing, dielectric layer 305 forms dielectric layer 305a.
With reference to Fig. 9, in order further to improve the transmitance of light, need be with the further attenuate of dielectric layer 305a, eat-back described dielectric layer 305a attenuate is also comprised, the described thickness range that is etched back to dielectric layer be 1500 to
Such as can for
Through after eat-backing, dielectric layer 305a forms dielectric layer 305b.
With reference to Figure 10, on the process dielectric layer 305b of attenuate, form anti-reflecting layer 306, described anti-reflecting layer 307 adopts silicon oxynitrides usually, and the thickness range of described anti-reflecting layer 306 is
Then, form second dielectric layer 307 on anti-reflecting layer 306, described second dielectric layer 307 adopts not fluorine-containing silica, absorbs airborne steam so that be absorbed in the photoetching process in the air because anti-reflecting layer 306 is exposed to, and is used to protect anti-reflecting layer 306.The thickness of described second dielectric layer 307 is
The interlayer dielectric layer adopts not fluorine-containing silicate oxide layer 304 among the present invention, need not to resemble the 4th not fluorine-containing oxide layer 208 that forms among Fig. 5 the prior art isolates, though the 4th oxide layer 208 also has the effect of repairing blemish, but because its counter productive of bringing is the thickness that has increased dielectric layer, cause light path elongated, be unfavorable for seeing through of light, its shortcoming is compared with its advantage, shortcoming is greater than advantage, so among the present invention, do not form this layer.Simplified technology like this, cost reduces, and the number of plies reduces, and helps seeing through of light.
The above-mentioned technology of process forms the interlayer dielectric layer in the cmos image sensor of the present invention, with reference to Figure 10, comprising: be positioned at dielectric layer 305b, anti-reflecting layer 306 and second dielectric layer 307 on the Semiconductor substrate 301 successively; Do not contain fluorine in the described dielectric layer 305b.
Described anti-reflecting layer 306 is a silicon oxynitride, and described second dielectric layer 307 is a silica.
Form interlayer dielectric layer of the present invention through above-mentioned technology, the thickness of the dielectric layer 305b of described interlayer dielectric layer only have 1500 to
Compared with prior art, thickness reduces greatly, helps improving the transmitance of light; Simultaneously, because the number of plies is few, stress is little, the cracking phenomena of prior art can not occur.
Simultaneously, the present invention gives the manufacture method of the interconnection structure in a kind of cmos image sensor, comprising: Semiconductor substrate is provided, is formed with discrete interconnect metallization lines on the described Semiconductor substrate; On Semiconductor substrate, form dielectric layer; Dielectric layer is thinned to predetermined thickness; On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer; Same position in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate forms opening and exposes interconnect metallization lines; Filled conductive material in opening; On second dielectric layer, form second interconnect metallization lines facing to aperture position; Do not contain fluorine in the described dielectric layer.
The manufacture method of the interconnection structure in the described cmos image sensor comprises the technology of aforesaid manufacturing interlayer dielectric layer, and concrete technology please refer to Fig. 7 to Figure 10.
Then, please continue, form opening in the dielectric layer 305b behind second dielectric layer 307, anti-reflecting layer 306 and attenuate and expose interconnect metallization lines 302 with reference to Figure 11; Filled conductive material 308 in opening; Form second interconnect metallization lines 309 facing to aperture position on second dielectric layer 307, described second interconnect metallization lines 309 is electrically connected with metal interconnecting wires 302 by electric conducting material 308; Do not contain fluorine in the described dielectric layer 305b.
Then, on second metal interconnecting wires 309 and second dielectric layer 307, form the 3rd dielectric layer 310, described the 3rd dielectric layer 310 does not contain fluorine, with reference to aforementioned same technology, forms second anti-reflecting layer 311 and the 4th dielectric layer 312 successively on the 3rd dielectric layer 310.
In semi-conductive interconnection process, also may comprise more interlayer dielectric layer and metal interconnecting wires layer, only be illustrated at this with double layer of metal and two layers of dielectric layer, should too much not limit protection scope of the present invention at this.
Based on above-mentioned technology, formed the interconnection structure in the cmos image sensor of the present invention, with reference to Figure 11, comprising: be positioned at dielectric layer 305b, anti-reflecting layer 306 and second dielectric layer 307 behind the attenuate on the Semiconductor substrate 301 successively; Be positioned at the opening of the dielectric layer 305b behind second dielectric layer 307, anti-reflecting layer 306 and the attenuate and the electric conducting material 308 that is filled in opening; Be positioned at second metal interconnecting wires 309 on second dielectric layer 307; Be positioned at the 3rd dielectric layer 310, second anti-reflecting layer 311 and the 4th dielectric layer 312 on second metal interconnecting wires 309 and second dielectric layer 307 successively; Do not contain fluorine in described dielectric layer 305b and the 3rd dielectric layer 310.
Interlayer dielectric layer of the present invention adopts not fluorine-containing dielectric layer 305b and the 3rd dielectric layer 310, avoided the fluorine in the fluorine-containing oxide of the employing of prior art to spread easily, need not to increase betwixt that first oxide layer is isolated and the 4th oxide layer is carried out repair-deficiency, the interlayer dielectric layer number of plies that forms is few, simple in structure, and cost is lower; Between layer and the layer reflection of light and scattering are reduced the transmitance height; And because the number of plies is few, the stress of interlayer is less, is not easy to cause cracking phenomena.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (15)
1. the manufacture method of the interlayer dielectric layer in the cmos image sensor comprises:
Semiconductor substrate is provided;
On Semiconductor substrate, form dielectric layer;
Dielectric layer is thinned to predetermined thickness;
On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively;
It is characterized in that, do not contain fluorine in the described dielectric layer.
2. the manufacture method of interlayer dielectric layer according to claim 1, it is characterized in that, described dielectric layer comprises not fluorine-containing high-density oxide layer, described high-density oxide layer adopts the high density plasma CVD device to form, and the thickness range of described high-density oxide layer is 4500 to 6000
3. the manufacture method of interlayer dielectric layer according to claim 2 is characterized in that, described dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the described high-density oxide layer, and the thickness range of described silicate oxide layer is 8000 to 9000
4. the manufacture method of interlayer dielectric layer according to claim 1 is characterized in that, described the dielectric layer attenuate is comprised chemico-mechanical polishing, and the described thickness range that is chemically mechanically polished to dielectric layer is 3500 to 4500
5. according to the manufacture method of claim 1 or 4 described interlayer dielectric layers, it is characterized in that eat-back the described dielectric layer attenuate is also comprised, the described thickness range that is etched back to dielectric layer is 1500 to 2500
6. the manufacture method of interlayer dielectric layer according to claim 1 is characterized in that, described second dielectric layer is a silica, and described anti-reflecting layer is a silicon oxynitride.
7. the manufacture method of interlayer dielectric layer according to claim 1 is characterized in that, also is formed with metal pickup layer and metal interconnecting wires on the described Semiconductor substrate successively, described metal interconnecting wires thickness range be 1800 to
Described metal pickup layer be 100 to
8. one kind as the interlayer dielectric layer in the cmos image sensor of each manufacturing in the claim 1 to 7.
9. the manufacture method of the interconnection structure in the cmos image sensor comprises:
Semiconductor substrate is provided, is formed with metal pickup layer and metal interconnecting wires on the described Semiconductor substrate successively;
On Semiconductor substrate, form dielectric layer;
Dielectric layer is thinned to predetermined thickness;
On the dielectric layer behind the attenuate, form the anti-reflecting layer and second dielectric layer successively;
Form opening in the dielectric layer behind second dielectric layer, anti-reflecting layer and attenuate and expose interconnect metallization lines;
Filled conductive material in opening;
On anti-reflecting layer, form second metal interconnecting wires facing to aperture position;
It is characterized in that, do not contain fluorine in the described dielectric layer.
10. the manufacture method of interconnection structure according to claim 9, it is characterized in that, described dielectric layer comprises not fluorine-containing high-density oxide layer, described high-density oxide layer adopts the high density plasma CVD device to form, the thickness range of described high-density oxide layer be 4500 to
11. the manufacture method of interconnection structure according to claim 10 is characterized in that, described dielectric layer also comprises the not fluorine-containing silicate oxide layer that is positioned on the described high-density oxide layer, the thickness range of described silicate oxide layer be 8000 to
12. the manufacture method of interconnection structure according to claim 11 is characterized in that, described the dielectric layer attenuate is comprised chemico-mechanical polishing, the described thickness range that is chemically mechanically polished to dielectric layer be 3500 to
13. the manufacture method according to claim 9 or 12 described interconnection structures is characterized in that, eat-back the described dielectric layer attenuate is also comprised, the described thickness range that is etched back to dielectric layer be 1500 to
14. the manufacture method of interconnection structure according to claim 9 is characterized in that, described metal interconnecting wires thickness range be 1800 to
Described metal pickup layer be 100 to
15. one kind as the interconnection structure in the cmos image sensor of each manufacturing in the claim 9 to 14.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820256A (en) * | 2011-06-08 | 2012-12-12 | 无锡华润上华半导体有限公司 | Method for preparing inter-metal dielectric layer |
| CN103094194A (en) * | 2011-11-01 | 2013-05-08 | 无锡华润上华科技有限公司 | Forming method of metal inter-lamination dielectric layer and metal inter-lamination dielectric layer |
| CN103247594A (en) * | 2012-02-09 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Stress reduction apparatus |
| CN110828370A (en) * | 2018-08-07 | 2020-02-21 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN113517219A (en) * | 2020-04-09 | 2021-10-19 | 中国科学院微电子研究所 | Method for preventing metal corrosion after metal etching |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006708A (en) * | 2002-03-27 | 2004-01-08 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
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2008
- 2008-11-18 CN CN 200810202961 patent/CN101740473B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820256A (en) * | 2011-06-08 | 2012-12-12 | 无锡华润上华半导体有限公司 | Method for preparing inter-metal dielectric layer |
| CN103094194A (en) * | 2011-11-01 | 2013-05-08 | 无锡华润上华科技有限公司 | Forming method of metal inter-lamination dielectric layer and metal inter-lamination dielectric layer |
| CN103247594A (en) * | 2012-02-09 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Stress reduction apparatus |
| US9373536B2 (en) | 2012-02-09 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus |
| US9865534B2 (en) | 2012-02-09 | 2018-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus |
| US10290576B2 (en) | 2012-02-09 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus with an inverted cup-shaped layer |
| CN110828370A (en) * | 2018-08-07 | 2020-02-21 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN113517219A (en) * | 2020-04-09 | 2021-10-19 | 中国科学院微电子研究所 | Method for preventing metal corrosion after metal etching |
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| CN101740473B (en) | 2012-12-12 |
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