KR20050031302A - Method for forming semiconductor wiring - Google Patents
Method for forming semiconductor wiring Download PDFInfo
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- KR20050031302A KR20050031302A KR1020030067560A KR20030067560A KR20050031302A KR 20050031302 A KR20050031302 A KR 20050031302A KR 1020030067560 A KR1020030067560 A KR 1020030067560A KR 20030067560 A KR20030067560 A KR 20030067560A KR 20050031302 A KR20050031302 A KR 20050031302A
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- forming
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- wiring
- tungsten plug
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체 소자의 제조 방법하는 방법에 관한 것으로서, 보다 상세하게는, 반도체 소자 제조시 절연막 증착하는 방법에 적용할 수 있고, 구리 배선(copper wiring) 공정에 응용할 수 있는 반도체 배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an insulating film during semiconductor device manufacturing, and to a method of forming a semiconductor wiring that can be applied to a copper wiring process. will be.
일반적으로, 단일 대머신(single damascene) 방법을 이용하여 제 1 메탈을 형성하는데, 이때 구리가 채워질 트렌치(trench)를 형성하기 위해서는 반드시 식각 공정이 필요하다. 그러나, 플라즈마 식각시 플라즈마 형성이 불안정할 경우 소자에 플라즈마 손상을(plasma damage)를 유발하게 되어 소자특성을 악화시키는 결과를 초래하게 된다. In general, the first metal is formed using a single damascene method, in which an etching process is necessary to form a trench to be filled with copper. However, if plasma formation is unstable during plasma etching, plasma damage may occur to the device, resulting in deterioration of device characteristics.
또한, 일반적으로 메탈 라인을 형성하기 위하여 트렌치 식각시 낮은 k를 갖는 Si02와 같은 물질로 층간절연막과의 고선택비를 가지는 Si3N4, SiC 등과 같은 물질로 식각 방지막(etch stopping layer)의 형성이 필요하며, 트렌치 식각시 고선택비를 위한 식각조건 설정이 필요하므로 공정이 복잡해지는 난점이 있다.In addition, in order to form a metal line, a material such as Si0 2 having a low k during trench etching and a material such as Si 3 N 4 , SiC, etc. having a high selectivity with an interlayer insulating film, may be used. Formation is required, and the process requires complicated etching conditions for high selectivity when trenching.
더욱이, 트렌치 식각후 텅스텐 플러그를 개방(open) 시키기 위하여 식각 방지막 제거를 위하여 충분히 과식각(over etch)가 필요하며, 이때 텅스텐 플러그 아래로 식각이 이루어 짐으로서 스텝 커버리지(step coverage) 특성이 열화됨으로 후속의 장벽 메탈(barrier metal) 증착을 어렵게 한다. Furthermore, in order to open the tungsten plug after the trench is etched, it is necessary to overetch enough to remove the etch stop layer, and the step coverage characteristic is degraded by etching under the tungsten plug. This makes subsequent barrier metal deposition difficult.
도 1은 종래 기술에 따라 형성된 반도체 배선에서 텅스텐 플러그가 노출되는 현상을 설명하기 위한 단면도를 도시한다. 1 is a cross-sectional view illustrating a phenomenon in which a tungsten plug is exposed in a semiconductor wiring formed according to the prior art.
도 1에 도시한 바와 같이, 반도체 소자는 층간 유전체 층(ILD; inter dielectric layer)(10), ILD 층(10) 내에 형성된 텅스텐 플러그(16), 식각 방지를 위하여 형성된 식각 방지층(12) 및 액상 증착(LPD; liquid phase deposition) 산화막(18)을 포함하며, 참조 번호 16은 텅스텐 플러그가 노출된 모습을 도시한다. As shown in FIG. 1, the semiconductor device includes an inter dielectric layer (ILD) 10, a tungsten plug 16 formed in the ILD layer 10, an etch stop layer 12 formed to prevent etching, and a liquid phase. A liquid phase deposition (LPD) oxide film 18 is shown, with reference numeral 16 showing the tungsten plug exposed.
도 2는 도 1에 도시한 반도체 배선에서 텅스텐 플러그가 노출되는 현상을 설명하기 위하여 SEM 사진으로 촬영한 도면이다. FIG. 2 is a SEM photograph taken to explain a phenomenon in which a tungsten plug is exposed in the semiconductor wiring illustrated in FIG. 1.
도 1 및 도2에 도시한 바와같이, 텅스텐 플러그(16)가 노출되면서 거칠은(tough) 금속 폴리머(WxCyFz....)를 형성함으로 이를 제거하기 위한 추가의 세정(cleaning) 공정 필요하게 되며, 잔유물(residue)이 남겨진 경우에 후속의 장벽 메탈의 증착을 어렵게 하는 문제점이 있다. As shown in Figs. 1 and 2, the tungsten plug 16 is exposed to form a tough metal polymer (WxCyFz ....) which requires an additional cleaning process to remove it. However, there is a problem that it is difficult to deposit subsequent barrier metal in the case where residue is left.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 주목적은 단일 대머신 패턴(single dmascene pattern) 형성 시 플라즈마를 이용하지 않고 상온에서 침적 방법에 의하여 절연막 증착을 하는 선택적 LPD(LPD; liquid phase deposition)를 이용하여 노출된 절연막(SiO2)에만 선택적으로 FSG(fluorinated silica glass) 또는 SiOF로 이루어진 절연막을 증착하고 포토 레지스트가 남아있는 즉, 트렌치 메탈 라인이 형성되는 부분에서는 절연막 성장이 이루어지지 않는 방법을 이용하여 패터닝을 형성함으로서 플라즈마 손상에 대한 우려가 없으므로 소자특성을 개선 할 수 있는 반도체 배선 형성 방법을 제공하는 것이다. The present invention has been made to solve the above problems, and the main object of the present invention is to select a selective LPD (LPD) for depositing an insulating film at room temperature without using plasma when forming a single dmascene pattern. by selectively depositing an insulating film made of fluorinated silica glass (FSG) or SiOF on the exposed insulating film (SiO2) using liquid phase deposition, and growing the insulating film at a portion where the photoresist remains, that is, a trench metal line is formed. There is no concern about plasma damage by forming the patterning by using a method that does not support, thereby providing a semiconductor wiring forming method that can improve the device characteristics.
또한, 본 발명의 다른 목적은 선택적으로 절연막을 증착하여 메탈 라인을 형성함으로서 종래의 단일 대머신 공정에서 사용하는 트렌치 식각시 라인 형성을 위한 식각 방지막을 증착할 필요가 없으므로 공정 단순화를 기대할 수 있는 반도체 배선 형성 방법을 제공하는 것이다. In addition, another object of the present invention is to form a metal line by selectively depositing an insulating film to form a metal line, it is not necessary to deposit an etch stop layer for forming a line during the trench etching used in the conventional single damascene process semiconductor can be expected to simplify the process It is to provide a wiring forming method.
본 발명의 다른 목적은 종래의 식각 방지막 제거를 위한 식각시 텅스텐 플러그 아래로의 식각이 이루어 짐으로서 스텝 커버리지 특성이 열화 및 메탈 라인 상부의 결함(fecet)에 대한 우려가 없으며, 식각 공정에 의한 금속 폴리머(metallic polymer) 형성에 대한 우려가 없으므로 추가의 세정(cleaning) 공정 필요없으므로 공정 단순화에 기여할 수 있는 반도체 배선 형성 방법을 제공하는 것이다. Another object of the present invention is that etching is performed under the tungsten plug during etching to remove the conventional etch barrier layer, there is no concern about deterioration of step coverage characteristics and defects on the upper part of the metal line. Since there is no concern about the formation of a metallic polymer, there is no need for an additional cleaning process, thereby providing a method for forming a semiconductor wiring, which may contribute to the process simplification.
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판 상에 형성된 층간 유전체층 내에 텅스텐 플러그를 형성하는 단계와, 텅스텐 플러그 상에 소정 패턴의 포토레지스트를 형성하는 단계와, 소정 패턴의 포토레지스트 사이에 산화막을 형성하는 단계와, 소정 패턴의 포토레지스트를 제거하는 단계와, 소정 패턴의 포토레지스트가 제거된 영역에 메탈을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 배선 형성 방법을 제공한다. The present invention for achieving the above object is a step of forming a tungsten plug in the interlayer dielectric layer formed on the semiconductor substrate, forming a photoresist of a predetermined pattern on the tungsten plug, and an oxide film between the photoresist of the predetermined pattern And forming a metal in a region where the photoresist of the predetermined pattern has been removed, and forming a metal in a region from which the photoresist of the predetermined pattern has been removed.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.
도 3a 내지 도 3e는 본 발명의 바람직한 실시예에 따른 반도체 배선 형성 방법을 설명하기 위한 단면도들을 도시한다. 3A to 3E are cross-sectional views illustrating a method for forming a semiconductor wiring in accordance with a preferred embodiment of the present invention.
먼저, 도 3a에 도시한 바와 같이, 반도체 소자와 배선간 연결을 위하여 층간절연막(ILD : inter layer dielectric)(100)을 플라즈마 식각을 이용하여 컨택홀(contact hole)을 형성하고, 텅스텐을 화학적 기상 증착(CVD; chemical vapor deposition)방법을 이용하여 증착한 후, 화학적 기계적 연마(CMP; chemical mechanical polishing)방법을 이용하여 텅스텐 플러그(102)를 형성한다.First, as shown in FIG. 3A, a contact hole is formed in the inter layer dielectric (ILD) 100 using plasma etching to connect the semiconductor device and the wiring, and tungsten is formed in a chemical vapor phase. After deposition using a chemical vapor deposition (CVD) method, the tungsten plug 102 is formed using a chemical mechanical polishing (CMP) method.
다음으로, 마스크 오버레이 마진(mask overlay margin) 부족으로 인하여 후속의 액상 증착(LPD; liquid phase deposition) 산화막 증착시 텅스텐 플러그(102)가 노출되어 LPD 산화막 증착시 사용되는 산성 용액에 의한 텅스텐 플러그(102)의 부식을 방지하기 위하여 텅스텐 플러그(102) 표면을 산화시킨다. Next, the tungsten plug 102 is exposed by an acidic solution used for LPD oxide deposition by exposing the tungsten plug 102 during subsequent liquid phase deposition (LPD) oxide deposition due to a lack of mask overlay margin. The surface of the tungsten plug 102 is oxidized to prevent corrosion.
이때, 본 발명의 바람직한 실시예에 따르면, 텅스텐 표면의 산화를 위하여 노(furnace)에서 산소(oxygen) 분위기에서 고온의 400 내지 500 ?? 범위로 유지하여 텅스텐 플러그(102)를 패시베이션(passivation)한다.At this time, according to a preferred embodiment of the present invention, the high temperature 400 ~ 500 ℃ in the oxygen (oxygen) atmosphere in the furnace (furnace) for the oxidation of the tungsten surface Keep in range to passivate the tungsten plug 102.
다음 단계로, 도 3b에 도시한 바와 같이, 포토레지스트(photoresist)(104)를 회전 도포 방법을 이용하여 도포(coating)한다. 본 발명의 바람직한 실시예에 따르면, 이때의 포토레지스트(104) 물질은 후속의 식각공정이 없으므로 식각 선택비가 우수한 물질의 설정이 필요없으며, 포토레지스트(104)의 모서리 거칠기(edge roughness)를 최소화하기 위하여 분자량(molecular weight)가 작은 물질을 사용하며, 이때 포토레지스트(104)의 두께는 상부 메탈 레벨의 절연막 두께 이상으로 4,000 ?? 내지 5,000 ??의 범위로 도포한 후 메탈 배선이 형성될지 지역위에만 포토레지스트(104)가 남도록 마스크 작업을 실시한다. 이때, 텅스텐 플러그(102) 위로 포토레지스트(104)가 남게 된다.Next, as shown in FIG. 3B, the photoresist 104 is coated using a rotary coating method. According to a preferred embodiment of the present invention, since the material of the photoresist 104 at this time does not have a subsequent etching process, it is not necessary to set a material having excellent etching selectivity, and to minimize edge roughness of the photoresist 104. For this purpose, a material having a low molecular weight is used, and the thickness of the photoresist 104 is greater than or equal to the thickness of the insulating film of the upper metal level. After coating in the range of 5,000 to 5,000 degrees, masking is performed so that the photoresist 104 remains only on the region where the metal wiring is to be formed. At this time, the photoresist 104 remains on the tungsten plug 102.
그리고 나서, 도 3c에 도시한 바와 같이, 배선간의 절연막이 증착될 지역에 절연막을 선택적으로 형성하기 위하여 대략 25?? 내지 대략 35 ??의 범위로 과포화된 H3B03(hydrofluosilicic acid)를 첨가한 수용액에 침적하여 포토레지스트(104)가 남아있는 즉, 상부메탈이 형성되는 부분에서는 절연막(SiO2)성장이 이루어지지 않고, 노출된 지역에서만 선택적으로 절연막(SiO2)이 성장하는 선택적 LPD방법을 이용하여 선택적으로 LPD 산화막(106)을 증착한다. 이때, 본 발명의 바람직한 실시예에 따르면, 증착 두께는 대략 3,000 ?? 내지 4,000 ?? 정도로 증착하는 것이 바람직하다.Then, as shown in Fig. 3C, in order to selectively form the insulating film in the region where the insulating film between the wires is to be deposited, approximately 25 ?? The photoresist 104 remains after being deposited in an aqueous solution containing H 3 B0 3 (hydrofluosilicic acid) supersaturated in the range of about 35 ° to about 35 °. Instead, the LPD oxide layer 106 is selectively deposited using the selective LPD method in which the insulating film SiO 2 is selectively grown only in the exposed region. At this time, according to a preferred embodiment of the present invention, the deposition thickness is about 3,000 ?? To 4,000 ?? It is preferable to deposit to the extent.
이때, 실리콘 이산화막의 LPD의 매커니즘은 다음과 같다. At this time, the mechanism of the LPD of the silicon dioxide film is as follows.
H2SiF6 + 2H2O ?? SiO2 + HFH 2 SiF 6 + 2H 2 O ?? SiO 2 + HF
따라서, H2SiF6(hydrofluosilicic acid) 수용액에서 SiO2가 증착되고, SiO 2와 포토레지스트를 식각하는 HF가 발생되는데, 이 HF를 분해하기 위하여 H3BO3(boric acid)를 대략 20 % 내지 대략 30% 정도 첨가하여 다음과 같은 반응에 의해 포토레지스트의 선택비 및 증착 속도를 높인다.Therefore, SiO 2 is deposited in an aqueous H 2 SiF 6 (hydrofluosilicic acid) solution, and HF is formed to etch SiO 2 and photoresist. In order to decompose HF, H 3 BO 3 (boric acid) is approximately 20% to Add about 30% to increase the selectivity and deposition rate of the photoresist by the following reaction.
H3BO3 + 4HF ?? BF4 + H3O+ + 2H2OH 3 BO 3 + 4HF ?? BF 4 + H 3 O + + 2H 2 O
이어서, 도 3d에 도시한 바와 같이, O2 플라즈마를 이용하여 포토레지스트(104)를 제거한다. 이때, 본 발명의 바람직한 실시예에 따르면, O2 제거(strip)시 발생되는 스퍼터링 현상을 최소화하기 위하여 고압에서 바이어스 파워(bias power)가 없는 조건으로 진행하는 것이 바람직하다. 또한, O2 제거 조건의 압력은 대략 1,000 내지 1, 500 mT의 범위인 것이 바람직하며, 소오스 파워(source power)는 1,800 내지 2,000 와트를, 가스 흐름은 O2가 대략 200 내지 대략 300 sccm의 범위로 진행되도록 하는 것이 바람직하다.Next, as shown in FIG. 3D, the photoresist 104 is removed using an O 2 plasma. At this time, according to a preferred embodiment of the present invention, in order to minimize the sputtering phenomenon generated during O 2 strip (strip), it is preferable to proceed in a condition that there is no bias power (bias power) at high pressure. In addition, the pressure of the O 2 removal conditions is preferably in the range of approximately 1,000 to 1,500 mT, the source power of 1,800 to 2,000 watts, the gas flow range of approximately 200 to approximately 300 sccm O 2 It is desirable to proceed to.
마지막으로, 도 3e에 도시한 바와 같이, 장벽 메탈(barrier metal) 증착전에 스퍼터링을 통하여 텅스텐 플러그(102) 위로 형성된 산화막(106)을 제거한 후, 장벽 및 구리 시드층을 증착하고 전해도금(electroplating) 방법을 이용하여 Cu로 이루어진 메탈층(108)을 증착한 후, Cu CMP를 실시하여 단일 대머신 패턴을 형성한다. Finally, as shown in FIG. 3E, the oxide film 106 formed on the tungsten plug 102 is removed by sputtering before deposition of the barrier metal, and then the barrier and copper seed layers are deposited and electroplated. After depositing the metal layer 108 made of Cu using the method, Cu CMP is performed to form a single damascene pattern.
상기와 같이, 본 발명은 식각 공정이 없으므로 플라즈마 손상(plasma damage)에 대한 우려가 없으므로 소자특성을 개선할 수 있는 효과가 있다.As described above, since the present invention does not have an etching process, there is no concern about plasma damage, thereby improving the device characteristics.
또한, 본 발명은 선택적으로 절연막을 증착하여 메탈 라인을 형성함으로써 종래의 단일 대머신 공정에서 사용하는 트렌치 식각 라인 형성을 위한 식각 방지막을 증착할 필요가 없으므로 공정 단순화를 기대할 수 있는 효과가 있다.In addition, since the present invention selectively forms an insulating film to form a metal line, it is not necessary to deposit an etch stop layer for forming a trench etch line used in a conventional single damascene process.
더욱이, 본 발명은 선택적으로 절연막을 증착하여 메탈 라인을 형성함으로써, 식각에 의한 텅스텐 플러그와 절연막 간의 스텝 커버리지(step coverage) 특성이 열화 및 메탈 라인 상부의 결함(Fecet)에 대한 우려가 없으므로, 식각 공정에 의한 메탈 폴리머의 형성에 대한 우려가 없으므로 추가의 세정 공정 필요없으므로 공정 단순화에 기여할 수 있는 효과가 있다. Furthermore, the present invention selectively forms an insulating film to form a metal line, so that the step coverage characteristic between the tungsten plug and the insulating layer due to etching is not deteriorated and there is no concern about the defects on the upper metal line. Since there is no concern about the formation of the metal polymer by the process, there is no need for an additional cleaning process, and thus there is an effect that can contribute to the process simplification.
본 발명을 본 명세서 내에서 몇몇 바람직한 실시예에 따라 기술하였으나, 당업자라면 첨부한 특허 청구 범위에서 개시된 본 발명의 진정한 범주 및 사상으로부터 벗어나지 않고 많은 변형 및 향상이 이루어질 수 있다는 것을 알 수 있을 것이다. While the invention has been described in accordance with some preferred embodiments herein, those skilled in the art will recognize that many modifications and improvements can be made without departing from the true scope and spirit of the invention as set forth in the appended claims.
도 1은 종래 기술에 따라 형성된 반도체 배선에서 텅스텐 플러그가 노출되는 현상을 설명하기 위한 단면도를 도시한다. 1 is a cross-sectional view illustrating a phenomenon in which a tungsten plug is exposed in a semiconductor wiring formed according to the prior art.
도 2는 도 1에 도시한 반도체 배선에서 텅스텐 플러그가 노출되는 현상을 설명하기 위하여 SEM 사진으로 촬영한 도면이다. FIG. 2 is a SEM photograph taken to explain a phenomenon in which a tungsten plug is exposed in the semiconductor wiring illustrated in FIG. 1.
도 3a 내지 도 3e는 본 발명의 바람직한 실시예에 따른 반도체 배선 형성 방법을 설명하기 위한 단면도들을 도시한다. 3A to 3E are cross-sectional views illustrating a method for forming a semiconductor wiring in accordance with a preferred embodiment of the present invention.
- 도면의 주요부분에 대한 부호의 설명 - -Explanation of symbols for the main parts of the drawings-
100 : 층간 유전체 층 102 : 텅스텐 플러그100: interlayer dielectric layer 102: tungsten plug
104 : 포토레지스트 층 106 : LPD 산화막 104: photoresist layer 106: LPD oxide film
108 : 금속층 108: metal layer
Claims (10)
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| KR1020030067560A KR20050031302A (en) | 2003-09-29 | 2003-09-29 | Method for forming semiconductor wiring |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766704B1 (en) * | 2005-09-28 | 2007-10-11 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
| KR100790237B1 (en) * | 2005-12-29 | 2008-01-02 | 매그나칩 반도체 유한회사 | Method for fabricating the same of cmos image sensor in metal layer |
| US10510658B2 (en) | 2017-12-07 | 2019-12-17 | Samsung Electronics Co., Ltd. | Semiconductor devices |
-
2003
- 2003-09-29 KR KR1020030067560A patent/KR20050031302A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766704B1 (en) * | 2005-09-28 | 2007-10-11 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
| KR100790237B1 (en) * | 2005-12-29 | 2008-01-02 | 매그나칩 반도체 유한회사 | Method for fabricating the same of cmos image sensor in metal layer |
| US7678688B2 (en) | 2005-12-29 | 2010-03-16 | Kyeong-Keun Choi | Method for forming metal interconnection in image sensor |
| US10510658B2 (en) | 2017-12-07 | 2019-12-17 | Samsung Electronics Co., Ltd. | Semiconductor devices |
| US10847454B2 (en) | 2017-12-07 | 2020-11-24 | Samsung Electronics Co., Ltd. | Semiconductor devices |
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