CN113507285B - Low-voltage high-speed bidirectional logic level conversion circuit - Google Patents

Low-voltage high-speed bidirectional logic level conversion circuit Download PDF

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CN113507285B
CN113507285B CN202110790198.8A CN202110790198A CN113507285B CN 113507285 B CN113507285 B CN 113507285B CN 202110790198 A CN202110790198 A CN 202110790198A CN 113507285 B CN113507285 B CN 113507285B
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gate
level
signal
level conversion
low
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CN113507285A (en
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许超
常伟
李珂
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a low-voltage high-speed bidirectional logic level conversion circuit, which belongs to the field of signal level conversion and comprises a first level conversion module, a second level conversion module, an acceleration signal generation module,The first PMOS tube P1 and the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2. The first level conversion module converts the A-side low voltage into the Y-side high voltage and generates a signal V A The method comprises the steps of carrying out a first treatment on the surface of the The second level conversion module converts the high voltage on the Y side into the low voltage on the A side and generates a signal V Y The method comprises the steps of carrying out a first treatment on the surface of the The acceleration signal generating module receives the signal V A And V Y Generating a short pulse at a rising edge and a falling edge of an input signal, respectively; the first PMOS tube P1 and the second PMOS tube P2 receive low-level short pulse Y at the rising edge of the input signal A1 And Y A2 Accelerating the charging of the capacitor; the first NMOS tube N1 and the second NMOS tube N2 receive high-level short pulse Y at the falling edge of the input signal B1 And Y B2 Accelerating the discharge of the capacitor.

Description

Low-voltage high-speed bidirectional logic level conversion circuit
Technical Field
The invention relates to the technical field of signal level conversion, in particular to a low-voltage high-speed bidirectional logic level conversion circuit.
Background
Level shifting circuits are widely used in multi-voltage digital systems, serial interfaces, and communication devices. As process nodes develop to deep submicron, circuit operating voltages are lower and data transmission speeds are faster. The existing level conversion circuit has high working voltage and low data transmission speed, and cannot meet the requirements of low power consumption and high speed of a modern electronic system.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a low-voltage high-speed bidirectional logic level conversion circuit which can be applied to data transmission between low-power consumption high-speed systems, can not only meet bidirectional level conversion, but also has wide conversion level range.
In order to solve the above technical problems, the present invention provides a low voltage high speed bidirectional logic level conversion circuit, which is powered by dual power sources, and includes:
a first level conversion module for converting the A-side low voltage into the Y-side high voltage and generating a signal V A ；
A second level conversion module for converting the high voltage of the Y side into the low voltage of the A side and generating a signal V Y ；
Acceleration signal generating module for receiving signal V A And V Y Generating a short pulse at a rising edge and a falling edge of an input signal, respectively;
a first PMOS tube P1 and a second PMOS tube P2 for receiving low-level short pulse Y at the rising edge of the input signal A1 And Y A2 Accelerating the charging of the capacitor;
a first NMOS tube N1 and a second NMOS tube N2 for receiving high-level short pulse Y at the falling edge of the input signal B1 And Y B2 Accelerating the discharge of the capacitor.
Optionally, the acceleration signal generating module comprises NAND gates Y1-Y3, OR gate H1, NOT gates F1-F7 and buffers INV 1-INV 2;
the output end of the AND gate Y2 is connected with the input ends of the NOT gates F3 and F4, and the output end of the NOT gate F1 is connected with the input end of the AND gate Y2;
the output end of the AND gate Y3 is connected with the input ends of the NOT gates F6 and F7, and the output end of the OR gate H1 is connected with the input end of the AND gate Y3;
the two input ends of the NAND gate Y1 and the OR gate H1 respectively input a signal V A Sum signal V Y On the rising edge of the input signal, the NOT gates F6 and F7 generate low-level pulses Y, respectively A1 And Y A2 On the falling edge of the input signal, the NOT gates F3 and F4 generate a high level pulse Y B1 And Y B2 。
Optionally, capacitors C1 and C2 are further connected in parallel between the output end of the not gate F2 and the input end of the buffer INV1, and the width of the high-level pulse is adjusted by adjusting the values of the capacitors C1 and C2;
capacitors C3 and C4 are connected in parallel between the output end of the NOT gate F5 and the input end of the buffer INV2, and the width of the low-level pulse is adjusted by adjusting the values of the capacitors C3 and C4.
Optionally, the acceleration signal generating module is controlled by an enable signal EN, the enable signal EN is connected to the input ends of the and gates Y2 and Y3, when the enable signal EN is high, the acceleration signal generating module works normally, and when the enable signal EN is low, the output signal of the acceleration signal generating module is at a low level.
Optionally, the first level conversion module includes a nand gate Y4, a PMOS transistor P3, a level conversion module, not gates F8 to F11, a buffer INV3, and a resistor R1;
the NAND gate Y4, the NOT gate F8, the level conversion module, the NOT gate F9, the NOT gate F10, the NOT gate F11 and the resistor R1 are sequentially connected in series, the drain electrode of the PMOS tube P3 is connected with the input end of the NOT gate F8, and the grid electrode is connected with the output end of the NOT gate F8; the output end of the level conversion module is connected with the input end of the buffer INV 3;
the input end of the NAND gate Y4 inputs the A-side low voltage, and the output end of the buffer INV3 outputs the signal V A The method comprises the steps of carrying out a first treatment on the surface of the The first level conversion module is controlled by an enable signal EN, when EN is in a high level, the first level conversion module works normally, when EN is in a low level, the Y side is rapidly pulled down to be in a low level through a resistor R1, and the first level conversion module is in a high resistance state.
Optionally, the second level conversion module includes a nand gate Y5, a PMOS transistor P4, not gates F12 to F14, a buffer INV4, and a resistor R2;
the NAND gate Y5, the NOT gate F12, the NOT gate F13, the NOT gate F14 and the resistor R2 are sequentially connected, the grid electrode of the PMOS tube P4 is connected with the output end of the NOT gate F12, and the drain electrode is connected with the output end of the NOT gate F12; the input end of the buffer INV4 is connected with the output end of the NOT gate F12;
the input end of the NAND gate Y5 inputs the Y-side low voltage, and the output end of the buffer INV4 outputs V B The method comprises the steps of carrying out a first treatment on the surface of the The second level conversion module is controlled by an enable signal EN, when EN is in a high level, the second level conversion module works normally, when EN is in a low level, the A side is rapidly pulled down to be in a low level through a resistor R2, and the second level conversion module is in a high resistance state.
The low-voltage high-speed bidirectional logic level conversion circuit comprises a first level conversion module, a second level conversion module, an acceleration signal generation module, a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1 and a second NMOS tube N2. The first level conversion module converts the A-side low voltage into the Y-side high voltage and generates a signal V A The method comprises the steps of carrying out a first treatment on the surface of the The second level conversion module converts the high voltage on the Y side into the low voltage on the A side and generates a signal V Y The method comprises the steps of carrying out a first treatment on the surface of the The acceleration signal generating module receives the signal V A And V Y Generating a short pulse at a rising edge and a falling edge of an input signal, respectively; the first PMOS tube P1 and the second PMOS tube P2 receive low-level short pulse Y at the rising edge of the input signal A1 And Y A2 Accelerating the charging of the capacitor; the first NMOS tube N1 and the second NMOS tube N2 receive high-level short pulse Y at the falling edge of the input signal B1 And Y B2 Accelerating the discharge of the capacitor.
The invention has the following beneficial effects:
(1) The internal structure of the invention is composed of basic digital logic gates such as an inverter, has lower power consumption and can work in a wider voltage range
(2) The invention adopts the acceleration module, can be conducted on the rising edge and the falling edge of the signal, accelerates the charge and discharge of the capacitor, accelerates the data transmission, and is suitable for a high-speed signal transmission system.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a low voltage high speed bi-directional logic level conversion circuit provided by the present invention;
FIG. 2 is a schematic diagram of a block diagram illustrating an acceleration signal generation module in a low voltage high speed bi-directional logic level shifter circuit;
FIG. 3 is a schematic diagram of a first level shifter module in a low voltage high speed bidirectional logic level shifter circuit;
fig. 4 is a schematic diagram of a second level shifter module in the low voltage high speed bidirectional logic level shifter circuit.
Detailed Description
The following describes a low voltage high speed bi-directional logic level conversion circuit according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
The invention provides a low-voltage high-speed bidirectional logic level conversion circuit, the structure of which is shown in figure 1,the low-voltage high-speed bidirectional logic level conversion circuit is powered by a dual power supply and comprises a first level conversion module, a second level conversion module, an acceleration signal generation module, a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1 and a second NMOS tube N2. The first level conversion module converts the A-side low voltage into the Y-side high voltage and generates a signal V A The method comprises the steps of carrying out a first treatment on the surface of the The second level conversion module converts the high voltage on the Y side into the low voltage on the A side and generates a signal V Y The method comprises the steps of carrying out a first treatment on the surface of the The acceleration signal generating module receives the signal V A And V Y Generating a short pulse at a rising edge and a falling edge of an input signal, respectively; the first PMOS tube P1 and the second PMOS tube P2 receive low-level short pulse Y at the rising edge of the input signal A1 And Y A2 Accelerating the charging of the capacitor; the first NMOS tube N1 and the second NMOS tube N2 receive high-level short pulse Y at the falling edge of the input signal B1 And Y B2 Accelerating the discharge of the capacitor.
As shown in FIG. 2, the acceleration signal generating module comprises NAND gates Y1-Y3, OR gate H1, NOT gates F1-F7, and buffers INV 1-INV 2; the output end of the AND gate Y2 is connected with the input ends of the NOT gates F3 and F4, and the output end of the NOT gate F1 is connected with the input end of the AND gate Y2; the output end of the AND gate Y3 is connected with the input ends of the NOT gates F6 and F7, and the output end of the OR gate H1 is connected with the input end of the AND gate Y3; the two input ends of the NAND gate Y1 and the OR gate H1 respectively input a signal V A Sum signal V Y On the rising edge of the input signal, the NOT gates F6 and F7 generate low-level pulses Y, respectively A1 And Y A2 On the falling edge of the input signal, the NOT gates F3 and F4 generate a high level pulse Y B1 And Y B2 。
Capacitors C1 and C2 are connected in parallel between the output end of the NOT gate F2 and the input end of the buffer INV1, and the width of the high-level pulse is adjusted by adjusting the values of the capacitors C1 and C2; capacitors C3 and C4 are connected in parallel between the output end of the NOT gate F5 and the input end of the buffer INV2, and the width of the low-level pulse is adjusted by adjusting the values of the capacitors C3 and C4. The acceleration signal generating module is controlled by an enable signal EN, the enable signal EN is connected to the input ends of the AND gates Y2 and Y3, when the enable signal EN is high, the acceleration signal generating module works normally, and when the enable signal EN is low, the output signal of the acceleration signal generating module is in a normal low level.
As shown in FIG. 3, the first level conversion module includes a NAND gate Y4, a PMOS tube P3, a level conversion module, NOT gates F8-F11, a buffer INV3 and a resistor R1; the NAND gate Y4, the NOT gate F8, the level conversion module, the NOT gate F9, the NOT gate F10, the NOT gate F11 and the resistor R1 are sequentially connected in series, the drain electrode of the PMOS tube P3 is connected with the input end of the NOT gate F8, and the grid electrode is connected with the output end of the NOT gate F8; the output end of the level conversion module is connected with the input end of the buffer INV 3; the input end of the NAND gate Y4 inputs the A-side low voltage, and the output end of the buffer INV3 outputs the signal V A . The left half of the dashed line in fig. 3 is supplied with low voltage and the right half with high voltage. The first level conversion module is controlled by an enable signal EN, when EN is in a high level, the first level conversion module works normally, when EN is in a low level, the Y side is rapidly pulled down to be in a low level through a resistor R1, and the first level conversion module is in a high resistance state.
As shown in fig. 4, the second level conversion module includes a nand gate Y5, a PMOS transistor P4, not gates F12 to F14, a buffer INV4, and a resistor R2; the NAND gate Y5, the NOT gate F12, the NOT gate F13, the NOT gate F14 and the resistor R2 are sequentially connected, the grid electrode of the PMOS tube P4 is connected with the output end of the NOT gate F12, and the drain electrode is connected with the output end of the NOT gate F12; the input end of the buffer INV4 is connected with the output end of the NOT gate F12; the input end of the NAND gate Y5 inputs the Y-side low voltage, and the output end of the buffer INV4 outputs V B . The left half of the dashed line in fig. 4 is supplied with low voltage and the right half with high voltage. The second level conversion module is controlled by an enable signal EN, when EN is in a high level, the second level conversion module works normally, when EN is in a low level, the A side is rapidly pulled down to be in a low level through a resistor R2, and the second level conversion module is in a high resistance state.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (4)

1. A low voltage high speed bi-directional logic level conversion circuit powered by a dual power supply, the low voltage high speed bi-directional logic level conversion circuit comprising:
a first level conversion module for converting the A-side low voltage into the Y-side high voltage and generating a signal V A ；
A second level conversion module for converting the high voltage of the Y side into the low voltage of the A side and generating a signal V Y ；
Acceleration signal generating module for receiving signal V A And V Y Generating a short pulse at a rising edge and a falling edge of an input signal, respectively;
a first PMOS tube P1 and a second PMOS tube P2 for receiving low-level short pulse Y at the rising edge of the input signal A1 And Y A2 Accelerating the charging of the capacitor;
a first NMOS tube N1 and a second NMOS tube N2 for receiving high-level short pulse Y at the falling edge of the input signal B1 And Y B2 Accelerating the discharge of the capacitor;
the acceleration signal generation module comprises NAND gates Y1-Y3, OR gate H1, NOT gates F1-F7 and buffers INV 1-INV 2;
the output end of the AND gate Y2 is connected with the input ends of the NOT gates F3 and F4, and the output end of the NOT gate F1 is connected with the input end of the AND gate Y2;
the output end of the AND gate Y3 is connected with the input ends of the NOT gates F6 and F7, and the output end of the OR gate H1 is connected with the input end of the AND gate Y3;
the two input ends of the NAND gate Y1 and the OR gate H1 respectively input a signal V A Sum signal V Y On the rising edge of the input signal, the NOT gates F6 and F7 generate low-level pulses Y, respectively A1 And Y A2 On the falling edge of the input signal, the NOT gates F3 and F4 generate a high level pulse Y B1 And Y B2 ；
The acceleration signal generating module is controlled by an enable signal EN, the enable signal EN is connected to the input ends of the AND gates Y2 and Y3, when the enable signal EN is high, the acceleration signal generating module works normally, and when the enable signal EN is low, the output signal of the acceleration signal generating module is in a normal low level.
2. The low voltage high speed bi-directional logic level conversion circuit according to claim 1, wherein capacitors C1 and C2 are further connected in parallel between the output end of the not gate F2 and the input end of the buffer INV1, and the width of the high level pulse is adjusted by adjusting the values of the capacitors C1 and C2;
capacitors C3 and C4 are connected in parallel between the output end of the NOT gate F5 and the input end of the buffer INV2, and the width of the low-level pulse is adjusted by adjusting the values of the capacitors C3 and C4.
3. The low voltage high speed bi-directional logic level shift circuit of claim 1, wherein said first level shift module comprises a nand gate Y4, a PMOS transistor P3, a level shift module, not gates F8-F11, a buffer INV3, and a resistor R1;
the NAND gate Y4, the NOT gate F8, the level conversion module, the NOT gate F9, the NOT gate F10, the NOT gate F11 and the resistor R1 are sequentially connected in series, the drain electrode of the PMOS tube P3 is connected with the input end of the NOT gate F8, and the grid electrode is connected with the output end of the NOT gate F8; the output end of the level conversion module is connected with the input end of the buffer INV 3;
the input end of the NAND gate Y4 inputs the A-side low voltage, and the output end of the buffer INV3 outputs the signal V A The method comprises the steps of carrying out a first treatment on the surface of the The first level conversion module is controlled by an enable signal EN, when EN is in a high level, the first level conversion module works normally, when EN is in a low level, the Y side is rapidly pulled down to be in a low level through a resistor R1, and the first level conversion module is in a high resistance state.
4. The low voltage high speed bi-directional logic level shift circuit of claim 1, wherein said second level shift module comprises a nand gate Y5, a PMOS transistor P4, not gates F12-F14, a buffer INV4, and a resistor R2;
the NAND gate Y5, the NOT gate F12, the NOT gate F13, the NOT gate F14 and the resistor R2 are sequentially connected, the grid electrode of the PMOS tube P4 is connected with the output end of the NOT gate F12, and the drain electrode is connected with the output end of the NOT gate F12; the input end of the buffer INV4 is connected with the output end of the NOT gate F12;
the input end of the NAND gate Y5 inputs the Y-side low voltage, and the output end of the buffer INV4 outputs V B The method comprises the steps of carrying out a first treatment on the surface of the The second level conversion module is controlled by an enable signal EN, when EN is in a high level, the second level conversion module works normally, when EN is in a low level, the A side is rapidly pulled down to be in a low level through a resistor R2, and the second level conversion module is in a high resistance state.
CN202110790198.8A 2021-07-13 2021-07-13 Low-voltage high-speed bidirectional logic level conversion circuit Active CN113507285B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110138359A (en) * 2019-05-20 2019-08-16 上海艾为电子技术股份有限公司 Pulse generation circuit and level shifting circuit
CN111817705A (en) * 2020-07-27 2020-10-23 中国电子科技集团公司第五十八研究所 Self-induction self-acceleration bidirectional level conversion circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110138359A (en) * 2019-05-20 2019-08-16 上海艾为电子技术股份有限公司 Pulse generation circuit and level shifting circuit
CN111817705A (en) * 2020-07-27 2020-10-23 中国电子科技集团公司第五十八研究所 Self-induction self-acceleration bidirectional level conversion circuit

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