CN115544935B - Multi-level output serial interface transmitting end driving device - Google Patents

Multi-level output serial interface transmitting end driving device Download PDF

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CN115544935B
CN115544935B CN202211286939.XA CN202211286939A CN115544935B CN 115544935 B CN115544935 B CN 115544935B CN 202211286939 A CN202211286939 A CN 202211286939A CN 115544935 B CN115544935 B CN 115544935B
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stage
auxiliary
driving
tube array
driving units
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CN115544935A (en
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龙爽
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Beijing Chaomo Technology Co ltd
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Beijing Chaomo Technology Co ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/373—Design optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention provides a serial interface transmitting end driving device with multiple level outputs, which comprises: the device comprises a data signal processing unit, a plurality of front stage P auxiliary driving units, a plurality of front stage N auxiliary driving units, a plurality of driving stages, a plurality of front stage P driving units, a plurality of front stage N driving units and a plurality of auxiliary driving stages; the output end of the data signal processing unit is connected with a plurality of front-stage P auxiliary driving units, a plurality of front-stage N auxiliary driving units, a plurality of front-stage P driving units and a front-stage N driving unit; the output ends of the plurality of front-stage P auxiliary driving units and the plurality of front-stage N auxiliary driving units are respectively connected with the plurality of driving stages; and the output ends of the front-stage P driving unit and the front-stage N driving unit are respectively connected with the auxiliary driving stage. The setting of gear can be greatly reduced, the level value of the intermediate level V10-V01 is stabilized near VTHP and VDD-VTHN, the design of a driving stage is greatly simplified, and the power consumption is low, and the power consumption is small.

Description

Multi-level output serial interface transmitting end driving device
Technical Field
The invention relates to the field of analog integrated circuit design, in particular to a serial interface transmitting end driving device with multiple level outputs.
Background
With the development of the semiconductor industry, particularly in the development of transmission interfaces, the requirement on the transmission rate is increasing, and a high-speed serial interface is becoming the mainstream of a new generation of high-speed interfaces instead of the traditional parallel transmission. A conventional universal serial interface such as PCI-Express (peripheral component interconnect express), differential pressure signal LVDS (Low Voltage Differential Signal). The transmitting end driving device is a part directly connected with the package, and the output level of the transmitting end driving device can be a high-low two-value level (non-return-to-zero code NRZ) or a four-level pulse amplitude modulation PAM4; in contrast to these two techniques, the NRZ signal uses high and low signal levels to represent 1 and 0 of the digital logic signal, and can transmit 1bit of logic information every clock cycle. The PAM4 signal uses 4 different signal levels for signal transmission, and each clock cycle can transmit 2 bits of logic information, namely 00, 01, 10 and 11. Therefore, under the same baud rate condition, the PAM4 signal bit rate is 2 times that of the NRZ signal, so that the transmission efficiency is doubled, and the attention is paid.
The output of the transmitting end driving stage device of the conventional NRZ and PAM4 serial interfaces is generally combined by adopting a plurality of driving stages with different driving strengths to finally combine 2 or 4 different signal levels, and the driving stage device has the advantages of more required driving stages, complex control and larger power consumption area.
Disclosure of Invention
The present invention has been made in view of the above problems, and has as its object to provide a multi-level output serial interface transmitting end driving apparatus which overcomes or at least partially solves the above problems.
According to an aspect of the present invention, there is provided a serial interface transmitting end driving apparatus for multi-level output, comprising:
the device comprises a data signal processing unit, a plurality of front stage P auxiliary driving units, a plurality of front stage N auxiliary driving units, a plurality of driving stages, a plurality of front stage P driving units, a plurality of front stage N driving units and a plurality of auxiliary driving stages;
the output end of the data signal processing unit is connected with a plurality of front-stage P auxiliary driving units, a plurality of front-stage N auxiliary driving units, a plurality of front-stage P driving units and a front-stage N driving unit;
the output ends of the plurality of front-stage P auxiliary driving units and the plurality of front-stage N auxiliary driving units are respectively connected with the plurality of driving stages;
and the output ends of the front-stage P driving unit and the front-stage N driving unit are respectively connected with the auxiliary driving stage.
Optionally, the driving stage specifically includes: the first auxiliary PMOS tube array and the first auxiliary NMOS tube array; the first auxiliary PMOS tube array is composed of n PMOS tubes with different sizes, and the first auxiliary NMOS tube array is composed of n NMOS tubes with different sizes;
the grid electrode of the first auxiliary PMOS tube array is connected with the front-stage P auxiliary driving unit;
the drain electrode of the first auxiliary PMOS tube array is connected with a power supply, the source electrode of the first auxiliary PMOS tube array is connected with the drain electrode of the first auxiliary NMOS tube, the grid electrode of the first auxiliary NMOS tube array is connected with the front-stage N driving unit, and the source electrode of the first auxiliary NMOS tube array is connected with a ground wire.
Optionally, the auxiliary driving stage specifically includes: the second NMOS tube array and the second PMOS tube array; the second NMOS tube array is provided with n NMOS tubes with different sizes, and the second PMOS tube array is provided with n PMOS tubes with different sizes;
the drain electrode of the second NMOS tube array is connected with a power supply, the grid electrode of the second NMOS tube array is connected with the front-stage P driving unit, and the source electrode of the second NMOS tube array is connected with the drain electrode of the second PMOS tube array;
the front-stage N driving unit is connected with the grid electrode of the second PMOS tube array, and the source electrode of the second PMOS tube array is connected with the ground wire.
Optionally, the data signal processing unit specifically includes: the device comprises a data phase delay module, a high-speed data multiplexing array, a data weight control module and a high-speed multiphase clock generating device;
the data phase delay module is used for inputting low-speed N-bit data;
the data weight control module is connected with the data phase delay module;
the data phase delay module sends N-bit data with different delay phases to the high-speed data multiplexing array;
the high-speed multi-phase clock generating device sends multi-phase clock signals to the high-speed data multiplexing array;
the high-speed data multiplexing array outputs an n-bit auxiliary PMOS weight signal, an n-bit auxiliary NMOS weight signal, a k-bit NMOS weight signal, and a k-bit PMOS weight signal.
The invention provides a serial interface transmitting end driving device with multiple level outputs, which comprises: the device comprises a data signal processing unit, a plurality of front stage P auxiliary driving units, a plurality of front stage N auxiliary driving units, a plurality of driving stages, a plurality of front stage P driving units, a plurality of front stage N driving units and a plurality of auxiliary driving stages; the output end of the data signal processing unit is connected with a plurality of front-stage P auxiliary driving units, a plurality of front-stage N auxiliary driving units, a plurality of front-stage P driving units and a front-stage N driving unit; the output ends of the plurality of front-stage P auxiliary driving units and the plurality of front-stage N auxiliary driving units are respectively connected with the plurality of driving stages; and the output ends of the front-stage P driving unit and the front-stage N driving unit are respectively connected with the auxiliary driving stage. The setting of gear can be greatly reduced, the level value of the intermediate level V10V 01 is stabilized near VTHP and VDD-VTHN, the design of a driving stage is greatly simplified, and the power consumption is low, and the area is small.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a structure of a driving device for a serial interface transmitting end with multiple level outputs according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a data signal processing unit according to an embodiment of the present invention;
fig. 3 is an input/output schematic diagram of a pre-stage P driving unit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a PAM4 output system provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the generation of a V11 state according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the generation of an intermediate state V01 according to an embodiment of the present invention;
fig. 7 is a schematic diagram of intermediate state V10 state generation according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terms "comprising" and "having" and any variations thereof in the description embodiments of the invention and in the claims and drawings are intended to cover a non-exclusive inclusion, such as a series of steps or elements.
The technical scheme of the invention is further described in detail below with reference to the accompanying drawings and the examples.
As shown in fig. 1, in order to solve the problems of the conventional serial interface transmitting end driving device, the scheme adopts a serial interface transmitting end driving device with multiple level outputs as shown in fig. 1, which comprises a data signal processing unit, a front-stage P driving unit 1,2..n, and a front-stage N
The driving units 1,2..n, the front auxiliary P driving units 1,2..n, the front auxiliary N driving units 1,2..n, the 1,2..n groups of driving stages and the 1,2..k groups of auxiliary driving stages.
The data signal processing unit is shown in fig. 2 and consists of a data phase delay module, a high-speed data multiplexing array, a data weight control module and a high-speed multiphase clock generating device; the data phase delay module is used for generating different delays for each bit signal of the input N-bit data signals and generating N-bit data with different delay phases; the high-speed multi-phase clock generating device can generate multi-path clock signals with equal phase difference for high-speed data multiplexing array, and the data weight control module controls effective information.
As shown in fig. 3, the front-stage P driving unit 1,2..n, the front-stage N driving unit 1,2..n, the front-stage auxiliary P driving unit 1,2..n, and the front-stage auxiliary N driving unit 1,2..n may each be composed of an inverter chain to which m input/output strings are connected.
The output level of the serial interface transmitting end driving device with various level outputs can be adjusted, and a PAM4 output system is used for illustration, as shown in fig. 4, four levels V00, V01, V10 and V11 of PAM4 output represent four states of 2 bits respectively;
the V00 state generation may be at the same time, with the n-bit auxiliary PMOS weight signal VPZ < n:1> being partially or fully high, the k-bit NMOS weight signal VN < k:1> being partially or fully low, the n-bit auxiliary NMOS weight signal VNZ < n:1> being partially or fully high, and the k-bit NMOS weight signal VP < k:1> being partially or fully low.
The same applies to the V11 state generation as in fig. 5;
intermediate state V01 state results as in fig. 6; the method is characterized in that VPZ < n:1> is partially or completely changed into high level, VNZ < n:1> is partially or completely changed into low level, at the moment, the first auxiliary PMOS NMOS tube and the second NMOS tube are both closed, only the second PMOS tube is opened, but the pull-down current capability of the second PMOS tube changes along with the change of the first output node, when the first output node approaches to the vicinity of the threshold voltage VTHP of the second PMOS tube, the second PMOS tube enters a subthreshold region, the pull-down current capability becomes very weak, and the V01 level value approaches to the VTHP.
Intermediate state V10 state results as in fig. 7; the method is characterized in that VPZ < n:1> is partially or completely changed into high level, VNZ < n:1> is partially or completely changed into low level, at the moment, the first auxiliary PMOS NMOS tube and the second PMOS are both closed, only the second NMOS tube is opened, but the charging current capacity of the second NMOS tube changes along with the change of a first output node, when the first output node approaches to the vicinity of the difference value (VDD-VTHN) between the power supply voltage VDD and the threshold voltage VTHN of the second NMOS tube, the second NMOS tube enters a subthreshold region, the pull-down current capacity becomes very weak, and the V10 level value approaches to VDD-VTHN.
The beneficial effects are that: the traditional PAM4 signal has 4 levels to be accurately controlled, and a plurality of gears are required to be accurately controlled for the output capability of the driving stage, so that the setting of the gears can be greatly reduced, the level value of the middle level V10V 01 is stabilized near VTHP and VDD-VTHN, the design of the driving stage is greatly simplified, and the invention has the advantages of low power consumption and small area.
The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the invention is not limited to the particular embodiments disclosed, but is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the invention.

Claims (3)

1. A serial interface transmitting end driving device for outputting multiple levels, the driving device comprising:
the device comprises a data signal processing unit, a plurality of front stage P auxiliary driving units, a plurality of front stage N auxiliary driving units, a plurality of driving stages, a plurality of front stage P driving units, a plurality of front stage N driving units and a plurality of auxiliary driving stages;
the output end of the data signal processing unit is connected with a plurality of front-stage P auxiliary driving units, a plurality of front-stage N auxiliary driving units, a plurality of front-stage P driving units and a front-stage N driving unit;
the output ends of the plurality of front-stage P auxiliary driving units and the plurality of front-stage N auxiliary driving units are respectively connected with the plurality of driving stages;
the output ends of the front-stage P driving unit and the front-stage N driving unit are respectively connected with the auxiliary driving stage;
the data signal processing unit specifically includes: the device comprises a data phase delay module, a high-speed data multiplexing array, a data weight control module and a high-speed multiphase clock generating device;
the data phase delay module is used for inputting low-speed N-bit data;
the data weight control module is connected with the data phase delay module;
the data phase delay module sends N-bit data with different delay phases to the high-speed data multiplexing array;
the high-speed multi-phase clock generating device sends multi-phase clock signals to the high-speed data multiplexing array;
the high-speed data multiplexing array outputs an n-bit auxiliary PMOS weight signal, an n-bit auxiliary NMOS weight signal, a k-bit NMOS weight signal, and a k-bit PMOS weight signal.
2. The apparatus of claim 1, wherein the driving stage specifically comprises: the first auxiliary PMOS tube array and the first auxiliary NMOS tube array;
the first auxiliary PMOS tube array is composed of n PMOS tubes with different sizes, and the first auxiliary NMOS tube array is composed of n NMOS tubes with different sizes;
the grid electrode of the first auxiliary PMOS tube array is connected with the front-stage P auxiliary driving unit;
the drain electrode of the first auxiliary PMOS tube array is connected with a power supply, the source electrode of the first auxiliary PMOS tube array is connected with the drain electrode of the first auxiliary NMOS tube, the grid electrode of the first auxiliary NMOS tube array is connected with the front-stage N driving unit, and the source electrode of the first auxiliary NMOS tube array is connected with a ground wire.
3. The apparatus of claim 1, wherein the auxiliary driving stage specifically comprises: the second NMOS tube array and the second PMOS tube array; the second NMOS tube array is provided with n NMOS tubes with different sizes, and the second PMOS tube array is provided with n PMOS tubes with different sizes;
the drain electrode of the second NMOS tube array is connected with a power supply, the grid electrode of the second NMOS tube array is connected with the front-stage P driving unit, and the source electrode of the second NMOS tube array is connected with the drain electrode of the second PMOS tube array;
the front-stage N driving unit is connected with the grid electrode of the second PMOS tube array, and the source electrode of the second PMOS tube array is connected with the ground wire.
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TWI388120B (en) * 2009-12-17 2013-03-01 Phison Electronics Corp Driving circuit for input/output interface
CN104333524B (en) * 2014-11-13 2017-07-07 清华大学 A kind of HSSI High-Speed Serial Interface emitter
CN109308922B (en) * 2017-07-28 2020-10-09 中芯国际集成电路制造(上海)有限公司 Memory and data reading drive circuit thereof
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