CN104333524B - A kind of HSSI High-Speed Serial Interface emitter - Google Patents
A kind of HSSI High-Speed Serial Interface emitter Download PDFInfo
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- CN104333524B CN104333524B CN201410641518.3A CN201410641518A CN104333524B CN 104333524 B CN104333524 B CN 104333524B CN 201410641518 A CN201410641518 A CN 201410641518A CN 104333524 B CN104333524 B CN 104333524B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
A kind of new HSSI High-Speed Serial Interface emitter,Including combiner and voltage-mode driver,Also include feed forward equalizer and feedback equalizer simultaneously,The feed forward equalizer is integrated in voltage-mode driver,The high-speeld code-flow serial data of input connection combiner output,And output impedance and equalizing coefficient can be carried out separately adjustable,The feedback equalizer includes being both connected to the low pass filter and transconductance stage circuit of voltage-mode driver output end,The low-frequency component of the high data rate bit stream that wherein described low pass filter is exported to voltage-mode driver is extracted,The transconductance stage connects the low pass filter output simultaneously,The output voltage of the low pass filter is converted into electric current by it,And the electric current is sued for peace with the output current of the voltage-mode driver,Combined with feedback equalization present invention employs feed forward equalization,So that skin-effect attenuation and dielectric loss decay are compensated by feedback and feedforward respectively,It is equalized simultaneously,And substantially reduce the power consumption of emitter.
Description
Technical field
The invention belongs to circuit design and technical field of data transmission, more particularly to a kind of new HSSI High-Speed Serial Interface hair
Penetrate machine.
Background technology
HSSI High-Speed Serial Interface transceiver is widely used in wired data transfer.Emitter will be sent out after multidiameter delay data combining
It is sent on transmission channel.Receiver receives signal and branch from transmission channel, so that circuit below is continued with.
The data transfer rate of High Speed Serial transceiver transmission in recent years constantly rises, at present commercial HSSI High-Speed Serial Interface data transfer rate
28Gbps can be reached.Design of the data bit rate for gradually being lifted to HSSI High-Speed Serial Interface emitter proposes many challenges.
Wherein, more serious challenge is that the data flow transmission in the channel of high-transmission code check receives serious high frequency attenuation.This
A little high frequency attenuations mostly come from two aspects, are respectively dielectric loss and Kelvin effect.Declined by high frequency caused by dielectric loss
Subtracting can be compensated using traditional balanced device, for example feed forward equalizer (FFE).However, being decayed by caused by Kelvin effect
Cannot be compensated with traditional equalization methods such as FFE.This is due to being decayed generally in relatively low frequency by caused by Kelvin effect
Rate begins to produce influence, and this frequency is relevant with the specific characteristic of channel, typically tens of megahertzs.Meanwhile, by becoming, skin is imitated
The decay that should cause has very slow slope, typically smaller than 4dB/dec at low frequency.And FFE is only capable of on its zero frequency
The attenuation compensation of steeper 20dB/dec is provided.Therefore the decay for being caused by Kelvin effect needs to carry out extra equilibrium.
Additionally, with the lifting of code check, the power consumption of emitter is gradually lifted.The driver of usual emitter can be consumed largely
Power consumption.The driver of current-mode and the driver of voltage-mode are used in emitter frequently as line drive.Current-mode driver has
There is impedance easy to control, balanced easily to realize, the advantages of impedance and separately adjustable equalizing coefficient, but the power consumption of consumption is larger.Electricity
The power consumption of the driver of pressing mold is relatively low.In the case where output voltage amplitude is consistent, the power consumption of driver of voltage-mode well below
Current-mode driver.However, the driver of voltage-mode to have the shortcomings that impedance matching and equalizing coefficient are difficult separately adjustable.
The content of the invention
In order to overcome the shortcoming of above-mentioned prior art, it is an object of the invention to provide a kind of new HSSI High-Speed Serial Interface
Emitter, the emitter balanced device employs feed forward equalization and is combined with feedback equalization, current-mode driver and voltage-mode driver
With reference to structure so that skin-effect attenuation and dielectric loss decay can respectively by feed back and feedforward compensate, while
It is equalized；Meanwhile, the structure combined using voltage-mode and current-mode driver substantially reduces the power consumption of emitter.
To achieve these goals, the technical solution adopted by the present invention is：
A kind of new HSSI High-Speed Serial Interface emitter, including combiner and voltage-mode driver, while also including feedforward
Balanced device and feedback equalizer, the feed forward equalizer are integrated in voltage-mode driver, input connection combiner output
High-speeld code-flow serial data, and output impedance and equalizing coefficient can be carried out it is separately adjustable, the feedback equalizer include connect
The low pass filter and transconductance stage circuit of voltage-mode driver output end are connected on, wherein the low pass filter drives to voltage-mode
The low-frequency component of the high data rate bit stream of device output is extracted, and the transconductance stage connects the low pass filter output simultaneously,
The output voltage of the low pass filter is converted into electric current by it, and by the output current of the electric current and the voltage-mode driver
Sued for peace.
The combiner by the parallel data combining of multi-path low speed be multipath high-speed difference bit stream MAINP/MAINN with
POSTP/POSTN, wherein POSTP/POSTN are obtained by one data symbol width of MAINP/MAINN time delays, MAINP/MAINN
It is input into respectively as two of two tap feed forward equalizers with POSTP/POSTN.
The combiner is connected with one for producing the clock of clock signal required for combinings at different levels in combiner to produce
Module.
Preferably, the voltage-mode driver is made up of 22 actuator units, wherein, wherein 15 actuator units
Data input is connected to MAINP/MAINN, and the data input of another 7 actuator units is connected to POSTP/POSTN, connection
The positive output of the actuator unit of MAINP/MAINN is connected with the anti-phase output of the actuator unit for being connected POSTP/POSTN,
The anti-phase output of actuator unit for connecting MAINP/MAINN is exported with the positive of the actuator unit for being connected POSTP/POSTN
It is connected, so that a feed forward equalizer for two taps is constituted, the Input Control Word UP_RES of each actuator unit<0:3>, DN_
RES<0:3>The pull-up and pull down resistor of each actuator unit, SLICE_EN_MAIN are adjusted respectively<0:3>And SLICE_EN_
POST<0:2>The switch for controlling each actuator unit and then the equalizing coefficient for controlling feed forward equalization device.22 drivings
Have in device unit 15 it is in running order, the output impedance of each actuator unit is 750 ohm, when open one connection
The unit for MAINP/MAINN then closes a unit for the POSTP/POSTN that ins succession, complete in the case of keeping output impedance constant
The regulation of paired equalizing coefficient.
Described each actuator unit is made up of the adjustable phase inverter of two output impedances, the data input of actuator unit
It is a pair of differential signals of CMOS logic, the output impedance regulation of actuator unit is by configuring parallel-connected transistor pipe size come real
Existing, the size of parallel transistor is by 4bit binary codes UP_RES<0:3>And DN_RES<0:3>It is controlled, and then adjusts respectively
The pull-up and pull-down impedance of actuator unit are saved, SLICE_EN controls the working condition of actuator unit, when SLICE_EN controls
When actuator unit processed is off state, its output impedance is approximately infinitely great.
The low pass filter is configurable by frequency, its concrete numerical value between 10MHz to 1GHz, by specific channel
It is fixed.The low pass filter is active low-pass filter, and the wave filter is based on the current mode logic amplifier knot of PMOS input
Structure, and realized to its cut-off frequency by being configured to switched capacitor array and then output load capacitance being configured
Regulation, and using source degeneracy resistance RdegTo improve the linearity of the low pass filter.
The transconductance stage is based on the structure of current steer, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, a MOS
The grid of the grid of pipe and the second metal-oxide-semiconductor connects the two ends of the low pass filter difference output respectively, the drain electrode of the first metal-oxide-semiconductor and
The drain electrode of the second metal-oxide-semiconductor connects the two ends of the difference output of the voltage-mode driver respectively, the 3rd metal-oxide-semiconductor as current source, its
The source electrode of drain electrode the first metal-oxide-semiconductor of connection and the source electrode of the second metal-oxide-semiconductor.
Compared with prior art, emitter proposed by the present invention employs feed forward equalization and is combined with feedback equalization, current-mode
The structure that driver is combined with voltage-mode driver, can carry out balanced benefit simultaneously to skin-effect attenuation and dielectric loss decay
Repay and reduce emitter power consumption.Meanwhile, using voltage-mode driver, independent tune can be carried out to impedance matching and equalizing coefficient
Section.
Brief description of the drawings
Fig. 1 is the transmitter architecture schematic diagram for proposing.
Fig. 2 is the schematic diagram that a kind of feed forward equalization is realized.
Fig. 3 is the circuit diagram of actuator unit in Fig. 2.
Fig. 4 is a kind of possible circuit embodiments of low pass filter and transconductance device in Fig. 1.
Specific embodiment
Below in conjunction with the accompanying drawings with embodiment, preferred embodiment is elaborated.It is emphasized that the description below is only
It is exemplary, rather than in order to limit the scope of the present invention and its application.
As shown in figure 1, a kind of new HSSI High-Speed Serial Interface emitter, including combiner, clock generation module, voltage-mode
Driver, low pass filter, transconductance stage etc..It is two-pass DINSAR that wherein combiner is responsible for the parallel data combining of multi-path low speed
High-speed serial data：MAINP/MAINN and POSTP/POSTN.Wherein POSTP/POSTN is by by MAINP/MAINN time delays
What one data symbol width was obtained.Clock generation module is responsible for producing in combiner the clock signal required for combinings at different levels.
It should be noted that the feed forward equalization in order to realize more multi-tap, combiner can export the high-speeld code-flow of more multichannel here.Close
Road device and the common circuit that clock generation circuit is in HSSI High-Speed Serial Interface emitter, can be accomplished in several ways, herein not
Illustrate.
Voltage-mode driver is integrated with a feed forward equalizer, can carry out independent tune to impedance matching and equalizing coefficient
Section, MAINP/MAINN, POSTP/POSTN will act as two inputs of tap of feed forward equalizer, and feed forward equalizer main compensation is situated between
The decay that matter loss causes.Emitter contains a low pass filter for entering to the low-frequency component for exporting high data rate bit stream
Row is extracted.The cut-off frequency of low pass filter can be configured for different channels spy's letter.It is generally relatively low by frequency, can
Configured between 10MHz to 1GHz.The low frequency of the high data rate bit stream that low pass filter is exported to voltage-mode driver
Composition is extracted, the photovoltaic conversion that transconductance stage exports low pass filter be electric current and with the output current of voltage-mode driver
Sued for peace.Due to the presence of low pass filter, the electric current of transconductance stage output only has low-frequency component.This part low-frequency component is from most
Subtracted in whole output stream, so that the relative radio-frequency component that improve data flow, so that what equilibrium was caused by Kelvin effect
Decay.
Fig. 2 is a kind of theory diagram of the voltage-mode driver for being capable of achieving two tap feed forward equalizations.The driver includes 22
Individual actuator unit, it is also possible to comprising more actuator units.Wherein 15 actuator units are connected to MAINP/MAINN,
Another 7 actuator units are connected to POSTP/POSTN.It should be noted that the number of actuator unit should be with essence in a balanced way
The tap number of degree and balanced device changes, and the actuator unit number indicated in figure is intended only as example.
Connect the positive output of the actuator unit of MAINP/MAINN and the actuator unit for being connected POSTP/POSTN
Anti-phase output is connected, and connects the anti-phase output and the driver list for being connected POSTP/POSTN of the actuator unit of MAINP/MAINN
The positive output of unit is connected.They connect and compose a feed forward equalizer for two taps.The control word input of actuator unit
UP_RES<0:3>, DN_RES<0:3>The pull-up and pull down resistor of each actuator unit are adjusted respectively.SLICE_EN_MAIN<
0:3>And SLICE_EN_POST<0:2>The switch for controlling each actuator unit and then the equalizing coefficient for controlling feed forward equalization.With
As a example by Fig. 2, in specific works, one has that 15 actuator units are in running order, the output resistance of each actuator unit
Anti- is all 750 ohm.A list for the POSTP/POSTN that ins succession then is closed when a unit for being connected to MAINP/MAINN is opened
Unit, keeps completing the regulation to equalizing coefficient in the case that output impedance is constant.
Fig. 3 is a kind of possible realization of the actuator unit shown in Fig. 2, by the adjustable phase inverter structure of two output impedances
Into.Its data input is a pair of differential signals of CMOS logic.The output impedance regulation of actuator unit is by configuring simultaneously
Join transistor size to realize.The size of parallel transistor is by 4bit binary codes UP_RES<0:3>And DN_RES<0:3>Carry out
Control, and then the pull-up and pull-down impedance of adjustment driver unit respectively.SLICE_EN controls the work shape of actuator unit
State, when SLICE_EN control actuator units are off state, its output impedance is approximately infinitely great.
Fig. 4 is a kind of circuit realiration of low pass filter shown in Fig. 1 and transconductance stage.The low pass filter is one to be had
Source low pass filter, and be the current mode logic amplifier architecture based on PMOS input.The low pass filter cutoff frequency
Regulation be by C<0>,C<1>,..C<5>Configured and then output load capacitance is configured to realize, its tool
Body numerical value between 10MHz to 1GHz, depending on specific channel.One source degeneracy resistance Rdeg is used for improving the low pass filter
The linearity.The output of transconductance stage is connected to the output of voltage-mode driver, and be converted into for the output voltage of low pass filter by it
Electric current is simultaneously sued for peace with the output current of voltage-mode driver, completes the isostatic compensation to Frequency Power Loss.On circuit realiration,
The transconductance stage can be based on the structure of current steer, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor
With the two ends of the difference output that the grid of the second metal-oxide-semiconductor connects the low pass filter respectively, the drain electrode of the first metal-oxide-semiconductor and second
The drain electrode of metal-oxide-semiconductor connects the two ends of the difference output of the voltage-mode driver respectively, and used as current source, it drains the 3rd metal-oxide-semiconductor
Connect the source electrode of the first metal-oxide-semiconductor and the source electrode of the second metal-oxide-semiconductor.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
Should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
It is defined.
Claims (7)
1. a kind of HSSI High-Speed Serial Interface emitter, including combiner, voltage-mode driver, feed forward equalizer and feedback equalizer,
The feed forward equalizer is integrated in voltage-mode driver, the high-speeld code-flow serial data of input connection combiner output, and
Output impedance and equalizing coefficient can be carried out it is separately adjustable, the feedback equalizer include be both connected to voltage-mode driver output
The low pass filter and transconductance stage circuit at end, wherein the high data rate bit stream that the low pass filter is exported to voltage-mode driver
Low-frequency component extracted, the transconductance stage circuit connects low pass filter output simultaneously, and it is by the LPF
The output voltage of device is converted into electric current, and the electric current is sued for peace with the output current of the voltage-mode driver, its feature
It is：
The parallel data combining of multi-path low speed is multipath high-speed difference bit stream MAINP/MAINN and POSTP/ by the combiner
POSTN, wherein POSTP/POSTN are obtained by one data symbol width of MAINP/MAINN time delays, MAINP/MAINN with
Two inputs of the POSTP/POSTN respectively as two tap feed forward equalizers；
The voltage-mode driver is made up of 22 actuator units, wherein, wherein 15 data inputs of actuator unit connect
MAINP/MAINN is connected to, the data input of another 7 actuator units is connected to POSTP/POSTN, connection MAINP/MAINN's
The positive output of actuator unit is connected with the anti-phase output of the actuator unit for being connected POSTP/POSTN, connects MAINP/
The anti-phase output of the actuator unit of MAINN is connected with the positive output of the actuator unit for being connected POSTP/POSTN, so that structure
Into a feed forward equalizer for two taps, the Input Control Word UP_RES of each actuator unit<0:3>, DN_RES<0:3>Point
The pull-up and pull down resistor of each actuator unit, SLICE_EN_MAIN are not adjusted<0:3>And SLICE_EN_POST<0:2>Control
The switch for making each actuator unit and then the equalizing coefficient for controlling feed forward equalizer.
2. HSSI High-Speed Serial Interface emitter according to claim 1, it is characterised in that the combiner is connected with to be used for
Produce the clock generation module of clock signal required for combinings at different levels in combiner.
3. HSSI High-Speed Serial Interface emitter according to claim 1, it is characterised in that have 15 in 22 actuator units
Individual in running order, the output impedance of each actuator unit is 750 ohm, and MAINP/ is connected to when opening one
The unit of MAINN then closes a unit for the POSTP/POSTN that ins succession, and keeps being completed to equilibrium in the case that output impedance is constant
The regulation of coefficient.
4. the HSSI High-Speed Serial Interface emitter according to claim 1 or 3, it is characterised in that described each actuator unit by
Two adjustable phase inverters of output impedance are constituted, and the data input of actuator unit is a pair of differential signals of CMOS logic, is driven
The output impedance regulation of dynamic device unit realizes that the size of parallel transistor is entered by 4bit bis- by configuring parallel-connected transistor pipe size
Code UP_RES processed<0:3>And DN_RES<0:3>It is controlled, and then the pull-up and pull-down impedance of adjustment driver unit respectively,
SLICE_EN controls the working condition of actuator unit, when SLICE_EN control actuator units are off state, its
Output impedance is approximately infinitely great.
5. HSSI High-Speed Serial Interface emitter according to claim 1, it is characterised in that the low pass filter can by frequency
Configuration, its concrete numerical value between 10MHz to 1GHz, depending on specific channel.
6. the HSSI High-Speed Serial Interface emitter according to claim 1 or 5, it is characterised in that the low pass filter is active
Low pass filter, the wave filter is based on the current mode logic amplifier architecture of PMOS input, and the regulation of its cut-off frequency is logical
Cross and switched capacitor array is configured and then output load capacitance is configured to realize, and utilize source degeneracy resistance
RdegTo improve the linearity of the low pass filter.
7. HSSI High-Speed Serial Interface emitter according to claim 6, it is characterised in that the transconductance stage circuit is based on current steer
Structure, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid point of the grid of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor
The two ends of the low pass filter difference output are not connect, and the drain electrode of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor connect the electricity respectively
The two ends of the difference output of pressing mold driver, the 3rd metal-oxide-semiconductor as current source, the source electrode of its drain electrode the first metal-oxide-semiconductor of connection and the
The source electrode of two metal-oxide-semiconductors.
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| TWI823731B (en) * | 2022-12-28 | 2023-11-21 | 國立清華大學 | Feed-forward equalizer and voltage-mode signal transmitter using thereof |
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| CN109246037B (en) * | 2018-08-13 | 2019-07-12 | 上海奥令科电子科技有限公司 | Driver and HSSI High-Speed Serial Interface transmitter for high-speed serial data transmission |
| US11069989B2 (en) * | 2019-07-15 | 2021-07-20 | Huawei Technologies Co., Ltd. | Method and apparatus for multi-mode multi-level transmitter |
| US11528168B2 (en) * | 2019-08-02 | 2022-12-13 | Sitrus Technology Corporation | Methods, systems and apparatus for hybrid signal processing for pulse amplitude modulation |
| CN111446955B (en) * | 2020-05-07 | 2023-07-14 | 江苏集萃智能集成电路设计技术研究所有限公司 | Pre-coding swing controllable low-power consumption SST driver |
| CN113708742B (en) * | 2020-05-20 | 2022-08-19 | 广东高云半导体科技股份有限公司 | Drive circuit, control method thereof, transmitter and serial deserializing system |
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