KR101845326B1 - Multiplexer including level shifting function - Google Patents

Abstract

The present invention provides a multiplexer having a level shifting function. The multiplexer according to the present invention includes a first pull-up driving part and a second pull-up driving part for driving the voltage level of an output signal to a power supply voltage (VDD) level according to the level of a first clock signal and a second clock signal, and a first pull-down driving part and a second pull-down driving part for driving the voltage level of the output signal to the ground voltage (VSS) level according to the level of the first clock signal and the second clock signal. Accordingly, the multiplexer according to the present invention can easily drive a VML-type Tx driver that requires a full-swing input signal that is the same as the power supply voltage of a driver, and reduces power consumption when a serializer is implemented.

Description

[0001] MULTIPLEXER INCLUDING LEVEL SHIFTING FUNCTION [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer, and more particularly, to a multiplexer capable of performing a full swing and a high-speed operation regardless of a swing level of an input voltage.

Recently, the bandwidth of data increases, and the cost of channel number and the burden of electromagnetic interference between channels cause high-speed communication system to convert low-speed parallel data channels into one high-speed single data channel I use a lot of serializers.

The serializer is typically configured to include a plurality of multiplexers and a Tx driver, and the Tx driver is implemented using a high supply voltage to have a large voltage swing level.

In order for such a TX driver to have a large voltage swing level, the signal input to the Tx driver must have a voltage swing level above a certain level, so there is a method of disposing a level converter in front of the multiplexer disposed at the last stage of the plurality of multiplexers. However, the level converter itself has a drawback in that power consumption is large and power supply switching noise is large.

To compensate for these drawbacks, a method of incorporating a level converter function in the final stage multiplexer has been proposed. In other words, the way to embed the level converter function in the multiplexer is to make the output signal of the multiplexer have the voltage swing level required by the Tx driver.

Thus, when converting the voltage swing level required by the Tx driver, the method may vary depending on the type of the Tx driver.

In general, the Tx driver may have a CML (Current Mode Logic) type or a VML (Voltage Mode Logic) type. The CML type has a relatively low voltage swing level and is easy to convert. Therefore, it is not difficult to implement a level converter in the multiplexer. However, the power consumption of the Tx driver itself is larger than that of the VML type, have.

However, the Tx driver of the VML type is advantageous in that the power consumption is small and the chip size is small, but a signal having a full-swing voltage level must be received as input. In order to satisfy the requirement, a level converter There is a problem that it is difficult to implement the method inherent in the present invention.

Accordingly, an object of the present invention is to provide a multiplexer having a full-swing voltage level required by a VML type Tx driver without adding a separate level converter.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a multiplexer for driving a voltage level of an output signal to a power supply voltage (VDD) level according to a level of a first clock signal and a second clock signal, And a second pull-down driving unit and a second pull-down driving unit for driving the voltage level of the output signal toward the ground voltage (VSS) level according to the level of the first clock signal and the second clock signal .

The first pull-up driving part and the second pull-down driving part are controlled according to the level of the data signal, and the second pull-up driving part and the first pull-down driving part can be controlled according to the level of the inverted data signal.

The data signal and the inverted data signal may be configured to be applied to the gate of the NMOS transistor.

The first pull-up driving unit, the second pull-up driving unit, the first pull-down driving unit, and the second pull-down driving unit implement a circuit using a Domino Logic method to preliminarily charge and discharge the voltage of a specific node, And latch a voltage of the particular node according to an up or down transition of a clock signal that arrives after the full-swing voltage level.

The multiplexer according to the present invention can be configured to output a full-swing signal even when the voltage swing level of the data signal input to the input is small.

The details of other embodiments are included in the detailed description and drawings.

The present invention can reduce a chip size of a serializer by providing a multiplexer capable of outputting a signal having a full-swing voltage level required by a VML-type Tx driver in a serializer using a Vx-type Tx driver, Power consumption can also be reduced.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

FIG. 1 is a schematic diagram of a serializer including a multiplexer having a level converter function according to an embodiment of the present invention. Referring to FIG.
2 is a block diagram schematically showing a configuration of a multiplexer according to an embodiment of the present invention.
3 is a timing chart for explaining driving of a multiplexer according to an embodiment of the present invention.
4 is a circuit diagram illustrating a detailed configuration of a unit cell of a multiplexer according to an embodiment of the present invention.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Specific examples and arrangements in devices are described for the purpose of simplifying the present invention. These are merely examples and are not to be construed in a limiting sense. Further, the present invention repeats the drawing identification numbers and / or characters in various examples. Such repetition is used for the sake of simplicity and clarity, and is not intended to be limited to the relationship between the various embodiments and / or configurations discussed.

In addition, throughout the specification, when an element is referred to as " including " an element, it is to be understood that the element may include other elements, The phrases such as where a component is coupled to another component, coupled to, and / or coupled to, may include embodiments in which two components are directly connected, and in addition, another component may be coupled between two components Such that the two components are not directly connected to each other. Also, it will be understood that, if the terms referring to first, second, etc. may be used herein to describe various components, the components are not intended to be limited to these terms. Only these terms are used to distinguish one component from another.

FIG. 1 is a schematic diagram of a serializer including a multiplexer having a level converter function according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 1, a serializer 100 according to an exemplary embodiment of the present invention includes a plurality of multiplexers 110, 120, and 130 and a Tx driver 140.

The plurality of multiplexers 110, 120 and 130 are driven using a first power supply voltage VDD1 that is a low power supply voltage and include a first multiplexer 110, a second multiplexer 120, and a third multiplexer 130 do. Here, the first multiplexer 110 is a 64:16 multiplexer, the second multiplexer 120 is a 16: 4 multiplexer, and the third multiplexer 130 is a 4: 1 multiplexer. In particular, the third multiplexer 130 may be a multiplexer having a level shifter function. The number of bits and the bit-rate shown in FIG. 1 are only one example, and the third multiplexer 130 is not limited to 4: 1 multiplexers, 1, and so on.

 The Tx driver 140 is implemented by a VML (Voltage Mode Logic) method and uses a second power supply voltage VDD2 that is a high power supply voltage to have a large voltage swing level.

In general, the Vx Tx driver in the serializer has lower power consumption, smaller chip size, and faster operation speed than the Cx (Current Mode Logic) Tx driver. However, since the signal input to the Tx driver is input to the Tx driver Because it is difficult to implement a full-swing voltage level equal to the supply voltage, the VML-style Tx driver is not well suited for serializers that output signals with a large voltage swing level.

In more detail, if a level converter is not implemented in a general VML Tx driver, the first power source voltage VDD1, which is a low power supply voltage, must be written in accordance with the voltage swing level input to the input, and the output swing is limited. This is because, if the power supply voltage is higher than the driver input swing, the Vx Tx driver will not switch properly and the normal operation will not be possible.

For this purpose, there is a method of arranging the level converter in front of the third multiplexer, but there is also a difficulty in this method because the power of the level converter itself is large and the power noise is large.

Accordingly, in the present invention, it is desired to provide a multiplexer in which the Tx driver 140 of the VML scheme is made to be capable of full swing by implementing the pull-up and pull-down logic to implement the level converter function in the multiplexer. A more detailed configuration of such a multiplexer will be described with reference to FIGS. 2 to 4. FIG.

FIG. 2 is a block diagram schematically illustrating a configuration of a multiplexer according to an embodiment of the present invention, and FIG. 3 is a timing diagram illustrating driving of a multiplexer according to an embodiment of the present invention.

Referring to FIG. 2, a multiplexer 130 according to an embodiment of the present invention includes a plurality of unit cells, that is, a first unit cell 131 to a fourth unit cell 134. The number of unit cells of the multiplexer 130 is not limited to four, because the number of unit cells is four in the embodiment of the present invention.

The first unit cell 131 to the fourth unit cell 134 have the same circuit structure as each other, but different data signals and different clock signals are input. For example, as shown in FIG. 3, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3, which are input to the first unit cell 131, 3, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3, which are input to the second unit cell 132, As shown, Clock 90 °, Clock 180 °, Clock 270 ° can be input. The data signal input to the first unit cell 131 is the first data signal D1 and the first inverted data signal DB1 and the data signal input to the second unit cell 132 is the second data signal D1. (D2) and a second inverted data signal (DB2), different data signals may be input to each unit cell. At this time, when the pull-up or pull-down operation is performed in the first unit cell 131 and a signal is output, no pull-up or pull-down operation is performed on the second unit cell 132 to the fourth unit cell 134, .

That is, as shown in FIG. 3, the multiplexer 130 according to an embodiment of the present invention includes a first clock signal CK1 having a clock 0 ° of the first unit cell 131 and a second clock signal CK1 having a clock 90 °, A current flows when the clock signal CK2 is at a high level and a signal is output from the first unit cell 131 according to the level of the first data signal D1 and the first inverted data signal DB1, At this time, current may not flow through the second unit cell 132 to the fourth unit cell 134.

Thereafter, when the first clock signal CK1 having the clock 0 degree becomes the low level, the second clock signal CK2 having the clock 90 degrees and the third clock signal CK3 having the clock 180 degrees becoming the high level A current flows through the second unit cells 132 and C2 and a signal is output from the second unit cell 132 according to the level of the second data signal D2 and the second inverted data signal DB2.

The structure of the unit cell of the multiplexer 130 will be described in detail with reference to FIG.

4 is a circuit diagram illustrating a detailed configuration of a unit cell of a multiplexer according to an embodiment of the present invention.

Referring to FIG. 4, each unit cell 131 of the multiplexer 130 includes a first driving unit 1311 and a second driving unit 1312. 4, the detailed structure of the first unit cell 131 will be described by way of example. In the multiplexer according to the embodiment of the present invention, as described above, each unit cell may have the same circuit structure.

The first driving unit 1311 includes a first pull-up driving unit 1311p and a first pull-down driving unit 1311d.

The first pull-up driving part 1311p outputs the voltage level of the output signal OUT to the power supply voltage VDD level according to the level of the first clock signal CK1 having a clock of 0 degrees and the second clock signal CK2 having a clock of 90 degrees. Up direction. At this time, the first pull-up driver 1311p may be controlled by the level of the first data signal D1. Specifically, the first pull-up driver 1311p outputs a first data signal (CK1) when the level of the first clock signal (CK1) at Clock 0 ° and the level of the second clock signal (CK2) at Clock 90 ° are at a high level D1 is at a high level, the output signal out can be pulled up. The first pull-up driver 1311p includes a first PMOS transistor P1 receiving the third clock signal CK3, a second PMOS transistor P2 receiving the second clock signal CK2, A first NMOS transistor N1 receiving a first clock signal CK1 and a second NMOS transistor N2 receiving a third clock signal CK3 and a first pull-up transistor PU1.

The first pull-down driving unit 1311d converts the voltage level of the output signal OUT to the ground voltage VSS level according to the level of the first clock signal CK1 having a clock of 0 degrees and the second clock signal CK2 having a clock of 90 degrees. Can be pulled down. At this time, the first pull-down driving unit 1311d may be controlled by the level of the first inverted data signal DB1. Specifically, when the level of the first clock signal CK1 having a clock of 0 degrees and the level of a second clock signal CK2 having a clock of 90 degrees are at a high level, the first pull-down driving unit 1311d outputs a first inverted data signal The output signal out can be pulled down if the level of the output signal DB1 is at a high level. The first pull-down driving unit 1311d includes a third PMOS transistor P3 receiving the first clock signal CK1, a third NMOS transistor N3 receiving the first inverted data signal DB1, And a fourth PMOS transistor N4 and a first pull-down transistor PD1 receiving the signal CK1.

The second driving unit 1312 includes a second pull-up driving unit 1312p and a second pull-down driving unit 1312d.

The second pull-up driving part 1312p changes the voltage level of the output signal OUTB to the power supply voltage VDD level according to the level of the first clock signal CK1 having a clock of 0 degrees and the second clock signal CK2 having a clock of 90 degrees. Up direction. At this time, the second pull-up driver 1312p may be controlled according to the level of the first inverted data signal DB1. Specifically, when the level of the first clock signal CK1 and the level of the second clock signal CK2 are at a high level, the second pull-up driving unit 1312p turns the level of the first inverted data signal DB1 to the high level The output signal OUTB can be pulled up. The configuration of the second pull-up driver 1312p is the same as that of the first pull-up driver 1311p.

The second pull-down driving unit 1312d adjusts the voltage level of the output signal OUTB according to the levels of the first clock signal CK1 at clock 0 ° and the second clock signal CK2 at clock 90 ° to the ground voltage VSS level Can be pulled down. At this time, the second pull-down driving unit 1312d can be controlled according to the level of the first data signal D1. Specifically, if the level of the first data signal D1 is high when the level of the first clock signal CK1 and the level of the second clock signal CK2 is high, the second pull-down driving unit 1312d The output signal out can be pulled down. The second pull down portion 1312d has the same configuration as the first pull down portion 1311d.

As such, the multiplexer 130 according to the embodiment of the present invention may be configured such that the first clock signal CK1 or the second clock signal CK2 has a low level or the first data signal The first pull-down driver 1311d can be completely turned off if the level of the first pull-down driver 1311d has a high level. This is because the multiplexer 130 according to an embodiment of the present invention is designed to be capable of full swing. Accordingly, the multiplexer 130 according to the embodiment of the present invention is designed so that static current does not flow, thereby reducing power consumption.

In the meantime, the multiplexer 130 according to an embodiment of the present invention is configured such that the first data signal D1 or the first inverted data signal DB1 is supplied to the first NMOS transistor N1 and the third NMOS transistor N3 As shown in FIG. The reason for designing the data signal input to receive only the NMOS transistors is to turn it off clearly when the transistor has to be turned off, even if the voltage swing level is low. In more detail, when the input level is low, the gate-source voltage of the NMOS transistor becomes 0V regardless of the voltage swing level, and the NMOS transistor can be turned off explicitly. If the input level is low when the input is received by the PMOS transistor, the PMOS transistor can be turned on clearly. However, when the input level is high, the voltage level is low, Becomes greater than 0V, the PMOS transistor can not be turned off clearly, and in this case, a very large leakage current flows, which hinders logic operation. As described above, the multiplexer 130 according to the embodiment of the present invention is designed so that the first data signal D1 and the first inverted data signal DB1 are inputted to the gates of the NMOS transistors, not.

However, if the gate-source voltage of the NMOS transistor is low when the input level is high and the NMOS transistor can not be sufficiently turned on, the voltage charging or discharging will be slowed down and the logic operation speed may be limited .

In order to solve this problem, the multiplexer 130 according to an embodiment of the present invention may be implemented in a Domino Logic manner. 4, if the first inverted data signal DB1 of the second pull-up driving part 1312p has a high level, the second pull-up driving part 1312p supplies a pre- Can be pre-dischored. This charged current is latched when the next clock signal is applied, resulting in a full high or low level voltage. Thus, even if the gate voltage of the NMOS transistor is low due to the small input swing, the current charged or discharged before one clock cycle before the NMOS transistor is turned on is used when the next clock signal is applied, Speed can be accelerated.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: Serializer
110: first multiplexer
120: second multiplexer
130: Third multiplexer
140: Tx driver
131: first unit cell
132: second unit cell
133: third unit cell
134: fourth unit cell
1311:
1311p: first pull-up driving section
1311d: first pull-down driving section
1312:
1312p: a second pull-up driving section
1312d: a second pull-down driving section

Claims (5)

A first pull-up driving unit and a second pull-up driving unit for driving a voltage level of an output signal toward a power supply voltage (VDD) level according to the levels of the first clock signal and the second clock signal; And
And a first pull-down driving unit and a second pull-down driving unit for driving the voltage level of the output signal toward a ground voltage (VSS) level according to the level of the first clock signal and the second clock signal. The method according to claim 1,
Wherein the first pull-up driver and the second pull-down driver are controlled according to a level of a data signal, and the second pull-up driver and the first pull-down driver are controlled according to a level of an inverted data signal. 3. The method of claim 2,
Wherein the data signal and the inverted data signal are applied to the gate of the NMOS transistor. The method according to claim 1,
The first pull-up driving unit, the second pull-up driving unit, the first pull-down driving unit, and the second pull-down driving unit implement a circuit using a Domino Logic method, And latch a voltage of the particular node according to an up or down transition of a clock signal that arrives thereafter to output a full-swing voltage level. The method according to claim 1,
A multiplexer configured to output a full-swing signal even when the voltage swing level of the incoming data signal is low.

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