CN113489287B - Active parallel current sharing control method for SiC MOSFET modules - Google Patents

Active parallel current sharing control method for SiC MOSFET modules Download PDF

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CN113489287B
CN113489287B CN202110645039.9A CN202110645039A CN113489287B CN 113489287 B CN113489287 B CN 113489287B CN 202110645039 A CN202110645039 A CN 202110645039A CN 113489287 B CN113489287 B CN 113489287B
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sic mosfet
current
cpld
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CN113489287A (en
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文阳
杨媛
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Xian University of Technology
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Xian University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses an active parallel current sharing control method for SiC MOSFET modules, which comprises the steps of connecting two SiC MOSFET modules in parallel, setting four different driving voltages, driving by adopting different driving voltages in the switching-on and switching-off process of the SiC MOSFET modules, obtaining a voltage value proportional to the switching transient current value of the SiC MOSFET modules, inputting the voltage value into a window comparator, judging whether the current edges and the current slopes of the two SiC MOSFET modules connected in parallel are consistent at the switching moment, regulating the current edges and the current slopes of the two SiC MOSFET modules, and finally realizing that the current edges and the current slopes of the two SiC MOSFET modules are consistent at the switching moment. The parallel SiC MOSFET module and the parallel SiC MOSFET module have the advantages that the parallel SiC MOSFET module current sharing effect is improved, and the service life of the parallel SiC MOSFET module is prolonged.

Description

Active parallel current sharing control method for SiC MOSFET modules
Technical Field
The invention belongs to the technical field of SiC MOSFET parallel current sharing, and particularly relates to an active parallel current sharing control method for SiC MOSFET modules.
Background
Currently, the maximum current capacity of a commercial SiC MOSFET module is 300A, and in order to meet the application requirement of a larger current capacity, two methods are generally used for solving the problem: and a plurality of power modules in a single device are output in parallel, and a plurality of devices are output in parallel. In the parallel output method of multiple devices, the devices need to be de-rated, which not only increases the volume and cost of the devices, but also reduces the system efficiency, thereby being not beneficial to exerting various advantages of the SiC MOSFET module. Therefore, increasing current capacity by connecting multiple SiC MOSFET modules in parallel in a single device is the first choice for SiC MOSFET module applications. However, power loop asymmetry, gate drive loop parameter differences, and power module parameter differences may cause dynamic and static imbalance currents in the parallel SiC MOSFET modules and cause unnecessary system failures. In recent years, various current sharing methods, such as a derating method, a power loop impedance balancing method, a grid resistance compensation method, a pulse transformer method and the like, are presented, but all the methods belong to passive current sharing, and on one hand, the methods are accompanied by higher cost and larger device loss, and on the other hand, current sharing parameters are required to be set through experience of people in advance, so that the current sharing effect in parallel module operation is general.
Disclosure of Invention
The invention aims to provide an active parallel current sharing control method for SiC MOSFET modules, which solves the problem that the current sharing effect of the passive current sharing method in the existing SiC MOSFET parallel application is poor.
The technical scheme adopted by the invention is that the active parallel current sharing control method for the SiC MOSFET module comprises the following steps:
step 1: two SiC MOSFET modules are connected in parallel, and the driving voltage of the grid driving unit of the SiC MOSFET modules is set to four different voltages V GG1 、V GG2 、V GG3 、V GG4 Forward voltage V GG1 、 V GG2 Satisfy V GG1 >V GG2 Negative voltage V GG3 、V GG4 Satisfy V GG3 >V GG4 ；
Step 2: in the turn-on process of the SiC MOSFET module, V is adopted in stages GG1 And V GG2 Driving, in the turn-off process of the SiC MOSFET, V is adopted in stages GG3 And V GG4 Driving;
step 3: integrating induced voltages on parasitic inductances of source electrodes of the two SiC MOSFET modules by utilizing an RC integrating circuit to obtain a voltage value proportional to a transient current value of the SiC MOSFET modules;
step 4: respectively inputting the voltage values corresponding to the two SiC MOSFET modules obtained in the step 3 into a window comparator to obtain the starting rising time of the current in the opening process of the two SiC MOSFET modules as T 1 ,T 2 And the moment T when the currents rise to the same value in the switching-on process of the two SiC MOSFET modules 3 ,T 4 Similarly, the voltage values obtained in the step 3 are respectively input into another window comparator to obtain the current starting to drop in the turn-off process of the two SiC MOSFET modules at the time of T 5 ,T 6 And the moment T when the currents rise to the same value in the turn-off process of the two SiC MOSFET modules 7 ,T 8 ；
Step 5: one SiC MOSFET module is selected as a master module, the other SiC MOSFET module is selected as a slave module, the time result obtained in the step 4 is transmitted to a control chip CPLD, and the CPLD judges whether the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching through calculating a signal turning time difference delta T obtained in the step 4;
step 6: the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching, and the two parallel SiC MOSFET modules realize current sharing; and (3) the current edges and the current slopes of the two parallel SiC MOSFET modules are inconsistent, the CPLD adjusts the time of applying different driving voltages in stages according to the judging result obtained in the step (5) in combination with the step (2), the current edges of the slave modules are consistent with the master module, then the current slopes of the slave modules are consistent with the master module, and finally the consistency of the current edges and the current slopes of the two SiC MOSFET modules at the switching moment is realized.
The present invention is also characterized in that,
the step 2 is specifically as follows:
before the turn-on signal arrives, CPLD controls the output voltage of the grid driving unit to be kept at V GG4 The reliable turn-off of the SiC MOSFET is ensured;
when the turn-on signal arrives, the delay time t is elapsed delay1 Rear CPLD controls the output V of the gate driving unit GG1 ；
When the current of the SiC MOSFET module begins to rise, the CPLD controls the output V of the grid driving unit GG2 At a delay time t delay2 After that, CPLD controls the gate driving unit to output V GG1 Until the SiC MOSFET module is fully turned on;
before the turn-off signal arrives, the CPLD controls the output voltage of the grid driving unit to be kept at V GG1 The SiC MOSFET is ensured to be turned on;
when the off signal arrives, the delay time t is elapsed delay3 Rear CPLD controls the output V of the gate driving unit GG4 ；
When the SiC MOSFET current begins to drop, the CPLD controls the gate drive unit output V GG3 At a delay time t delay4 After that, CPLD controls the gate driving unit to output V GG4 Until the SiC MOSFET module is completely turned off.
In the step 5), whether the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching is determined specifically as follows:
setting the oscillation period of the CPLD as T, and calculating the current starting rising time difference delta T obtained in the step 4 by the CPLD in the opening process d,on ＝T 1 -T 2 If DeltaT d,on The slave module is opened after the slave module is opened; if DeltaT d,on The slave module is firstly opened if the value is more than T; if T is less than or equal to DeltaT d,on The current edges of the two SiC MOSFET modules are consistent when the T is less than or equal to T; the CPLD calculates the time difference delta T of the current obtained in the step 4 rising to the same value s,on ＝T 3 -T 4 If DeltaT s,on The current slope of the slave module is smaller; if DeltaT s,on The current slope of the slave module is larger than T; if T is less than or equal to DeltaT s,on The current slopes of the two SiC MOSFET modules are consistent when the T is less than or equal to T;
in the turn-off process, the CPLD calculates the current start rising time difference delta T obtained in the step 4 d,off ＝T 5 -T 6 If DeltaT d,off The slave module is opened after the slave module is opened; if DeltaT d,off The slave module is firstly opened if the value is more than T; if T is less than or equal to DeltaT d,off The current edges of the two SiC MOSFET modules are consistent when the T is less than or equal to T; the CPLD calculates the time difference delta T of the current obtained in the step 4 rising to the same value slope ＝T 7 -T 8 If DeltaT slope The current slope of the slave module is smaller when the slave module is < -T; if DeltaT slope When the current is more than T, the current slope of the slave module is larger; if T is less than or equal to DeltaT slope And when the current slope is less than or equal to T, the current slopes of the two SiC MOSFET modules are identical.
In the step 6, the current edge of the slave module is regulated to be consistent with that of the master module, specifically:
during the on process of the two SiC MOSFET modules, when delta T d,on < -T, will DeltaT d,on Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay1 Reducing DeltaT d,on Outputting time; when DeltaT d,on At > T, deltaT will be d,on Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay1 Increasing DeltaT d,on Outputting time; when-T is less than or equal to delta T d,on When T is less than or equal to T, the CPLD stops the delay time T delay1 Is adjusted.
During the turn-off process of the two SiC MOSFET modules, when delta T d,off With < -T, deltaT d,off Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay2 Reducing DeltaT d,off Outputting time; when DeltaT d,off At > T, deltaT will be d,off Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay2 Increasing DeltaT d,off Outputting time; when-T is less than or equal to delta T d,off When T is less than or equal to T, the CPLD stops the delay time T delay2 Is adjusted.
In the step 6, the current slope of the slave module is regulated to be consistent with that of the master module, specifically:
during the on process of the two SiC MOSFET modules, when delta T s,on With < -T, deltaT s,on Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay3 Reducing DeltaT s,on Outputting time; when DeltaT s,on At > T, the delay time T from the SiC MOSFET will be delay3 Increasing DeltaT s,on Outputting time; when-T is less than or equal to delta T s,on When T is less than or equal to T, the CPLD stops the delay time T delay3 Is adjusted.
During the turn-off process of the two SiC MOSFET modules, when delta T s,off With < -T, deltaT s,off Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay4 Reducing DeltaT s,on Outputting time; when DeltaT s,on At > T, the delay time T from the SiC MOSFET will be delay4 Increasing DeltaT s,on Outputting time; when-T is less than or equal to delta T s,on When T is less than or equal to T, the CPLD stops the delay time T delay4 Is adjusted.
The beneficial effects of the invention are as follows:
according to the active parallel current sharing control method for the SiC MOSFET modules, in the switching transient process of the two parallel SiC MOSFET modules, according to the comparison result of the current information of the master SiC MOSFET module and the slave SiC MOSFET modules, the gate driving voltage of the slave SiC MOSFET modules in parallel is dynamically adjusted, so that the current edge synchronization and the current slope synchronization of the two parallel SiC MOSFET modules are realized, the parallel current sharing effect of the SiC MOSFET modules is improved, and the service life of the parallel SiC MOSFET modules is prolonged.
Drawings
Fig. 1 is a flow chart of an active parallel current sharing control method of a SiC MOSFET module according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the following embodiments.
The invention relates to an active parallel current sharing control method for SiC MOSFET modules, which is shown in figure 1 and comprises the following steps:
step 1: two SiC MOSFET modules are connected in parallel, and the driving voltage of the grid driving unit of the SiC MOSFET modules is set to four different voltages V GG1 、V GG2 、V GG3 、V GG4 Forward voltage V GG1 、 V GG2 Satisfy V GG1 >V GG2 Negative voltage V GG3 、V GG4 Satisfy V GG3 >V GG4 。
Step 2: in the turn-on process of the SiC MOSFET module, V is adopted in stages GG1 And V GG2 Driving, in the turn-off process of the SiC MOSFET, V is adopted in stages GG3 And V GG4 Driving;
the step 2 is specifically as follows:
before the turn-on signal arrives, CPLD controls the output voltage of the grid driving unit to be kept at V GG4 The reliable turn-off of the SiC MOSFET is ensured;
when the turn-on signal arrives, the delay time t is elapsed delay1 Rear CPLD controls the output V of the gate driving unit GG1 ；
When the current of the SiC MOSFET module begins to rise, the CPLD controls the output V of the grid driving unit GG2 At a delay time t delay2 Thereafter, CPLD controls gate drive unit output V GG1 Until the SiC MOSFET module is fully turned on;
before the turn-off signal arrives, the CPLD controls the output voltage of the grid driving unit to be kept at V GG1 The SiC MOSFET is ensured to be turned on;
when the off signal arrives, the delay time t is elapsed delay3 Rear CPLD controls the output V of the gate driving unit GG4 ；
When the SiC MOSFET current begins to drop, the CPLD controls the gate drive unit output V GG3 At a delay time t delay4 After that, CPLD controls the gate driving unit to output V GG4 Until the SiC MOSFET module is completely turned off.
Step 3: and integrating the induced voltages on the parasitic inductances of the source electrodes of the two SiC MOSFET modules by utilizing an RC integrating circuit to obtain a voltage value proportional to the switching transient current value of the SiC MOSFET modules.
Step 4: respectively inputting the voltage values corresponding to the two SiC MOSFET modules obtained in the step 3 into a window comparator to obtain the starting rising time of the current in the opening process of the two SiC MOSFET modules as T 1 ,T 2 And the moment T when the currents rise to the same value in the switching-on process of the two SiC MOSFET modules 3 ,T 4 Similarly, the voltage values obtained in the step 3 are respectively input into another window comparator to obtain the current starting to drop in the turn-off process of the two SiC MOSFET modules at the time of T 5 ,T 6 And the moment T when the currents rise to the same value in the turn-off process of the two SiC MOSFET modules 7 ,T 8 。
Step 5: one SiC MOSFET module is selected as a master module, the other SiC MOSFET module is selected as a slave module, the time result obtained in the step 4 is transmitted to a control chip CPLD, and the CPLD judges whether the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching through calculating a signal turning time difference delta T obtained in the step 4;
in the step 5), whether the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching is determined specifically as follows:
let the oscillation period of the CPLD be T,in the switching-on process, the CPLD calculates the current starting rising time difference delta T obtained in the step 4 d,on ＝T 1 -T 2 If DeltaT d,on The slave module is opened after the slave module is opened; if DeltaT d,on The slave module is firstly opened if the value is more than T; if T is less than or equal to DeltaT d,on The current edges of the two SiC MOSFET modules are consistent when the T is less than or equal to T; the CPLD calculates the time difference delta T of the current obtained in the step 4 rising to the same value s,on ＝T 3 -T 4 If DeltaT s,on The current slope of the slave module is smaller; if DeltaT s,on The current slope of the slave module is larger than T; if T is less than or equal to DeltaT s,on The current slopes of the two SiC MOSFET modules are consistent when the T is less than or equal to T;
in the turn-off process, the CPLD calculates the current start rising time difference delta T obtained in the step 4 d,off ＝T 5 -T 6 If DeltaT d,off The slave module is opened after the slave module is opened; if DeltaT d,off The slave module is firstly opened if the value is more than T; if T is less than or equal to DeltaT d,off The current edges of the two SiC MOSFET modules are consistent when the T is less than or equal to T; the CPLD calculates the time difference delta T of the current obtained in the step 4 rising to the same value slope ＝T 7 -T 8 If DeltaT slope The current slope of the slave module is smaller when the slave module is < -T; if DeltaT slope When the current is more than T, the current slope of the slave module is larger; if T is less than or equal to DeltaT slope And when the current slope is less than or equal to T, the current slopes of the two SiC MOSFET modules are identical.
Step 6: the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching, and the two parallel SiC MOSFET modules realize current sharing; the current edges and the current slopes of the two parallel SiC MOSFET modules are inconsistent, the CPLD adjusts the time of applying different driving voltages in stages according to the judging result obtained in the step 5 and the step 2, the current edges of the slave modules are consistent with the master module, then the current slopes of the slave modules are consistent with the master module, and finally the consistency of the current edges and the current slopes of the two SiC MOSFET modules at the switching moment is realized;
the current edge of the slave module is regulated to be consistent with the master module, specifically:
during the on process of the two SiC MOSFET modules, when delta T d,on < -T, will DeltaT d,on Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay1 Reducing DeltaT d,on Outputting time; when DeltaT d,on At > T, deltaT will be d,on Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay1 Increasing DeltaT d,on Outputting time; when-T is less than or equal to delta T d,on When T is less than or equal to T, the CPLD stops the delay time T delay1 Is adjusted.
During the turn-off process of the two SiC MOSFET modules, when delta T d,off With < -T, deltaT d,off Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay2 Reducing DeltaT d,off Outputting time; when DeltaT d,off At > T, deltaT will be d,off Is stored in a register of the CPLD, and when the next switching period arrives, the delay time t of the SiC MOSFET is reduced delay2 Increasing DeltaT d,off Outputting time; when-T is less than or equal to delta T d,off When T is less than or equal to T, the CPLD stops the delay time T delay2 Is adjusted.
The current slope of the regulating slave module is consistent with that of the master module, and the regulating slave module comprises the following specific steps:
during the on process of the two SiC MOSFET modules, when delta T s,on With < -T, deltaT s,on Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay3 Reducing DeltaT s,on Outputting time; when DeltaT s,on At > T, the delay time T from the SiC MOSFET will be delay3 Increasing DeltaT s,on Outputting time; when-T is less than or equal to delta T s,on When T is less than or equal to T, the CPLD stops the delay time T delay3 Is adjusted.
During the turn-off process of the two SiC MOSFET modules, when delta T s,off With < -T, deltaT s,off Stored in a register of the CPLD, the delay time t from the SiC MOSFET is reached when the next switching period comes delay4 Reducing DeltaT s,on Outputting time; when DeltaT s,on At > T, the delay time T from the SiC MOSFET will be delay4 Increasing DeltaT s,on Time transmissionDischarging; when-T is less than or equal to delta T s,on When T is less than or equal to T, the CPLD stops the delay time T delay4 Is adjusted.

Claims (5)

1. The active parallel current sharing control method for the SiC MOSFET module is characterized by comprising the following steps of:
step 1: two SiC MOSFET modules are connected in parallel, and the driving voltage of the grid driving unit of the SiC MOSFET module is set to four different voltagesV GG1 、V GG2 、V GG3 、V GG4 Forward voltageV GG1 、V GG2 Satisfy the following requirementsV GG1 >V GG2 Negative voltageV GG3 、V GG4 Satisfy the following requirementsV GG3 >V GG4 ；
Step 2: in the process of switching on the SiC MOSFET module, the method adopts the following steps ofV GG1 AndV GG2 driving, in the turn-off process of the SiC MOSFET, the method adopts the following stepsV GG3 AndV GG4 driving;
step 3: integrating induced voltages on parasitic inductances of source electrodes of the two SiC MOSFET modules by utilizing an RC integrating circuit to obtain a voltage value proportional to a transient current value of the SiC MOSFET modules;
step 4: respectively inputting the voltage values corresponding to the two SiC MOSFET modules obtained in the step 3 into a window comparator to obtain the starting rising moments of the currents in the opening process of the two SiC MOSFET modules respectivelyAnd the moment in time when the currents rise to the same value during the switching on of the two SiC MOSFET modules +.>Similarly, the voltage values obtained in the step 3 are respectively input into another window comparator, and the current starting falling moments in the turn-off process of the two SiC MOSFET modules are respectively obtained as +.>And the moment in time when the currents rise to the same value during the switching off of the two SiC MOSFET modules +.>；
Step 5: one SiC MOSFET module is selected as a main module, the other SiC MOSFET module is used as a slave module, the time result obtained in the step 4 is transmitted to a control chip CPLD, and the CPLD calculates the signal turning time difference value obtained in the step 4Judging whether the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching;
step 6: the current edges and the current slopes of the two parallel SiC MOSFET modules are consistent at the moment of switching, and the two parallel SiC MOSFET modules realize current sharing; and (3) the current edges and the current slopes of the two parallel SiC MOSFET modules are inconsistent, the CPLD adjusts the time of applying different driving voltages in stages according to the judging result obtained in the step (5) in combination with the step (2), the current edges of the slave modules are consistent with the master module, then the current slopes of the slave modules are consistent with the master module, and finally the consistency of the current edges and the current slopes of the two SiC MOSFET modules at the switching moment is realized.
2. The active parallel current sharing control method of SiC MOSFET modules according to claim 1, wherein the step 2 specifically comprises:
before the turn-on signal arrives, CPLD controls the output voltage of the grid driving unit to be kept atV GG4 The reliable turn-off of the SiC MOSFET is ensured;
when the turn-on signal arrives, the delay time is elapsedt delay1 Post CPLD control gate drive unit outputV GG1 ；
When the current of the SiC MOSFET module begins to rise, the CPLD controls the output of the grid driving unitV GG2 At a delay time oft delay2 Thereafter, the CPLD controls the gate drive unit outputV GG1 Up to SiThe C MOSFET module is completely conducted;
before the turn-off signal arrives, the CPLD controls the output voltage of the grid driving unit to be kept atV GG1 The SiC MOSFET is ensured to be turned on;
when the off signal arrives, the delay time is elapsedt delay3 Post CPLD control gate drive unit outputV GG4 ；
When the SiC MOSFET current begins to drop, the CPLD controls the gate drive unit outputV GG3 At a delay time oft delay4 Thereafter, the CPLD controls the gate drive unit outputV GG4 Until the SiC MOSFET module is completely turned off.
3. The active parallel current sharing control method of SiC MOSFET modules according to claim 2, wherein the determining in step 5 whether the current edges and the current slopes of the two parallel SiC MOSFET modules are identical at the switching moment is specifically:
setting the oscillation period of the CPLD as T, and calculating the current starting rising time difference value obtained in the step 4 by the CPLD in the opening processIf->Opening the slave module; if->The slave module is firstly opened; if->The current edges of the two SiC MOSFET modules are consistent; CPLD calculates the time difference value of the current obtained in step 4 rising to the same valueIf->The slave current slope is smaller; if->The slave module current slope is larger; if it isThe current slopes of the two SiC MOSFET modules are identical;
in the turn-off process, the CPLD calculates the current starting rising time difference value obtained in the step 4If->Opening the slave module; if->The slave module is firstly opened; if->The current edges of the two SiC MOSFET modules are consistent; CPLD calculates the time difference value of the current obtained in step 4 rising to the same value +.>If->The slave current slope is smaller; if->When the current slope of the slave module is larger; if->And when the current slopes of the two SiC MOSFET modules are identical.
4. The active parallel current sharing control method of the SiC MOSFET module according to claim 3, wherein the adjusting the current edge of the slave module in step 6 is consistent with the master module specifically comprises:
during the on process of the two SiC MOSFET modules, whenWill->Is stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay1 Reduce->Outputting time; when->When it willIs stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay1 Increase->Outputting time; when->When CPLD stops to delay timet delay1 Is adjusted;
during the turn-off process of the two SiC MOSFET modules, whenWhen in use, will->Is stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay2 Reduce->Outputting time; when->When in use, will->Is stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay2 Add->Outputting time; when->When CPLD stops to delay timet delay2 Is adjusted.
5. The active parallel current sharing control method of SiC MOSFET modules according to claim 3, wherein the adjusting the current slope of the slave module in step 6 to be consistent with the master module specifically comprises:
during the on process of the two SiC MOSFET modules, whenWhen in use, will->Is stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay3 Reduce->Outputting time; when->Delay time from SiC MOSFETt delay3 Add->Outputting time; when->When CPLD stops to delay timet delay3 Is adjusted;
during the turn-off process of the two SiC MOSFET modules, whenWhen in use, will->Is stored in a register of the CPLD, and when the next switching period comes, the delay time of the SiC MOSFET is delayedt delay4 Reduce->Outputting time; when->Delay time from SiC MOSFETt delay4 Add->Outputting time; when->When CPLD stops to delay timet delay4 Is adjusted.
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