CN206146994U - Self -adaption sampling circuit, controller and power supply changeover device - Google Patents
Self -adaption sampling circuit, controller and power supply changeover device Download PDFInfo
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- CN206146994U CN206146994U CN201621188378.XU CN201621188378U CN206146994U CN 206146994 U CN206146994 U CN 206146994U CN 201621188378 U CN201621188378 U CN 201621188378U CN 206146994 U CN206146994 U CN 206146994U
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Abstract
The utility model provides a self -adaption sampling circuit, controller and power supply changeover device, the self -adaption sampling circuit includes: pulse generation unit, one end are used for receiving clock control signal, and the control end of the first switch of other end electric connection generates the control end that a single pulse signal exported first switch to at clock control signal's rising edge, first switch, first contact electric connection peak voltage output nodes, second contact ground connection, holding capacitor, one end electric connection peak voltage output nodes, other end ground connection, input voltage follows the unit, and the input is used for receiving input voltage, output electric connection peak voltage output nodes. The utility model discloses realize that accurate sampling obtains the peak voltage signal of voltage on the sampling resistor, can show and improve electric current and precision and the batch uniformity of power of final output to the load.
Description
Technical field
The utility model is related to integrated circuit and drives art field, more particularly to one kind to be applied to voltage sample
The adaptively sampled circuit of power supply change-over device, controller and power supply change-over device.
Background technology
With the fast development of power semiconductor technologies and modern control theory, power supply change-over device, particularly and city
Electricity is joined directly together the power supply change-over device for connecing and popularizes rapidly.Power supply change-over device can will be supplied directly after the power conversion of civil power
Low-voltage load.
With reference to Fig. 1, existing power supply conversion equipment configuration diagram.Controller 12, power tube switching tube MP and magnetic device
Part 13 cooperates, and directly the power of the civil power 10 after the rectification of rectifier bridge 11 is changed to low-voltage load 14.Controller 12 leads to
The sampling resistor R that normal open over-sampling circuit 121 is sampled and power switch pipe MP is in seriesCSOn voltage signal, obtain load 14
On electric current or power information；Then processed by control circuit 122, feed back to drive circuit 123, to control power switch pipe
The opening and closing of MP, the electric current or power that realization controls to load on 14 is a preset value.Therefore, sample circuit 121 is in electricity
It is a very important functional module in supply changeover device, the precision of sample circuit 121 determines that whole power supply change-over device is defeated
The precision of the voltage, electric current or the power that go out.
With reference to Fig. 2, existing sample circuit schematic diagram.Existing sample circuit 121, including clock control signal CLK, sampling
First switch SW1, holding capacitor C1.Sample circuit 121 is by the sampling resistor R that samplesCSOn voltage VCS, obtain peak value electricity
Pressure VCSPK.When the clock control signal CLK of the output of control circuit 122 is high level, the voltage signal V on sampling resistor RcsCS
Directly holding capacitor C1 is charged as input voltage, the voltage and input voltage V on electric capacity C1CSIt is equal；When clock control letter
When number CLK becomes low level, it is V that holding capacitor C1 keeps input voltage this momentCSPK, and as sampling and outputting voltage VOOutput
To control circuit 122.
Please also refer to Fig. 1-3, wherein Fig. 3 is the key point oscillogram of existing sample circuit shown in Fig. 2.From shown in Fig. 1
Power supply change-over device configuration diagram can be seen that after clock control signal CLK becomes low level from high level, in addition it is also necessary to Jing
Overdrive circuit 123, and inherent delay Tds of the power switch pipe MP from opening to closed mode；Therefore input voltage VCS
It is not after clock control signal CLK becomes low level, 0 to be become at once.As seen from Figure 3, due to inherent delay Td
Presence, cause sampling and outputting voltage VOIt is not the voltage V in each switch periods on sampling resistor RCSCSReal peak
Threshold voltage VCSPK。
In order to solve the voltage sample error that inherent delay Td brings, existing sample circuit can also adopt the side of time delay sampling
Method.But the conforming problem of delay time can bring the conforming problem of output batch again.Particularly isolation high power because
Number circuits in, system in each switch periods, VCSThe slope and peak value of voltage is all different, so time delay sampling can not be solved
The certainly linear regulation of output loading and in batches conforming problem.
Utility model content
The purpose of this utility model is exist by voltage sample institute for the sample circuit in existing power supply conversion equipment
The linear regulation of output loading that causes and the conforming problem of batch, there is provided a kind of adaptively sampled circuit, controller and
Power supply change-over device, realizes that accurate sampling obtains the peak voltage signal of voltage on sampling resistor, can significantly improve final defeated
The electric current gone out in load and the precision of power and batch uniformity.
For achieving the above object, the utility model provides a kind of adaptively sampled circuit, including：Pulse signal generating unit,
First switch, holding capacitor and following by inputting voltages unit；The pulse signal generating unit, one end is used to receive clock control letter
Number, the other end is electrically connected with the control end of the first switch, and the pulse signal generating unit is in the upper of the clock control signal
Rise and exported to the control end of the first switch along one single pulse signal of generation；The first switch, the first contact is electrically connected with
Crest voltage output node, the second contact ground connection；The holding capacitor, one end is electrically connected with the crest voltage output node,
The other end is grounded；The following by inputting voltages unit, input is used for receives input voltage, and output end is electrically connected with the peak value
Voltage output node；Export to the control end of the first switch when the pulse signal generating unit generates the single pulse signal
Afterwards, the first switch turns on and the holding capacitor is discharged；Institute is closed when the single pulse signal becomes low level
After stating first switch, the following by inputting voltages unit is in the input voltage more than or equal to the peak value electricity in the holding capacitor
During pressure, the crest voltage is kept to follow the change of the input voltage and export by the crest voltage output node,
When the input voltage is less than the crest voltage, the following by inputting voltages unit and the crest voltage output node are disconnected
Between connection, the holding capacitor keeps crest voltage now as maximum peak voltage and to pass through the crest voltage defeated
Egress is exported.
For achieving the above object, the utility model additionally provides a kind of controller for power conversion device, the control
Device processed includes：Control circuit, drive circuit and adaptively sampled circuit described in the utility model；The control circuit difference
It is electrically connected with the adaptively sampled circuit and the drive circuit, for receiving output voltage, and according to receiving
Output voltage generates clock control signal；The adaptively sampled circuit is used to receive the clock control signal, and according to institute
The input voltage for stating the clock control signal sampling controller obtains crest voltage as output voltage output；The control electricity
Road further generates switch controlling signal and exports to the drive circuit according to the output voltage for receiving；The drive circuit is used
In the opening and closing of the power switch pipe for controlling to be electrically connected with load according to the switch controlling signal.
For achieving the above object, the utility model additionally provides a kind of power supply change-over device, including electrical with AC power
The rectifier bridge of connection and the magnetic device being electrically connected with the rectifier bridge and load, described device also includes：Power switch
Pipe, voltage sample module and controller described in the utility model；The control end of the power switch pipe is electrically connected with described
Controller, the first contact is electrically connected with load, and the second contact is electrically connected with the voltage sample module；The voltage sample mould
Block, for generating the sampled voltage within a sampling period, and is sent to the described adaptive of the controller as input voltage
Answer sample circuit；Input voltage described in the adaptively sampled circuit sampling obtains crest voltage and exports as output voltage；
The control circuit of the controller generates switch controlling signal according to the output voltage, by described in the controller
Drive circuit controls the opening and closing of the power switch pipe, so as to realize the constant current to the load or invariable power control
System.
For achieving the above object, the utility model additionally provides a kind of adaptively sampled method, using the utility model institute
The adaptively sampled circuit stated, it is characterised in that comprise the steps：1) adaptively sampled circuit receives clock control signal,
And the rising edge in the clock control signal generates a single pulse signal, turns on the first switch in parallel with holding capacitor, with
The holding capacitor is set to be discharged；2) first switch is closed by the single pulse signal, will be described adaptively sampled
The input voltage that circuit is received is exported in the holding capacitor；3) judge the input voltage whether more than or equal to the guarantor
The crest voltage on electric capacity is held, if execution step 4), otherwise execution step 5)；4) crest voltage is kept to follow described defeated
Enter the change of voltage, and exported by the crest voltage output node；5) the described defeated of the adaptively sampled circuit is disconnected
Enter the connection between voltage follow unit and the crest voltage output node of the adaptively sampled circuit, the holding electricity
Hold and keep crest voltage now to export as maximum peak voltage and by the crest voltage output node.
The utility model has the advantage of：Can be with adaptive input by adaptively sampled circuit described in the utility model
The change of voltage, when input voltage is not less than output voltage, keeps its output voltage to follow the change of input voltage；Exist simultaneously
When input voltage is less than output voltage, the annexation between adaptive disconnection output voltage and input voltage.Can be accurate
The crest voltage and maximum peak voltage that sample input voltage, and uncontrolled device internal delay time and input signal
The impact of voltage slope.
Description of the drawings
Fig. 1, existing power supply conversion equipment configuration diagram；
Fig. 2, existing sample circuit schematic diagram；
Fig. 3 is the key point oscillogram of existing sample circuit shown in Fig. 2；
Fig. 4, power supply change-over device configuration diagram described in the utility model；
Fig. 5, the schematic diagram of adaptively sampled circuit framework described in the utility model；
Fig. 6 is the key point oscillogram of sample circuit described in the utility model shown in Fig. 5；
Fig. 7, the schematic diagram of adaptively sampled circuit first embodiment described in the utility model；
Fig. 8, the schematic diagram of adaptively sampled circuit second embodiment described in the utility model；
Fig. 9, the flow chart of adaptively sampled method described in the utility model.
Specific embodiment
Below in conjunction with the accompanying drawings to the utility model provide adaptively sampled circuit, adaptively sampled method, controller and
Power supply change-over device elaborates.
With reference to Fig. 4, power supply change-over device configuration diagram described in the utility model.Described power supply change-over device bag
Include：The rectifier bridge 41 being electrically connected with AC power 40 and the magnetic device 43 being electrically connected with the rectifier bridge 41 and negative
44 are carried, described power supply change-over device also includes：Power switch pipe MP, voltage sample module 45 and controller 42.Wherein, lead to
Cooperating for controller 42, power tube switching tube MP and magnetic device 43 is crossed, directly will be handed over after the rectification of rectifier bridge 41
The power of stream power supply 40 is changed to load 44.The AC power 40 can be civil power；The magnetic device 43 can be inductance
Or transformer etc..
The input of the rectifier bridge 41 is electrically connected with AC power 40, for the alternating current for exporting AC power 40
Rectification is direct current.Rectifier bridge 41 can be the full-bridge rectifier using four diode compositions.The output end of rectifier bridge 41 can
To set up a filtration module (not shown), direct current is filtered.
The controller 42 includes：Adaptively sampled circuit 421, control circuit 422 and drive circuit 423.The control
Circuit processed 422 is electrically connected with respectively with the adaptively sampled circuit 421 and the drive circuit 423, for receiving output
Voltage VO, and according to the output voltage V for receivingOGenerate clock control signal CLK.The adaptively sampled circuit 421 is used to connect
Receive the clock control signal CLK, and the input voltage V of the controller 42 of sampling according to the clock control signal CLKCSObtain
Take crest voltage VCSPKAs output voltage VOOutput.The control circuit 422 is further according to the output voltage V for receivingOIt is raw
Export to the drive circuit 24 into switch controlling signal.The drive circuit 423 is used for according to the switch controlling signal control
The opening and closing of the power switch pipe MP that system is electrically connected with load 44.For example, the drive circuit 423 is according to switch control rule
NGATE control signals control in signal is opened with the power switch pipe MP that load 44 is electrically connected with.
The control end of the power switch pipe MP is electrically connected with the controller 42, and first contact of MP is electrical with load 44
Connection, second contact of MP is electrically connected with the voltage sample module 45.
The voltage sample module 45, for generating the sampled voltage within a sampling period, and as input voltage VCS
It is sent to the adaptively sampled circuit 421 of the controller 42.Optionally, the voltage sample module 45 is to open with the power
Close the sampling resistor Rcs that second contact of pipe MP is electrically connected with.Sampling resistor Rcs pass through the sampling power switch pipe MP the
The electric current of two point, generates sampled voltage (the i.e. sampling resistor R within a sampling periodCSOn voltage VCS)。
The described adaptively sampled circuit 421 of the controller 42 is sampled the input voltage VCSObtain crest voltage VCSPK
And export as output voltage VO.The control circuit of the controller 42 is according to the output voltage VOGenerate switch controlling signal,
The opening and closing of the power switch pipe MP are controlled by the drive circuit 423 of the controller 42, so as to realize to described
The constant current of load 44 or power limitation control.Because the adaptively sampled circuit 421 can accurately sample the controller 42
Input voltage VCSObtain crest voltage VCSPK, export to the electric current and power loaded on 44 and follow crest voltage V automaticallyCSPK
Change and change, the precision and batch uniformity of electric current and power of the final output to load 44 can be significantly improved.
Used as preferred embodiment, the controller 42 further includes output buffer 424, the output buffering
Circuit 422 is electrically connected with respectively with the adaptively sampled circuit 421 and the control circuit 422, for will be described adaptive
The crest voltage V for answering sample circuit 421 to obtainCSPKAs output voltage V after bufferingOExport to the control circuit 422.
Controller described in the utility model 42 is in series by the sampling of adaptively sampled circuit 421 with power switch pipe MP
Voltage sample module 45 input voltage VCS, obtain the electric current or power information in load 44；Then control circuit 422 is passed through
Process, feed back to drive circuit 423, to control the opening and closing of power switch pipe MP, realize the electric current in control load 44
Or power is a preset value.And, the voltage sample module 45 that the adaptively sampled circuit 421 can accurately sample is transmitted
To the input voltage V of the controller 42CSCrest voltage VCSPK is obtained, the electric current and power exported in load 44 is automatic
Follow crest voltage VCSPKChange and change, the precision of electric current and power of the final output to load 44 can be significantly improved
And batch uniformity.
With reference to Fig. 5, the schematic diagram of adaptively sampled circuit framework described in the utility model.Described adaptively sampled electricity
Road 421 includes：Pulse signal generating unit 51, first switch SW1, holding capacitor C1 and following by inputting voltages unit 52.
The pulse signal generating unit 51, one end is used to receive clock control signal CLK, and the other end is electrically connected with described first
The control end of switch SW1.The pulse signal generating unit 51 generates pulse letter in the rising edge of the clock control signal CLK
Number CLKP is exported to the control end of first switch SW1, and the voltage in holding capacitor C1 is carried out into electric discharge clearing.Described
One switch SW1, the first contact is electrically connected with crest voltage output node, the second contact ground connection；First switch SW1 adopts switching tube
Realize, switching tube can be the transistor such as metal-oxide-semiconductor or diode, triode.The holding capacitor, one end is electrically connected with the peak
Threshold voltage output node Q, other end ground connection.The following by inputting voltages unit 52, input is used for receives input voltage VCS, it is defeated
Go out end and be electrically connected with the crest voltage output node Q.
Export to the control of first switch SW1 when the pulse signal generating unit 51 generates the single pulse signal CLKP
Behind end, first switch SW1 turns on and holding capacitor C1 is discharged.When the single pulse signal CLKP becomes low
Level is closed after first switch SW1, and the following by inputting voltages unit 52 is by the input voltage VCSExport the guarantor
Hold on electric capacity C1；The following by inputting voltages unit 52 is in the input voltage VCSMore than or equal to the peak in holding capacitor C1
Threshold voltage VCSPKWhen, keep the crest voltage VCSPKFollow the input voltage VCSChange, and by the crest voltage
Output node Q is exported；The following by inputting voltages unit 52 is in the input voltage VCSLess than the crest voltage VCSPKWhen, break
The connection between the following by inputting voltages unit 52 and the crest voltage output node Q is opened, holding capacitor C1 keeps
Crest voltage V nowCSPKExport as maximum peak voltage and by the crest voltage output node Q.
Please also refer to Fig. 5-6, wherein, Fig. 6 is the key point waveform of sample circuit described in the utility model shown in Fig. 5
Figure.The T1 stages：Pulse signal generating unit 51 receives the input of clock control signal CLK, while exporting one and clock control signal
The related single pulse signal CLKP of CLK rising edges, the signal is discharged holding capacitor C1 by first switch SW1.T2 ranks
Section：After single pulse signal CLKP becomes low level, following by inputting voltages unit 52 is by the input voltage V of controller 42CSIt is defeated
Go out in holding capacitor C1, voltage (the i.e. crest voltage V in this stage holding capacitor C1CSPK) input voltage V is followed completelyCS
Rising and raise.The T3 stages：After clock control signal CLK becomes low level from high level, due to the drive of controller 42
The closing time delay (Td) of dynamic circuit 423 and power switch MP, input voltage VCSContinue to raise, while the electricity in holding capacitor C1
Pressure is also synchronous to follow rising.The T4 stages：When drive circuit 423 time delay and power tube switch MP closing time delay terminate with
Afterwards, input voltage VCS0 is quickly turned to, due to input voltage VCSLess than the voltage in holding capacitor C1；Now, input voltage with
With unit 52 by adaptive disconnection and the connection of holding capacitor C1, the voltage kept in holding capacitor C1 will be input voltage VCS
Maximum peak voltage VCSPK, until the single pulse signal of next clock control signal CLK generations is by holding capacitor C1
Voltage carries out electric discharge clearing.
Adaptively sampled circuit described in the utility model can be not low in input voltage with the change of adaptive input voltage
When output voltage, its output voltage is kept to follow the change of input voltage；Simultaneously when input voltage is less than output voltage, from
The annexation disconnected between output voltage and input voltage of adaptation.The crest voltage of input voltage can accurately be sampled
And maximum peak voltage, and the impact of uncontrolled device internal delay time and applied signal voltage slope.
With reference to Fig. 7, the schematic diagram of adaptively sampled circuit first embodiment described in the utility model.The input voltage
Unit 52 is followed to include the first error amplifier OP1 and second switch.The first error amplifier OP1, first input end is used
In the reception input voltage VCS, the second input electric connection crest voltage output node Q, output end electric connection institute
State the control end of second switch.The second switch, the first contact is electrically connected with a power supply VCC, and the second contact is electrically connected with institute
State crest voltage output node Q.As the input voltage VCSMore than or equal to the crest voltage V in holding capacitor C1CSPKWhen,
The first error amplifier OP1 and second switch composition negative feedback control loop so that the crest voltage VCSPKWith
With the input voltage VCSChange；As the input voltage VCSLess than the crest voltage VCSPKWhen, first error is put
Big device OP1 output control signals turn off the second switch so that the following by inputting voltages unit 52 and the crest voltage
Connection between output node Q disconnects.
In the present embodiment, the second switch is p-type metal-oxide-semiconductor MP1；The grid of MP1 is electrically connected with first error
The output end of amplifier OP1, the source electrode of MP1 is electrically connected with a power supply VCC, and the drain electrode electric connection crest voltage of MP1 is defeated
Egress Q.The inverting input of the first error amplifier OP1 and input voltage VCSCoupling, in-phase input end is defeated with crest voltage
Egress Q.As the input voltage V of the following by inputting voltages unit 52CSMore than or equal to the crest voltage in holding capacitor C1
VCSPKWhen, the negative feedback control loop of the first error amplifier OP1 and p-type metal-oxide-semiconductor MP1 compositions will force crest voltage VCSPKIt is complete
Input voltage V is followed entirelyCSRising and raise.As the input voltage V of the following by inputting voltages unit 52CSLess than peak value electricity
Pressure VCSPKWhen, the first error amplifier OP1 output high level makes p-type metal-oxide-semiconductor MP1 be in cut-off state so that by OP1 and MP1
The adaptive disconnection crest voltage V of negative feedback control loop of compositionCSPKWith input voltage VCSBetween annexation (disconnect
Connection between the following by inputting voltages unit 52 and the crest voltage output node Q), will keep this in holding capacitor C1
When input voltage VCSMaximum peak voltage VCSPK。
Preferably, the crest voltage V of the output of adaptively sampled circuit 421CSPKIt is slow further across output buffer 424
As output voltage V after punchingOExport to control circuit 422.In the present embodiment, the output buffer 424 can include
Second error amplifier OP2；The first input end (being in the present embodiment in-phase input end) of the second error amplifier OP2
It is electrically connected with the crest voltage output node Q of the adaptively sampled circuit, the second input is (in the present embodiment for anti-
To input) with output end coupling after be electrically connected to control circuit 422.
With reference to Fig. 8, the schematic diagram of adaptively sampled circuit second embodiment described in the utility model.It is real with shown in Fig. 7
The difference for applying example is that in the present embodiment, the second switch is N-type metal-oxide-semiconductor MN1；The grid of MN1 is electrically connected with institute
The output end of the first error amplifier OP1 is stated, the source electrode of MN1 is electrically connected with the crest voltage output node Q, the drain electrode of MN1
It is electrically connected with a power supply VCC.First error amplifier OP1 and N-type metal-oxide-semiconductor MN1 constitutes negative feedback control loop.
In other embodiments, the second switch can also be triode.Such as NPN type triode or positive-negative-positive
Triode, to constitute negative feedback control loop with the first error amplifier OP1.Specific circuit connecting mode can be with reference to NPN type
Triode or PNP type triode self character, and connected mode accesses negative feedback control loop with reference to shown in Fig. 7 or Fig. 8, this
Place repeats no more.
With reference to Fig. 9, the flow chart of adaptively sampled method described in the utility model.Described adaptively sampled method is adopted
With adaptively sampled circuit described in the utility model, comprise the steps：S91：Adaptively sampled circuit receives clock control
Signal, and the rising edge in the clock control signal generates a single pulse signal, turns on first in parallel with holding capacitor and opens
Close, so that the holding capacitor is discharged；S92：The first switch is closed by the single pulse signal, will be described adaptive
The input voltage that sample circuit is received is answered to export in the holding capacitor；S93：Judge whether the input voltage is more than
Crest voltage in the holding capacitor, if execution step S94, otherwise execution step S95；S94：Keep the peak value electricity
Pressure follows the change of the input voltage, and is exported by the crest voltage output node；S95：Disconnect the self adaptation to adopt
Between the following by inputting voltages unit of sample circuit and the crest voltage output node of the adaptively sampled circuit
Connection, holding capacitor holding crest voltage now is as maximum peak voltage and by the crest voltage output node
Output.
S91：Adaptively sampled circuit receives clock control signal, and the rising edge in the clock control signal generates one
Single pulse signal, turns on the first switch in parallel with holding capacitor, so that the holding capacitor is discharged.
Please also refer to Fig. 5, export to described when the pulse signal generating unit 51 generates the single pulse signal CLKP
After the control end of one switch SW1, first switch SW1 turns on and holding capacitor C1 is discharged.
S92：The first switch is closed by the single pulse signal, by the adaptively sampled circuit receive it is defeated
Enter voltage output to the holding capacitor.
After the single pulse signal CLKP becomes low level closes first switch SW1, the following by inputting voltages
Unit 52 is by the input voltage VCSExport in holding capacitor C1.
Wherein, further include before step S92：By the voltage sample being electrically connected with the adaptively sampled circuit
Module generates the sampled voltage within a sampling period, and is sent to the adaptively sampled circuit as input voltage.
S93：Whether the input voltage is judged more than or equal to the crest voltage in the holding capacitor, if execution step
S94, otherwise execution step S95；S94：The crest voltage is kept to follow the change of the input voltage, and by the peak value
Voltage output node is exported；S95：Disconnect the following by inputting voltages unit and the self adaptation of the adaptively sampled circuit
Connection between the crest voltage output node of sample circuit, holding capacitor holding crest voltage now is used as most
Big crest voltage is simultaneously exported by the crest voltage output node.
The following by inputting voltages unit 52 is in the input voltage VCSMore than or equal to the peak value in holding capacitor C1
Voltage VCSPKWhen, keep the crest voltage VCSPKFollow the input voltage VCSChange, it is and defeated by the crest voltage
Egress Q is exported；The following by inputting voltages unit 52 is in the input voltage VCSLess than the crest voltage VCSPKWhen, disconnect
Connection between the following by inputting voltages unit 52 and the crest voltage output node Q, holding capacitor C1 keeps this
When crest voltage VCSPKExport as maximum peak voltage and by the crest voltage output node Q.
Preferably, further include after step S95：According to the output voltage life of crest voltage output node output
The opening and closing of the power switch pipe for controlling to be electrically connected with load into switch controlling signal, so as to realize to the load
Constant current or power limitation control.
That is, the aforesaid controller 42 of the utility model is by the sampling of adaptively sampled circuit 421 and power switch pipe MP
The input voltage V of the voltage sample module 45 being in seriesCS, obtain the electric current or power information in load 44；Then by control
Circuit 422 is processed, and feeds back to drive circuit 423, to control the opening and closing of power switch pipe MP, is realized in control load 44
Electric current or power be a preset value.And, the adaptively sampled circuit 421 can accurately sample the voltage sample module
The 45 input voltage V for being sent to the controller 42CSCrest voltage VCSPK is obtained, electric current and work(in load 44 is exported
Rate follows crest voltage V automaticallyCSPKChange and change, electric current and power of the final output to load 44 can be significantly improved
Precision and batch uniformity.
The above is only preferred embodiment of the present utility model, it is noted that for the common skill of the art
Art personnel, on the premise of without departing from the utility model principle, can also make some improvements and modifications, these improvements and modifications
Also should be regarded as protection domain of the present utility model.
Claims (12)
1. a kind of adaptively sampled circuit, it is characterised in that include：Pulse signal generating unit, first switch, holding capacitor and defeated
Enter voltage follow unit；
The pulse signal generating unit, one end is used to receive clock control signal, and the other end is electrically connected with the control of the first switch
End processed, the pulse signal generating unit generates a single pulse signal and exports to described first in the rising edge of the clock control signal
The control end of switch；
The first switch, the first contact is electrically connected with crest voltage output node, the second contact ground connection；
The holding capacitor, one end is electrically connected with the crest voltage output node, other end ground connection；
The following by inputting voltages unit, input is used for receives input voltage, and it is defeated that output end is electrically connected with the crest voltage
Egress；
After the pulse signal generating unit generates the single pulse signal exports the control end to the first switch, described first
Switch conduction causes the holding capacitor to be discharged；The first switch is closed when the single pulse signal becomes low level
Afterwards, the following by inputting voltages unit keeps when the input voltage is more than or equal to the crest voltage in the holding capacitor
The crest voltage is followed the change of the input voltage and is exported by the crest voltage output node, in the input electricity
Force down when the crest voltage, disconnect the company between the following by inputting voltages unit and the crest voltage output node
Connect, the holding capacitor keeps crest voltage now as maximum peak voltage and defeated by the crest voltage output node
Go out.
2. adaptively sampled circuit according to claim 1, it is characterised in that the following by inputting voltages unit includes the
One error amplifier and second switch；
First error amplifier, first input end is used to receive the input voltage, and the second input is electrically connected with described
Crest voltage output node, output end is electrically connected with the control end of the second switch；
The second switch, the first contact is electrically connected with a power supply, and the second contact is electrically connected with the crest voltage output node；
When the input voltage is more than or equal to the crest voltage, first error amplifier and the second switch are constituted
Negative feedback control loop so that the crest voltage follows the change of the input voltage；When the input voltage is less than described
During crest voltage, the first error amplifier output control signal turns off the second switch so that the input voltage with
Disconnect with the connection between unit and the crest voltage output node.
3. adaptively sampled circuit according to claim 2, it is characterised in that the second switch is p-type metal-oxide-semiconductor；Institute
The grid for stating p-type metal-oxide-semiconductor is electrically connected with the output end of first error amplifier, and the source electrode of the p-type metal-oxide-semiconductor is electrically connected with
One power supply, the drain electrode of the p-type metal-oxide-semiconductor is electrically connected with the crest voltage output node.
4. adaptively sampled circuit according to claim 2, it is characterised in that the second switch is N-type metal-oxide-semiconductor；Institute
The grid for stating N-type metal-oxide-semiconductor is electrically connected with the output end of first error amplifier, and the source electrode of the N-type metal-oxide-semiconductor is electrically connected with
The crest voltage output node, the drain electrode of the N-type metal-oxide-semiconductor is electrically connected with a power supply.
5. adaptively sampled circuit according to claim 2, it is characterised in that the second switch is triode.
6. a kind of controller for power conversion device, it is characterised in that the controller includes：Control circuit, driving electricity
Adaptively sampled circuit described in road and any one of Claims 1 to 5；
The control circuit is electrically connected with respectively with the adaptively sampled circuit and the drive circuit, for receiving output
Voltage, and clock control signal is generated according to the output voltage for receiving；
The adaptively sampled circuit is used to receive the clock control signal, and according to clock control signal sampling
The input voltage of controller obtains crest voltage and exports as output voltage；
The control circuit further generates switch controlling signal and exports to the drive circuit according to the output voltage for receiving；
The drive circuit is used for the unlatching of the power switch pipe for controlling to be electrically connected with load according to the switch controlling signal
And closing.
7. controller according to claim 6, it is characterised in that the controller further includes output buffer；
The output buffer is electrically connected with respectively with the adaptively sampled circuit and the control circuit, for by institute
State and exported to the control circuit as output voltage after the crest voltage buffering that adaptively sampled circuit is obtained.
8. controller according to claim 7, it is characterised in that the output buffer includes that the second error is amplified
Device；
The crest voltage that the first input end of second error amplifier is electrically connected with the adaptively sampled circuit is defeated
Egress, after the second input and output end coupling the control circuit is electrically connected to.
9. a kind of power supply change-over device, electrically connects including the rectifier bridge being electrically connected with AC power and with the rectifier bridge
The magnetic device for connecing and load, it is characterised in that described device also includes：Power switch pipe, voltage sample module and right
Require the controller described in 6；
The control end of the power switch pipe is electrically connected with the controller, and the first contact is electrically connected with load, the second contact
It is electrically connected with the voltage sample module；
The voltage sample module, for generating the sampled voltage within a sampling period, and is sent to institute as input voltage
State the described adaptively sampled circuit of controller；
Input voltage described in the adaptively sampled circuit sampling obtains crest voltage and exports as output voltage；
The control circuit of the controller generates switch controlling signal according to the output voltage, by the controller
The drive circuit controls the opening and closing of the power switch pipe, so as to realize the constant current to the load or invariable power
Control.
10. power supply change-over device according to claim 9, it is characterised in that the controller further includes that output is slow
Rush circuit；
The output buffer is electrically connected with respectively with the adaptively sampled circuit and the control circuit, for by institute
State and exported to the control circuit as output voltage after the crest voltage buffering that adaptively sampled circuit is obtained.
11. power supply change-over devices according to claim 10, it is characterised in that the output buffer is missed including second
Difference amplifier；
The crest voltage that the first input end of second error amplifier is electrically connected with the adaptively sampled circuit is defeated
Egress, after the second input and output end coupling the control circuit is electrically connected to.
12. power supply change-over devices according to claim 9, it is characterised in that the voltage sample module is and the work(
The sampling resistor that second contact of rate switching tube is electrically connected with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621188378.XU CN206146994U (en) | 2016-11-04 | 2016-11-04 | Self -adaption sampling circuit, controller and power supply changeover device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621188378.XU CN206146994U (en) | 2016-11-04 | 2016-11-04 | Self -adaption sampling circuit, controller and power supply changeover device |
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| CN206146994U true CN206146994U (en) | 2017-05-03 |
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|---|---|---|---|
| CN201621188378.XU Withdrawn - After Issue CN206146994U (en) | 2016-11-04 | 2016-11-04 | Self -adaption sampling circuit, controller and power supply changeover device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106501575A (en) * | 2016-11-04 | 2017-03-15 | 上海晶丰明源半导体有限公司 | Adaptively sampled circuit, the method for sampling, controller and power supply change-over device |
| CN107086639A (en) * | 2017-06-09 | 2017-08-22 | 上海裕芯电子科技有限公司 | The dead circuit of electric lock and method on a kind of elimination lithium battery protection circuit |
-
2016
- 2016-11-04 CN CN201621188378.XU patent/CN206146994U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106501575A (en) * | 2016-11-04 | 2017-03-15 | 上海晶丰明源半导体有限公司 | Adaptively sampled circuit, the method for sampling, controller and power supply change-over device |
| CN106501575B (en) * | 2016-11-04 | 2023-07-11 | 上海晶丰明源半导体股份有限公司 | Self-adaptive sampling circuit, sampling method, controller and power supply conversion device |
| CN107086639A (en) * | 2017-06-09 | 2017-08-22 | 上海裕芯电子科技有限公司 | The dead circuit of electric lock and method on a kind of elimination lithium battery protection circuit |
| CN107086639B (en) * | 2017-06-09 | 2023-06-06 | 上海裕芯电子科技有限公司 | Circuit and method for eliminating electric lock on lithium battery protection circuit |
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