CN102904443B - Dc-dc converter and voltage conversion method thereof - Google Patents
Dc-dc converter and voltage conversion method thereof Download PDFInfo
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- CN102904443B CN102904443B CN201210198967.6A CN201210198967A CN102904443B CN 102904443 B CN102904443 B CN 102904443B CN 201210198967 A CN201210198967 A CN 201210198967A CN 102904443 B CN102904443 B CN 102904443B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention provides a direct current-direct current converter and a voltage conversion method thereof. The DC-DC converter can increase the frequency of the pulse width modulation signal and reduce the pulse width of the pulse width modulation signal when the load is too light, so as to prevent the frequency of the pulse width modulation signal from falling into an audio frequency range which can be received by human ears, and simultaneously keep high conversion efficiency.
Description
Technical field
The invention relates to a kind of DC-DC converter, and relate to a kind of DC-DC converter and voltage conversion method thereof of pulse duration of adjustable pulse width modulating signal especially.
Background technology
As everyone knows, the operating voltage that central processing unit (CPU) in computer system, dynamic random access memory (DRAM), drawing wafer (graphic chip), wafer set (chip set) use is neither identical, therefore, many DC-DC converters are needed to be converted into the operating voltage needed for each element in order to the DC input voitage (such as 19V) provided by power supply unit in computer system.Constant on-time (Constant On Time, COT) pressurizer is a kind of DC-DC converter.Generally speaking, when feedback voltage is less than reference voltage, constant on-time pressurizer can within a fixed cycle the main switch of conducting one, and the not turn-on cycle of the main switch of adjustable, can provide stable output voltage.
When the load variations of constant on-time pressurizer is violent, the frequency of operation of pulse width modulation (Pulse Width Modulation, the PWM) signal of the constant on-time pressurizer of control also can produce corresponding change.For example, when the load of constant on-time pressurizer lightens, the frequency of pulse width modulating signal reduces, and each interpulse distance becomes large.When the load of constant on-time pressurizer become very light time, will the frequency of pulse width modulating signal be made lower than 25kHz, frequency now starts to enter within the receivable audiorange of people's ear.Thus, will user be made to occur that noise disturbs when using electronic product (such as mobile phone, computer or the walkman etc.) of various application constant on-time pressurizer, and then have influence on the using character of electronic product.
Summary of the invention
The invention provides a kind of DC-DC converter and voltage conversion method thereof, when not affecting conversion efficiency, the audiorange that the frequency of operation of pulse width modulating signal can receive higher than people's ear can be kept.
The present invention proposes a kind of DC-DC converter, and it comprises adjusting module, output module and control module.Adjusting module exports second pulse width modulating signal with constant on-time according to the output voltage of the first pulse width modulating signal and DC-DC converter.Output module couples the input voltage of adjusting module, earthed voltage and DC-DC converter, reacts the second pulse width modulating signal and switches earthed voltage and input voltage, with the switching of corresponding output module, input voltage is converted to output voltage.Control module couples adjusting module and output module, detect the frequency of the second pulse width modulating signal, when the frequency of the second pulse width modulating signal is lower than a predeterminated frequency, control output module and reduce output voltage until rising edge appears in the second pulse width modulating signal, and control the pulse duration that adjusting module reduces the second pulse width modulating signal.
In one embodiment of this invention, above-mentioned output module comprises inductance, switch unit and driver element.The first end of inductance exports output voltage.Switch unit couples the second end of inductance, input voltage and earthed voltage.Driver element couples adjusting module, control module and switch unit, controls switch unit switch input voltage and earthed voltage according to the second pulse width modulating signal, and then exports output voltage at the first end of inductance.
In one embodiment of this invention, above-mentioned switch unit comprises the first transistor and transistor seconds.The first transistor and transistor seconds are serially connected between input voltage and earthed voltage, the grid of the first transistor and transistor seconds couples driver element, the common joint of the first transistor and transistor seconds couples the second end of inductance, the conducting state of the first transistor and transistor seconds is controlled by driver element, driver element also forces conducting transistor seconds according to a priority mechanism and control signal, until next first pulse width modulating signal produces ahead of time.When the frequency of the second pulse width modulating signal is lower than predeterminated frequency, driver element conducting transistor seconds.
In one embodiment of this invention, output module in above-mentioned DC-DC converter also comprises a current detecting unit, it couples driver element, detect the electric current on inductance, when the electric current on inductance reduces to zero, driver element closes transistor seconds, and when the frequency of the second pulse width modulating signal reduces to zero lower than electric current during predeterminated frequency and on inductance, driver element utilizes priority mechanism pressure conducting transistor seconds.
In one embodiment of this invention, above-mentioned control module comprises frequency detecting unit and reduction control unit.Frequency detecting unit detects the transition time point of the first pulse width modulating signal or the rising edge of the second pulse width modulating signal within each signal period, when the rise edge delay of the first pulse width modulating signal or the second pulse width modulating signal occurs, frequency detecting unit exports control signal to control driver element conducting transistor seconds, produces ahead of time to trigger next first pulse width modulating signal.Reduction control unit couples frequency detecting unit and adjusting module, controls the pulse duration that adjusting module reduces the second pulse width modulating signal.
In one embodiment of this invention, above-mentioned adjusting module comprises the first comparator, the first current source, the first electric capacity, D type flip-flop, third transistor and inverter.The negative input end of the first comparator couples above-mentioned output voltage.First current source couples the positive input terminal of the first comparator, and the electric current that the first current source produces is proportional to above-mentioned input voltage; Between the positive input terminal that first electric capacity is coupled in the first comparator and earthed voltage.The data input end of D type flip-flop couples one first operating voltage, the clock input of D type flip-flop couples the first pulse width modulating signal, the replacement end of D type flip-flop couples the output of the first comparator, and the data output of D type flip-flop couples driver element.The drain electrode of third transistor and source electrode couple positive input terminal and the earthed voltage of the first comparator respectively.Between the data output that inverter is coupled in D type flip-flop and the grid of third transistor.
In one embodiment of this invention, above-mentioned reduction control unit comprises adjustable current source, it couples the positive input terminal of the first comparator, when the rise edge delay of the second pulse width modulating signal occurs, adjustable current source charges to the first electric capacity according to the rising edge transition of the second pulse width modulating signal time of delay.
In one embodiment of this invention, above-mentioned reduction control unit comprises arithmetic element and adjustable electric potential source.Arithmetic element is coupled between the negative input end of output voltage and the first comparator.Adjustable electric potential source is coupled between arithmetic element and earthed voltage, when the rise edge delay of the second pulse width modulating signal occurs, adjustable electric potential source exports an adjustment voltage according to the rising edge transition of the second pulse width modulating signal time of delay, and output voltage is deducted adjustment voltage to drag down output voltage by arithmetic element.
In one embodiment of this invention, above-mentioned reduction control unit is digital control circuit.
In one embodiment of this invention, above-mentioned DC-DC converter, also comprises feedback unit and pulse width modulating signal generation module.Feedback unit is coupled between the output of DC-DC converter and earthed voltage.Pulse width modulating signal generation module couples adjusting module and feedback unit, and the dividing potential drop according to a reference voltage and output voltage produces the first pulse width modulating signal.
In one embodiment of this invention, above-mentioned pulse width modulating signal generation module comprises error amplifier, compensating unit, ramp generator and the second comparator.The positive and negative input of error amplifier couples reference voltage and impedance unit respectively, and the dividing potential drop according to reference voltage and output voltage produces an error signal.Compensating unit couples the output of error amplifier, and it is in order to compensating error signal.Ramp generator is in order to produce a ramp signal.The positive and negative input of the second comparator couples output and the ramp generator of error amplifier respectively, and the comparative result according to error signal and ramp signal produces the first pulse width modulating signal.
The present invention proposes a kind of voltage conversion method, and be applicable to a DC-DC converter, voltage conversion method comprises the following steps.Output voltage according to the first pulse width modulating signal and DC-DC converter exports the second pulse width modulating signal; React the second pulse width modulating signal to provide output voltage; And whether the frequency of the frequency or the second pulse width modulating signal that detect the first pulse width modulating signal is lower than a predeterminated frequency, wherein when the frequency of the first pulse width modulating signal or the frequency of the second pulse width modulating signal are lower than predeterminated frequency, reduce output voltage, to make the first pulse width modulating signal produce ahead of time, and reduce the pulse duration of the second pulse width modulating signal.
Based on above-mentioned, the present invention controls according to the frequency of the second pulse width modulating signal the pulse duration that adjusting module reduces the second pulse width modulating signal, with when not affecting conversion efficiency, keep the audiorange that the frequency of pulse width modulating signal can receive higher than people's ear.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the DC-DC converter of one embodiment of the invention;
Fig. 2 is the waveform schematic diagram of multiple signal in the DC-DC converter of the embodiment of the present invention;
Fig. 3 is the schematic diagram of the DC-DC converter of another embodiment of the present invention;
Fig. 4 is the schematic diagram of the DC-DC converter of another embodiment of the present invention;
Fig. 5 is the adjusting module of one embodiment of the invention and the schematic diagram of reduction control unit;
Fig. 6 is the adjusting module of another embodiment of the present invention and the schematic diagram of reduction control unit;
Fig. 7 is the voltage conversion method flow chart of the DC-DC converter of one embodiment of the invention.
[main element symbol description]
100,300,400: DC-DC converter;
102: adjusting module;
104: output module;
106: control module;
108: current detecting unit;
302: reduction control unit;
304: frequency detecting unit;
306: driver element;
308: switch unit;
402: pulse width modulating signal generation module;
404: error amplifier;
406,502: comparator;
408: compensating unit;
410: ramp generator;
412: feedback unit;
504:D type flip-flop;
506: inverter;
602: arithmetic element;
VIN: input voltage;
GND: earthed voltage;
M1, M2, M3: transistor;
PWM1, PWM2: pulse width modulating signal
Vout: output voltage;
UG1, LG1: switching signal;
L1: inductance;
S1: control signal;
IL: electric current;
Vref: reference voltage;
ER1: error signal;
RA, RB, R1: resistance;
CA, CB, C1: electric capacity;
Ramp1: ramp signal;
I1: the first current source;
IS1: adjustable current source;
Vc: the voltage on electric capacity;
VS1: adjustable electric potential source;
S702-S708: each step of voltage conversion method flow chart of the DC-DC converter of one embodiment of the invention.
Embodiment
Fig. 1 is the schematic diagram of the DC-DC converter of one embodiment of the invention.Please refer to Fig. 1, DC-DC converter 100 comprises adjusting module 102, output module 104 and control module 106.Adjusting module 102 couples output module 104 and control module 106, and control module 106 also couples output module 104.Output module 104 couples earthed voltage GND, the input voltage VIN of DC-DC converter 100 and control module 106.
Adjusting module 102 in order to receive the output voltage Vout of the first pulse width modulating signal PWM 1 and DC-DC converter 100, and exports the second pulse width modulating signal PWM2 with constant on-time according to the first pulse width modulating signal PWM1 and output voltage Vout.Fig. 2 is the waveform schematic diagram of multiple signal in the DC-DC converter of the embodiment of the present invention, as shown in Figure 2, when rising edge appears in the first pulse width modulating signal PWM 1 that adjusting module 102 receives, adjusting module 102 just can export the second pulse width modulating signal PWM2 that has predetermined pulse width.So, output module 104 just can react the second pulse width modulating signal PWM2 and switch earthed voltage GND and input voltage VIN, with the switching of corresponding output module 104, input voltage VIN is converted to output voltage Vout.
In addition, control module 106 can be used to the frequency of detection second pulse width modulating signal PWM2.The frequency of the second pulse width modulating signal PWM2 is higher under a normal load, that is the time between every two pulses is comparatively of short duration.When the load of DC-DC converter 100 is underloads, the frequency of the second pulse width modulating signal PWM2 will reduce, and the time between two pulses may longer (such as 100us), and falls into the audiorange that people's ear can hear.
When the frequency of the second pulse width modulating signal PWM2 is lower than a predeterminated frequency, that is the time between two pulses is when exceeding a preset value (such as 40us), control module 106 exports a control signal S1 control output module 104 and reduces output voltage Vout, produce ahead of time to make next first pulse width modulating signal PWM1, and then shorten the interpulse distance of the second pulse width modulating signal PWM2, improve the second pulse width modulating signal PWM2 frequency.In addition, control module 106 is and the FREQUENCY CONTROL adjusting module 102 of foundation the second pulse width modulating signal PWM2 reduces the pulse duration of the second pulse width modulating signal PWM2.So, just the voltage conversion efficiency of DC-DC converter 100 can still be kept when the second pulse width modulating signal PWM2 frequency improves, and then the too low and problem that enters in audiorange that people's ear can receive of the frequency of operation solving existing DC-DC converter.
When above-mentioned second pulse width modulating signal PWM2 produces, control module 106 will detect the frequency of the second pulse width modulating signal PWM2 once again whether lower than predeterminated frequency, if, then continue to perform aforesaid operations, until control module 106 detects that the frequency of the second pulse width modulating signal PWM2 is higher than predeterminated frequency, just stop the frequency of adjustment second pulse width modulating signal PWM2, and maintain the pulse duration of the second pulse width modulating signal PWM2.
Fig. 3 is the schematic diagram of the DC-DC converter of another embodiment of the present invention.Please refer to Fig. 3, furthermore, the control module 106 of Fig. 1 comprises reduction control unit 302 and frequency detecting unit 304.Reduction control unit 302 couples adjusting module 102 and frequency detecting unit 304.In addition, output module 104 comprises driver element 306, switch unit 308, inductance L 1 and current detecting unit 108.Driver element 306 couples adjusting module 102, frequency detecting unit 304 and switch unit 308.The first end of inductance L 1 is coupled to the output of DC-DC converter 100, and the second end couples switch unit 308.Switch unit 308 is also coupled to input voltage VIN and the earthed voltage GND of DC-DC converter 100.Current detecting unit 108 is coupled to driver element 306.
Current detecting unit 108 in order to detect load current, such as: the electric current I L in inductance L 1.Driver element 306 is in order to load current output switching signal UG1 and the LG1 detected by foundation the second pulse width modulating signal PWM2 and current detecting unit 108, switch input voltage VIN and earthed voltage GND to control switch unit 308, and then export output voltage Vout at the first end of inductance L 1.
In the present embodiment, switch unit 308 comprises the first transistor M1 and transistor seconds M2.The first transistor M1 and transistor seconds M2 is serially connected between the input voltage VIN of DC-DC converter 100 and earthed voltage GND, and the common joint of the first transistor M1 and transistor seconds M2 is coupled to the second end of inductance L 1.The grid of the first transistor M1 and transistor seconds M2 then couples driver element 306, with difference receiving key signal UG1 and LG1.
When transistor seconds M2 is conducting state, the first transistor M1 is closed condition, and when the first transistor M1 is conducting state, transistor seconds M2 is closed condition, in addition when the electric current I L in inductance L 1 reduces to zero, driver element 306 closes transistor seconds M2.
In the present embodiment, frequency detecting unit 304 can detect the transition time point of the rising edge of the second pulse width modulating signal PWM2 within each signal period.In other embodiments, frequency detecting unit 304 also can detect the transition time point of the rising edge of the first pulse width modulating signal PWM1 within each signal period.
As shown in Figure 2, when the rise edge delay of the second pulse width modulating signal PWM2 (or first pulse width modulating signal PWM1) occurs, frequency detecting unit 304 just controls adjusting module 102 and makes driver element 306 send switching signal LG1 to transistor seconds M2, with conducting it, produce ahead of time to trigger next first pulse width modulating signal PWM1.
Referring to appears in the rise edge delay of above-mentioned second pulse width modulating signal PWM2, frequency detecting unit 304 is after detecting that first the second pulse width modulating signal PWM2 occurs, frequency detecting unit 304 can judge whether next second pulse width modulating signal PWM2 can occur in preset value (such as 40us), if the second pulse width modulating signal PWM2 occurs after preset value, then represent that the rise edge delay of the second pulse width modulating signal PWM2 occurs.
As shown in Figure 2, in other words, if according to predeterminated frequency (such as 25KHZ), second pulse width modulating signal PWM2 should the dotted line place transition shown on the waveform of the second pulse width modulating signal PWM2 be high voltage logic level, but because the load of the output of DC-DC converter 300 lightens, thus make that the frequency of the second pulse width modulating signal PWM2 reduces, the time point that distance broadens, the second pulse width modulating signal PWM2 transition is high voltage logic level between pulse and pulse is delayed.Now the control signal S1 of high voltage logic level exports to and controls driver element 306 by frequency detecting unit 304, there is provided the switching signal LG1 of high voltage logic level to switch unit 308 to make driver element 306, with conducting transistor seconds M2, and then next first pulse width modulating signal PWM1 is produced ahead of time, wherein control signal S1 is high voltage logic level.
It should be noted that, in embodiments of the present invention, when the rise edge delay of the second pulse width modulating signal PWM2 occurs, although the electric current I L in inductance L 1 reduces to zero, the event that so now rise edge delay occurs has higher priority, therefore driver element 306 forces conducting transistor seconds M2 according to a priority mechanism and control signal S1, until next first pulse width modulating signal PWM1 produces ahead of time, about the mechanism how the first pulse width modulating signal PWM1 produces ahead of time, be detailed later.
As shown in Figure 2, second pulse of the second pulse width modulating signal PWM2 has narrower pulse duration compared to first pulse.When the second pulse width modulating signal PWM2 transition is high voltage logic level, transition is low logic voltage level by switching signal LG1, and switching signal UG1 then transition is high voltage logic level.Until when the second pulse width modulating signal PWM2 transition is low logic voltage level, switching signal LG1 just transition is high voltage logic level, and switching signal UG1 then transition is low logic voltage level.The pulse duration of switching signal UG1 also can be subject to the impact of the pulse duration reduction of the second pulse width modulating signal PWM2 and narrow.In addition, when the electric current I L that current detecting unit 108 detects in inductance L 1 reduces to 0, switching signal LG1 transition is low logic voltage level by driver element 306.
It should be noted that, after the pulse duration of the second pulse width modulating signal PWM2 is reduced, when the second pulse width modulating signal PWM2 transfers high-voltage level to along with the appearance of the rising edge of the first pulse width modulating signal PWM1 next time, if the frequency of the second pulse width modulating signal PWM2 is higher than predeterminated frequency, then the pulse duration of the second pulse width modulating signal PWM2 by maintenance with last to reduce the second pulse width modulating signal PWM2 after pulse duration identical.And if the frequency of the second pulse width modulating signal PWM2 is still less than or equal to predeterminated frequency, then the pulse duration of the second pulse width modulating signal PWM2 will be reduced again according to the mode of above-described embodiment.So repeatedly improve the frequency of the second pulse width modulating signal PWM2 and reduce the pulse duration of the second pulse width modulating signal PWM2, the frequency of the second pulse width modulating signal PWM2 can be adjusted to higher than predeterminated frequency, and the voltage conversion efficiency of DC-DC converter 300 can not be had influence on.
The first above-mentioned pulse width modulating signal PWM1 can utilize pulse width modulating signal generation module to produce.Fig. 4 is the schematic diagram of the DC-DC converter of another embodiment of the present invention.Please refer to Fig. 4, the DC-DC converter 400 of the present embodiment is with the difference of the DC-DC converter 100 of Fig. 1, and DC-DC converter 400 also comprises pulse width modulating signal generation module 402 and feedback unit 412.Feedback unit 412 couples adjusting module 102 and pulse width modulating signal generation module 402.By this, pulse width modulating signal generation module 402 can produce the first pulse width modulating signal PWM1 according to a reference voltage Vref and output voltage Vout.The voltage that wherein adjusting module 102 and pulse width modulating signal generation module 402 receive can become a proportionate relationship with output voltage Vout.Such as in the present embodiment, adjusting module 102 is directly receive output voltage Vout, and pulse width modulating signal generation module 402 then receives the output voltage Vout after via feedback unit 412 dividing potential drop.
Specifically, pulse width modulating signal generation module 402 comprises error amplifier 404, compensating unit 408, ramp generator 410 and the second comparator 406.The positive and negative input of error amplifier 404 couples reference voltage Vref and feedback unit 412 respectively, to produce an error signal ER1 according to reference voltage Vref and output voltage Vout.In the present embodiment, feedback unit 412 comprises two resistance RA, RB of being serially connected between the output of DC-DC converter 400 and earthed voltage GND, and error amplifier 404 is that the dividing potential drop of foundation reference voltage Vref and output voltage Vout produces error signal ER1.
Compensating unit 408 couples the output of error amplifier 404, in the present embodiment compensating unit 408, and resistance R1 connects with electric capacity CA, then in parallel with electric capacity CB again, so not as limit.The positive and negative input of the second comparator 406 is coupled to output and the ramp generator 410 of error amplifier 404 respectively.Compensating unit 408 is in order to compensate error signal ER1, after completing the compensation to error signal Vref, the ramp signal ramp1 that error signal ER1 and ramp generator 410 provide compares by comparator 406, to produce the first pulse width modulating signal PWM1.The waveform of error signal ER1, ramp signal ramp1 and the first pulse width modulating signal PWM1 can be as shown in Figure 2.
After above-mentioned transistor seconds M2 is switched on, output voltage Vout will be dragged down.Under normal operation, that is first frequency of pulse width modulating signal PWM1 (or second pulse width modulating signal PWM2) when being greater than predeterminated frequency, output voltage Vout can because the electric current I L in inductance L 1 is greater than the relation of zero and slowly declines, and just make pulse width modulating signal generation module 402 produce the first pulse width modulating signal PWM1 after a certain time.
But, when the rise edge delay of the second pulse width modulating signal PWM2 occurs, electric current I L in inductance L 1 has now been zero, output voltage Vout makes error amplifier 404 produce an error signal ER1 by declining fast, and then make pulse width modulating signal generation module 402 do sth. in advance generation first pulse width modulating signal PWM1, to provide the second pulse width modulating signal PWM2.
After error amplifier 404 produces error signal ER1, the output of error amplifier 404 is charged to electric capacity CA, CB and the voltage level of error signal ER1 is driven high gradually.When the voltage level of error signal ER1 is driven high to during higher than ramp signal ramp1, second comparator 406 is by the first pulse width modulating signal PWM1 of output HIGH voltage logic level, and then making next first pulse width modulating signal PWM1 start to produce, the second pulse width modulating signal PWM2 also produces thereupon.Now notice reduction control unit 302 is controlled the pulse duration that adjusting module 102 reduces the second pulse width modulating signal PWM2 by frequency detecting unit 304.
Fig. 5 is the adjusting module of one embodiment of the invention and the schematic diagram of reduction control unit.Specifically, above-mentioned adjusting module 102 can be as shown in Figure 5 with the execution mode of reduction control unit 302.Adjusting module 102 can comprise the first comparator 502, first current source I1, first electric capacity C1, D type flip-flop 504, third transistor M3 and inverter 506.In addition, reduce control unit 302 and can comprise adjustable current source IS1.First current source I1 and adjustable current source IS1 couples the positive input terminal of the first comparator 502.Between the negative input end that first electric capacity C 1 is coupled to the first comparator 502 and earthed voltage GND.The drain electrode of third transistor M3 and source electrode couple positive input terminal and the earthed voltage GND of the first comparator 502 respectively.The data input end D of D type flip-flop 504 couples the first operating voltage VOP, the clock input of D type flip-flop 504 couples the first pulse width modulating signal PWM1, the replacement end R of D type flip-flop 504 couples the output of the first comparator 502, and the data output Q of D type flip-flop couples driver element 306.In addition, between the inverter 506 data output Q that is coupled in D type flip-flop 504 and the grid of third transistor M3.
As shown in Figure 5, the pulse duration of the second pulse width modulating signal PWM2 decides by the output of the first pulse width modulating signal PWM1 and the first comparator 502.D type flip-flop 504 exports data input end D to its output Q according to the first pulse width modulating signal PWM1 and produces the second pulse width modulating signal PWM2, and resets by the output of the first comparator 502 pulse duration that D type flip-flop 504 just can change the second pulse width modulating signal PWM2.In the present embodiment, the voltage of the first comparator 502 positive input terminal is the voltage Vc on electric capacity C1, and the change situation of voltage Vc on electric capacity C1 is by being determined by the first current source I1 and adjustable current source IS1.When the rise edge delay of the second pulse width modulating signal PWM2 occurs, adjustable current source IS1 can charge to the first electric capacity C 1 according to the rising edge transition of the second pulse width modulating signal PWM2 time of delay.Got final product the speed of the magnitude of voltage rate of climb of control voltage Vc by the size adjusting the output current of adjustable current source IS1, and then control the pulse duration (that is ON time of the second pulse width modulating signal PWM2) of the second pulse width modulating signal PWM2.
For example, when the pulse duration of wish reduction the second pulse width modulating signal PWM2, by heightening the electric current that adjustable current source IS1 exports, to make voltage Vc reach magnitude of voltage higher than output voltage Vout rapidly, and then D type flip-flop 504 is reset and is low logic voltage level by the second pulse width modulating signal PWM2 transition.When the output current of adjustable current source IS1 is larger, the speed that voltage Vc reaches higher than the magnitude of voltage of output voltage Vout is faster, and the pulse duration of the second pulse width modulating signal PWM2 is also narrower.
It should be noted that above-mentioned reduction control unit 302 can be such as a digital control circuit.The size of current of adjustable current source IS1 can such as with least significant bit (Least Significant Bit, LSB) control, when the frequency of the second pulse width modulating signal PWM2 is adjusted to after higher than predeterminated frequency, just can fix the digital signal controlling adjustable current source IS1, the second pulse width modulating signal PWM2 exported to make adjusting module 102 can continue the pulse duration maintained after the adjustment.
Fig. 6 is the adjusting module of another embodiment of the present invention and the schematic diagram of reduction control unit.Please refer to Fig. 6, the difference of the present embodiment and Fig. 5 embodiment is, Fig. 5 embodiment is the pulse duration utilizing the size of current of adjustable current source IS1 to adjust the second pulse width modulating signal PWM2, and the present embodiment is then the pulse duration utilizing adjustable electric potential source VS1 to adjust the second pulse width modulating signal PWM2.As shown in Figure 6, reduction control unit 302 comprises arithmetic element 602 and adjustable electric potential source VS1, wherein between arithmetic element 602 negative input end that is coupled in the first comparator 502 and output voltage Vout, adjustable electric potential source VS1 is then coupled between arithmetic element 602 and earthed voltage GND.
Similarly, when the rise edge delay of the second pulse width modulating signal PWM2 occurs, adjustable electric potential source VS1 can export corresponding adjustment voltage according to the rising edge transition of the second pulse width modulating signal PWM2 time of delay, output voltage is deducted this adjustment voltage by arithmetic element 602, to control the pulse duration of the second pulse width modulating signal PWM2.
For example, when the pulse duration of wish reduction the second pulse width modulating signal PWM2, by heightening the adjustment voltage that adjustable electric potential source VS1 exports, to make output voltage Vout be reduced to magnitude of voltage lower than voltage Vc rapidly, and then D type flip-flop 504 is reset and is low logic voltage level by the second pulse width modulating signal PWM2 transition.When the adjustment voltage that adjustable electric potential source VS1 exports is larger, the speed that the magnitude of voltage of voltage Vout is reduced to lower than voltage Vc is faster, and the pulse duration of the second pulse width modulating signal PWM2 is also narrower.
Similarly, the adjustment voltage swing that adjustable electric potential source VS1 exports also can such as control with least significant bit, when the frequency of the second pulse width modulating signal PWM2 is adjusted to after higher than predeterminated frequency, just can fix the digital signal controlling adjustable electric potential source VS1, the second pulse width modulating signal PWM2 exported to make adjusting module 102 can continue the pulse duration maintained after the adjustment.
Fig. 7 is the voltage conversion method flow chart of the DC-DC converter of one embodiment of the invention.Please refer to Fig. 7, in sum, the voltage conversion method step of DC-DC converter can be summarized as follows.First, the output voltage according to one first pulse width modulating signal and DC-DC converter exports one second pulse width modulating signal (step S702).Then, the second pulse width modulating signal is reacted to provide output voltage (step S704).Then, whether the frequency of the frequency or the second pulse width modulating signal that detect the first pulse width modulating signal is lower than a predeterminated frequency (step S706).When the frequency of the first pulse width modulating signal or the frequency of the second pulse width modulating signal are lower than predeterminated frequency, reduce output voltage, to make the first pulse width modulating signal produce ahead of time, and reduce the pulse duration (step S708) of the second pulse width modulating signal.Relatively, if the frequency of pulse width modulating signal is higher than predeterminated frequency, then pulse-width modulated signal does not carry out the adjustment of pulse duration, and gets back to step S702, and the output voltage according to the first pulse width modulating signal and DC-DC converter exports the second pulse width modulating signal.
In sum, the embodiment of the present invention can when the underload of DC-DC converter, improve the frequency of pulse width modulating signal, and the frequency of foundation pulse width modulating signal reduces the pulse duration of pulse width modulating signal, the audiorange dropping on people's ear to avoid the frequency of pulse width modulating signal and can receive, keeps its high conversion efficiency simultaneously.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (13)
1. a DC-DC converter, is characterized in that, comprising:
One adjusting module, the output voltage according to one first pulse width modulating signal and above-mentioned DC-DC converter exports one second pulse width modulating signal;
One output module, couples above-mentioned adjusting module, and reacts above-mentioned second pulse width modulating signal to provide above-mentioned output voltage; And
One control module, couples above-mentioned adjusting module and above-mentioned output module, detects the frequency of above-mentioned first pulse width modulating signal or the frequency of above-mentioned second pulse width modulating signal,
Wherein when the frequency of above-mentioned first pulse width modulating signal or the frequency of above-mentioned second pulse width modulating signal are lower than a predeterminated frequency, above-mentioned control module exports a control signal and controls above-mentioned output module and reduce above-mentioned output voltage, above-mentioned first pulse width modulating signal is produced ahead of time, and controls the pulse duration of above-mentioned second pulse width modulating signal of above-mentioned adjusting module reduction.
2. DC-DC converter according to claim 1, is characterized in that above-mentioned output module comprises:
One inductance, its first end exports above-mentioned output voltage;
One switch unit, couples the second end of above-mentioned inductance, an input voltage and an earthed voltage; And
One driver element, couple above-mentioned adjusting module, above-mentioned control module and above-mentioned switch unit, control above-mentioned switch unit according to above-mentioned second pulse width modulating signal and switch above-mentioned input voltage and above-mentioned earthed voltage, and then export above-mentioned output voltage at the first end of above-mentioned inductance.
3. DC-DC converter according to claim 2, is characterized in that above-mentioned switch unit comprises:
One the first transistor; And
One transistor seconds, and above-mentioned the first transistor is serially connected between above-mentioned input voltage and above-mentioned earthed voltage, the grid of above-mentioned the first transistor and above-mentioned transistor seconds couples above-mentioned driver element, the common joint of above-mentioned the first transistor and above-mentioned transistor seconds couples the second end of above-mentioned inductance, the conducting state of above-mentioned the first transistor and above-mentioned transistor seconds is controlled by above-mentioned driver element
Wherein, above-mentioned driver element also forces the above-mentioned transistor seconds of conducting according to a priority mechanism and above-mentioned control signal, until next first pulse width modulating signal produces ahead of time.
4. DC-DC converter according to claim 3, is characterized in that when the frequency of above-mentioned second pulse width modulating signal is lower than above-mentioned predeterminated frequency, the above-mentioned transistor seconds of above-mentioned driver element conducting.
5. DC-DC converter according to claim 3, is characterized in that above-mentioned output module also comprises:
One current detecting unit, couple above-mentioned driver element, detect the electric current on above-mentioned inductance, when the electric current on above-mentioned inductance reduces to zero, above-mentioned driver element closes above-mentioned transistor seconds, and when the frequency of above-mentioned second pulse width modulating signal reduces to zero lower than electric current during above-mentioned predeterminated frequency and on above-mentioned inductance, above-mentioned driver element utilizes above-mentioned priority mechanism to force the above-mentioned transistor seconds of conducting.
6. DC-DC converter according to claim 3, is characterized in that above-mentioned control module comprises:
One frequency detecting unit, detect the transition time point of above-mentioned first pulse width modulating signal or the rising edge of above-mentioned second pulse width modulating signal within each signal period, when the rise edge delay of above-mentioned first pulse width modulating signal or above-mentioned second pulse width modulating signal occurs, said frequencies detecting unit exports above-mentioned control signal to control the above-mentioned transistor seconds of above-mentioned driver element conducting, produces ahead of time to trigger next first pulse width modulating signal; And
One reduction control unit, couples said frequencies detecting unit and above-mentioned adjusting module, controls the pulse duration of above-mentioned second pulse width modulating signal of above-mentioned adjusting module reduction.
7. DC-DC converter according to claim 6, is characterized in that above-mentioned adjusting module comprises:
One first comparator, its negative input end couples above-mentioned output voltage;
One first current source, couples the positive input terminal of above-mentioned first comparator, and the electric current that above-mentioned first current source produces is proportional to above-mentioned input voltage;
One first electric capacity, between the positive input terminal being coupled in above-mentioned first comparator and above-mentioned earthed voltage;
One D type flip-flop, its D input couples one first operating voltage, the clock input of above-mentioned D type flip-flop couples above-mentioned first pulse width modulating signal, the replacement end of above-mentioned D type flip-flop couples the output of above-mentioned first comparator, and the Q output of above-mentioned D type flip-flop couples above-mentioned driver element;
One third transistor, its drain electrode couples the positive input terminal of above-mentioned first comparator and above-mentioned earthed voltage respectively with source electrode; And
One inverter, between the Q output being coupled in above-mentioned D type flip-flop and the grid of above-mentioned third transistor.
8. DC-DC converter according to claim 7, is characterized in that above-mentioned reduction control unit comprises:
One adjustable current source, couple the positive input terminal of above-mentioned first comparator, when the rise edge delay of above-mentioned second pulse width modulating signal occurs, above-mentioned adjustable current source charges to above-mentioned first electric capacity according to the rising edge transition of above-mentioned second pulse width modulating signal time of delay.
9. DC-DC converter according to claim 7, is characterized in that above-mentioned reduction control unit comprises:
One arithmetic element, between the negative input end being coupled in above-mentioned output voltage and above-mentioned first comparator; And
One adjustable electric potential source, be coupled between above-mentioned arithmetic element and above-mentioned earthed voltage, when the rise edge delay of above-mentioned second pulse width modulating signal occurs, above-mentioned adjustable electric potential source exports an adjustment voltage according to the rising edge transition of above-mentioned second pulse width modulating signal time of delay, and above-mentioned output voltage is deducted above-mentioned adjustment voltage to drag down above-mentioned output voltage by above-mentioned arithmetic element.
10. DC-DC converter according to claim 7, is characterized in that above-mentioned reduction control unit is a digital control circuit.
11. DC-DC converters according to claim 6, is characterized in that also comprising:
One feedback unit, is coupled between the output of above-mentioned DC-DC converter and above-mentioned earthed voltage; And
One pulse width modulating signal generation module, couples above-mentioned adjusting module and above-mentioned feedback unit, and the dividing potential drop according to a reference voltage and above-mentioned output voltage produces above-mentioned first pulse width modulating signal.
12. DC-DC converters according to claim 11, is characterized in that above-mentioned pulse width modulating signal generation module comprises:
One error amplifier, its positive and negative input couples above-mentioned reference voltage and an impedance unit respectively, and the dividing potential drop according to above-mentioned reference voltage and above-mentioned output voltage produces an error signal;
One compensating unit, couples the output of above-mentioned error amplifier, compensates above-mentioned error signal;
One ramp generator, produces a ramp signal; And
One second comparator, its positive and negative input couples the output of above-mentioned error amplifier and above-mentioned ramp generator respectively, and the comparative result according to above-mentioned error signal and above-mentioned ramp signal produces above-mentioned first pulse width modulating signal.
13. 1 kinds of voltage conversion methods, are applicable to a DC-DC converter, it is characterized in that, above-mentioned voltage conversion method comprises:
An output voltage according to one first pulse width modulating signal and above-mentioned DC-DC converter exports one second pulse width modulating signal;
React above-mentioned second pulse width modulating signal to provide above-mentioned output voltage; And
The frequency of the frequency or above-mentioned second pulse width modulating signal that detect above-mentioned first pulse width modulating signal whether lower than a predeterminated frequency,
Wherein when the frequency of above-mentioned first pulse width modulating signal or the frequency of above-mentioned second pulse width modulating signal are lower than above-mentioned predeterminated frequency, reduce above-mentioned output voltage, to make above-mentioned first pulse width modulating signal produce ahead of time, and reduce the pulse duration of above-mentioned second pulse width modulating signal.
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| TW100126620A TWI477048B (en) | 2011-07-27 | 2011-07-27 | Dc-dc converter and voltage conversion method thereof |
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