CN105703610A - Digital type IGBT parallel and active current-sharing method - Google Patents
Digital type IGBT parallel and active current-sharing method Download PDFInfo
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- CN105703610A CN105703610A CN201610132911.9A CN201610132911A CN105703610A CN 105703610 A CN105703610 A CN 105703610A CN 201610132911 A CN201610132911 A CN 201610132911A CN 105703610 A CN105703610 A CN 105703610A
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- igbt
- cpld
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- electric current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
Abstract
The invention discloses a digital type IGBT parallel and active current-sharing method. The method specifically comprises the steps of 1, setting the drive resistors of two IGBTs at three different resistance values; 2, respectively extracting the voltage values of the two IGBTs in the switched-on state; 3, inputting the voltage values obtained in the step 2 into two zero-crossing comparators respectively; 4, respectively inputting the voltage values obtained in the step 2 into two magnitude comparators; 5, transferring the result of the step 3 to a CPLD and judging whether the two IGBTs are simultaneously switched on or not by the CPLD; 6, according to the judgment result of the step 5, adjusting the switched-on time of the IGBTs; 7, transferring the result of the step 4 to the CPLD, and judging whether the rising slopes of the switched-on currents of the two IGBTs are identical or not by the CPLD; 8, adjusting the rising slopes of the switched-on currents of the two IGBTs by the CPLD; 9, repeating the steps 2-8 till the rising slopes of the switched-on currents of the two IGBTs are identical. According to the technical scheme of the invention, the parallel current-sharing effects of the IGBTs are effectively improved. Meanwhile, the service lives of the IGBT connected in parallel are prolonged.
Description
Technical field
The invention belongs to IGBT Current Sharing Technology field, be specifically related to a kind of digital IGBT parallel connection actively current equalizing method。
Background technology
Development along with semiconductor technology, the IGBT module capacity that main flow manufacturer can provide is own through being greatly improved, but when system has further dilatation demand, generally have that two ways is selective improves current capacity: 1) directly select the device of greater power capacity；2) device using middle low power grade is in parallel。But consider price, the complexity of drive circuit, adopt multiple IGBT module parallel to improve the practice that current capacity is present stage economy the most。IGBT module used in parallel, it is possible to improve the current capacity of device for power switching, but only when parallel IGBT module all reaches desirable symmetrical equilibrium state in respective characteristic, could farthest improve the utilization rate that device is in parallel。In actual application in parallel, due to the factor such as asymmetric, temperature contrast of the difference of device self, asymmetric, the drive circuit of loop of power circuit, causing parallel IGBT not current-sharing, reduce the efficiency used in parallel of IGBT, more severe patient can cause that IGBT damages。Occur in that a variety of current equalizing method in recent years, volume method, loop of power circuit impedance balance method, resistance penalty method, pulse transformer method etc. such as drop, but said method belongs to passive current-sharing, these methods are on the one hand along with higher cost and bigger device loss, on the other hand artificial in advance current-sharing parameter is set by experience owing to needing, therefore general for parallel module operating current-sharing effect。
Summary of the invention
It is an object of the invention to provide a kind of digital IGBT parallel connection actively current equalizing method, solve the problem of passive current equalizing method current-sharing weak effect in existing IGBT parallel connection application。
The technical solution adopted in the present invention is, a kind of digital IGBT parallel connection is current equalizing method actively, specifically according to following steps:
Step 1, by two IGBT drive element of the grid drive resistance be set to resistance R three kinds different1,R2,R3, and meet R1> R2> R3, and the initial resistance of two IGBT is disposed as R2；
Step 2, the inductive voltage value extracted when two IGBT open in emitter stage stray inductance respectively；
Step 3, two IGBT that step 2 is obtained magnitude of voltage input respectively in two zero-crossing comparators, obtain zero-crossing comparator signal upset moment T1,T2；
Step 4, two IGBT that step 2 is obtained magnitude of voltage be separately input in magnitude comparator, obtain output valve W1,W2；
Step 5, step 3 acquired results is transferred to main control chip CPLD, CPLD by calculation procedure 3 gained signal upset the moment between poor Δ T judgement two parallel IGBTs whether simultaneously open-minded；
Step 6, CPLD, according to step 5 gained result of determination, utilize its own switch period modulation IGBT service time so that two IGBT are simultaneously open-minded；
Step 7, when two IGBT open simultaneously, step 4 acquired results is transferred to main control chip CPLD, CPLD and judges that whether open the electric current rate of rise identical according to step 4 output valve；
Step 8, CPLD are according to step 7 gained result of determination, and integrating step 1 drives resistance to adjust IGBT and opens the electric current rate of rise；
Step 9, repeated execution of steps 2～step 8, until the electric current rate of rise of two IGBT is identical。
The feature of the present invention also resides in:
When two IGBT of step 2 open, the inductive voltage value in emitter stage stray inductance utilizes RC filter circuit to extract。
Step 5 main control chip CPLD judges that whether two parallel IGBTs are simultaneously open-minded, particularly as follows:
Difference DELTA T=T between the CPLD calculation procedure 3 gained signal upset moment1-T2, as Δ T=0, two IGBT are simultaneously open-minded；As Δ T < 0, T1Corresponding IGBT is first open-minded；As Δ T > 0, then T2Corresponding IGBT is first open-minded。
Step 6 main control chip CPLD utilizes its own switch period modulation IGBT service time, particularly as follows:
As Δ T=0, CPLD does not adjust；As Δ T < 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T1The driving signal delay Δ T time output of corresponding IGBT；As Δ T > 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T2The driving signal delay Δ T time output of corresponding IGBT。
Whether step 7CPLD judges to open the electric current rate of rise identical, particularly as follows:
As step 4 output valve W1=1, W2When=0, then W1The corresponding IGBT electric current rate of rise is higher than W2The corresponding IGBT electric current rate of rise；As output valve W1=0, W2When=1, then W1The corresponding IGBT electric current rate of rise is lower than W2The corresponding IGBT electric current rate of rise；As output valve W1=1, W2When=1, then W1The corresponding IGBT electric current rate of rise is equal to W2The corresponding IGBT electric current rate of rise。
Step 8 main control chip CPLD integrating step 1 drives resistance to adjust IGBT and opens the electric current rate of rise, particularly as follows:
Work as W1=1, W2When=1, raster data model resistance is not adjusted by CPLD, keeps original raster data model resistance R2Constant；Work as W1=1, W2When=0, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R1, by W2The raster data model resistance of corresponding IGBT switches to R3；Work as W1=0, W2When=1, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R3, by W2The raster data model resistance of corresponding IGBT switches to R1。
The invention has the beneficial effects as follows: the present invention a kind of digital IGBT parallel connection actively current equalizing method, in opening process, signal delay time and raster data model resistance is driven by adjusting two IGBT, make two parallel IGBTs open the moment and to open the electric current rate of rise equal, thus improving IGBT parallel current-sharing effect, improve parallel IGBT service life。
Accompanying drawing explanation
Fig. 1 is the flow chart of a kind of digital IGBT parallel connection of the present invention actively current equalizing method。
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail。
A kind of digital IGBT parallel connection of the present invention actively current equalizing method, flow process is as it is shown in figure 1, specifically according to following steps:
Step 1, by two IGBT drive element of the grid drive resistance be set to resistance R three kinds different1,R2,R3, and meet R1> R2> R3, and the initial resistance of two IGBT is disposed as R2, wherein drive element of the grid is made up of raster data model resistance and the MOSFET controlling to drive resistance to access and disconnect；
Step 2, utilize the inductive voltage value that RC filter circuit extracts when two IGBT open in emitter stage stray inductance respectively；
Step 3, two IGBT that step 2 is obtained magnitude of voltage input respectively in two zero-crossing comparators, obtain zero-crossing comparator signal upset moment T1,T2；
Step 4, two IGBT that step 2 is obtained magnitude of voltage be separately input in magnitude comparator, obtain output valve W1,W2；
Step 5, step 3 acquired results is transferred to main control chip CPLD, by the poor Δ T between the calculation procedure 3 gained signal upset moment, CPLD judges that whether two parallel IGBTs are simultaneously open-minded, particularly as follows: the difference DELTA T=T between the CPLD calculation procedure 3 gained signal upset moment1-T2, as Δ T=0, two IGBT are simultaneously open-minded；As Δ T < 0, T1Corresponding IGBT is first open-minded；As Δ T > 0, then T2Corresponding IGBT is first open-minded。
Step 6, CPLD, according to step 5 gained result of determination, utilize its own switch period modulation IGBT service time so that two IGBT are simultaneously open-minded, particularly as follows:
As Δ T=0, CPLD does not adjust；As Δ T < 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T1The driving signal delay Δ T time output of corresponding IGBT；As Δ T > 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T2The driving signal delay Δ T time output of corresponding IGBT。
Step 7, when two IGBT open simultaneously, step 4 acquired results is transferred to main control chip CPLD, CPLD and judges that whether open the electric current rate of rise identical according to step 4 output valve, particularly as follows:
As step 4 output valve W1=1, W2When=0, then W1The corresponding IGBT electric current rate of rise is higher than W2The corresponding IGBT electric current rate of rise；As output valve W1=0, W2When=1, then W1The corresponding IGBT electric current rate of rise is lower than W2The corresponding IGBT electric current rate of rise；As output valve W1=1, W2When=1, then W1The corresponding IGBT electric current rate of rise is equal to W2The corresponding IGBT electric current rate of rise。
Step 8, CPLD are according to step 7 gained result of determination, and integrating step 1 drives resistance to adjust IGBT and opens the electric current rate of rise, particularly as follows:
Work as W1=1, W2When=1, raster data model resistance is not adjusted by CPLD, keeps original raster data model resistance R2Constant；Work as W1=1, W2When=0, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R1, by W2The raster data model resistance of corresponding IGBT switches to R3；Work as W1=0, W2When=1, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R3, by W2The raster data model resistance of corresponding IGBT switches to R1。
The invention has the beneficial effects as follows: the present invention a kind of digital IGBT parallel connection actively current equalizing method, in opening process, signal delay time and raster data model resistance is driven by adjusting two IGBT, make two parallel IGBTs open the moment and to open the electric current rate of rise equal, thus improving IGBT parallel current-sharing effect, improve parallel IGBT service life。
Claims (6)
1. a digital IGBT parallel connection actively current equalizing method, it is characterised in that specifically according to following steps:
Step 1, by two IGBT drive element of the grid drive resistance be set to resistance R three kinds different1,R2,R3, and meet R1> R2> R3, and the initial resistance of two IGBT is disposed as R2；
Step 2, the inductive voltage value extracted when two IGBT open in emitter stage stray inductance respectively；
Step 3, two IGBT that step 2 is obtained magnitude of voltage input respectively in two zero-crossing comparators, obtain zero-crossing comparator signal upset moment T1,T2；
Step 4, two IGBT that step 2 is obtained magnitude of voltage be separately input in magnitude comparator, obtain output valve W1,W2；
Step 5, step 3 acquired results is transferred to main control chip CPLD, CPLD by calculation procedure 3 gained signal upset the moment between poor Δ T judgement two parallel IGBTs whether simultaneously open-minded；
Step 6, CPLD, according to step 5 gained result of determination, utilize its own switch period modulation IGBT service time so that two IGBT are simultaneously open-minded；
Step 7, when two IGBT open simultaneously, step 4 acquired results is transferred to main control chip CPLD, CPLD and judges that whether open the electric current rate of rise identical according to step 4 output valve；
Step 8, CPLD are according to step 7 gained result of determination, and integrating step 1 drives resistance to adjust IGBT and opens the electric current rate of rise；
Step 9, repeated execution of steps 2～step 8, until the electric current rate of rise of two IGBT is identical。
2. the digital IGBT parallel connection of one according to claim 1 actively current equalizing method, it is characterised in that when two IGBT of described step 2 open, the inductive voltage value in emitter stage stray inductance utilizes RC filter circuit to extract。
3. the digital IGBT parallel connection of one according to claim 1 actively current equalizing method, it is characterised in that described step 5 main control chip CPLD judges that whether two parallel IGBTs are simultaneously open-minded, particularly as follows:
Difference DELTA T=T between the CPLD calculation procedure 3 gained signal upset moment1-T2, as Δ T=0, two IGBT are simultaneously open-minded；As Δ T < 0, T1Corresponding IGBT is first open-minded；As Δ T > 0, then T2Corresponding IGBT is first open-minded。
4. the digital IGBT parallel connection of one according to claim 1 actively current equalizing method, it is characterised in that described step 6 main control chip CPLD utilizes its own switch period modulation IGBT service time, particularly as follows:
As Δ T=0, CPLD does not adjust；As Δ T < 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T1The driving signal delay Δ T time output of corresponding IGBT；As Δ T > 0, then Δ T is saved in the depositor of CPLD, when next switch periods arrives, by T2The driving signal delay Δ T time output of corresponding IGBT。
5. the digital IGBT parallel connection of one according to claim 1 actively current equalizing method, it is characterised in that whether described step 7 main control chip CPLD judges to open the electric current rate of rise identical, particularly as follows:
As step 4 output valve W1=1, W2When=0, then W1The corresponding IGBT electric current rate of rise is higher than W2The corresponding IGBT electric current rate of rise；As output valve W1=0, W2When=1, then W1The corresponding IGBT electric current rate of rise is lower than W2The corresponding IGBT electric current rate of rise；As output valve W1=1, W2When=1, then W1The corresponding IGBT electric current rate of rise is equal to W2The corresponding IGBT electric current rate of rise。
6. the digital IGBT parallel connection of one according to claim 1 actively current equalizing method, it is characterised in that described step 8 main control chip CPLD integrating step 1 drives resistance to adjust IGBT and opens the electric current rate of rise, particularly as follows:
Work as W1=1, W2When=1, raster data model resistance is not adjusted by CPLD, keeps original raster data model resistance R2Constant；Work as W1=1, W2When=0, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R1, by W2The raster data model resistance of corresponding IGBT switches to R3；Work as W1=0, W2When=1, CPLD is by W1The raster data model resistance of corresponding IGBT switches to R3, by W2The raster data model resistance of corresponding IGBT switches to R1。
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160428A (en) * | 2016-08-02 | 2016-11-23 | 西安交通大学 | A kind of IGBT parallel current-equalizing circuit and control method |
| CN106357253A (en) * | 2016-09-07 | 2017-01-25 | 中车大连电力牵引研发中心有限公司 | PWM (pulse width modulation) pulse signal generating circuit |
| CN107342759A (en) * | 2017-01-17 | 2017-11-10 | 青岛青铜剑电子技术有限公司 | A kind of digital intelligent IGBT driving methods and its system |
| CN108183656A (en) * | 2016-12-08 | 2018-06-19 | 福特全球技术公司 | The self-balancing parallel power device of gate drivers with temperature-compensating |
| CN109921606A (en) * | 2017-12-12 | 2019-06-21 | 北京天诚同创电气有限公司 | Current equalizing method, the apparatus and system of power module |
| CN113489287A (en) * | 2021-06-09 | 2021-10-08 | 西安理工大学 | Active parallel current sharing control method for SiCMOS MOSFET module |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160428A (en) * | 2016-08-02 | 2016-11-23 | 西安交通大学 | A kind of IGBT parallel current-equalizing circuit and control method |
| CN106160428B (en) * | 2016-08-02 | 2018-12-07 | 西安交通大学 | A kind of IGBT parallel current-equalizing circuit and control method |
| CN106357253A (en) * | 2016-09-07 | 2017-01-25 | 中车大连电力牵引研发中心有限公司 | PWM (pulse width modulation) pulse signal generating circuit |
| CN108183656A (en) * | 2016-12-08 | 2018-06-19 | 福特全球技术公司 | The self-balancing parallel power device of gate drivers with temperature-compensating |
| CN108183656B (en) * | 2016-12-08 | 2023-12-22 | 福特全球技术公司 | Power transmission system and method for controlling parallel power switch |
| CN107342759A (en) * | 2017-01-17 | 2017-11-10 | 青岛青铜剑电子技术有限公司 | A kind of digital intelligent IGBT driving methods and its system |
| CN107342759B (en) * | 2017-01-17 | 2020-07-10 | 深圳青铜剑技术有限公司 | Digital intelligent IGBT driving method and system |
| CN109921606A (en) * | 2017-12-12 | 2019-06-21 | 北京天诚同创电气有限公司 | Current equalizing method, the apparatus and system of power module |
| CN109921606B (en) * | 2017-12-12 | 2020-07-28 | 北京天诚同创电气有限公司 | Current equalizing method, device and system of power module |
| CN113489287A (en) * | 2021-06-09 | 2021-10-08 | 西安理工大学 | Active parallel current sharing control method for SiCMOS MOSFET module |
| CN113489287B (en) * | 2021-06-09 | 2023-12-22 | 西安理工大学 | Active parallel current sharing control method for SiC MOSFET modules |
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