CN101420218A - Method and circuit used for parallel IGBT dynamic flow equalization - Google Patents
Method and circuit used for parallel IGBT dynamic flow equalization Download PDFInfo
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- CN101420218A CN101420218A CNA2007101653753A CN200710165375A CN101420218A CN 101420218 A CN101420218 A CN 101420218A CN A2007101653753 A CNA2007101653753 A CN A2007101653753A CN 200710165375 A CN200710165375 A CN 200710165375A CN 101420218 A CN101420218 A CN 101420218A
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Abstract
The present invention provides a method and a circuit for dynamic flow equalization of parallel IGBTs. The method comprises the following steps that a time delay is performed to a PWM original waveform to obtain asynchronous PWM drive waveforms; the obtained asynchronous PWM drive waveforms are used to drive the parallel IGBTs to realize that the output waveforms of each IGBT are synchronous. The present invention provides a method and a circuit for dynamic flow equalization of parallel IGBTs. The circuit comprises multiple time-delay circuits each of which is used for performing time delay to PMW original waveforms to obtain asynchronous PWM drive waveforms to make that output waveforms of all the driven parallel IGBTs are synchronous. According to the present invention, comparing with a grid resistance compensating method of the prior art, the method of using time delay to obtain asynchronous PWM drive waveforms to drive parallel IGBTs to form that the output waveforms of all the parallel IGBTs are synchronous, has the characteristics of simple realization, high reliability and good modulation effect.
Description
Technical field
The present invention relates to a kind of Method and circuits that is used for igbt in parallel (IGBT) dynamic current equalizing.
Background technology
The parallel running of igbt (IGBT) can be born higher load current, but simultaneously because the threshold voltage U on each road of parallel IGBT
GE, Miller capacitance C
GE, the emitter-base bandgap grading inductance L
G, resistance R
G, the grid lead inductance L
G, grid capacitance C
GEDeng difference cause each road device of parallel IGBT to open with the turn-off time inconsistent, thereby cause the dynamically problem of not current-sharing, as shown in Figure 1, solid line is represented the grid emitter voltage waveform of a road in the parallel IGBT, IGBT elder generation's conducting in this road is also turn-offed earlier, dotted line is represented the grid voltage waveform on another road in the parallel IGBT, turn-off conducting and back behind the IGBT of this road, dynamically inequality fails to be convened for lack of a quorum and causes the IGBT of first conducting and back shutoff to bear overcurrent in the moment of switch, current imbalance by each road device of parallel IGBT can cause the heat imbalance like this, can damage device when abominable.Thereby the dynamic current equalizing problem that solves parallel IGBT in side circuit becomes vital link.
At present, solve IGBT dynamic current equalizing problem and adopt the resistance penalty method usually, thereby this method is to change grid by the size that changes resistance to discharge and recharge time realization current-sharing.But when adopting this kind method, must be by repetition test, the resistance difficulty of matching is big, and can not change resistance linearly, it is narrower that resistance changes scope, and change resistance undeservedly and may cause side effects such as device failure, is difficult to reach good current-sharing effect.
Summary of the invention
The present invention is directed to and change the narrow shortcoming of realization difficulty, adjustable range that resistance reaches the scheme of current-sharing in the prior art, a kind of Method and circuits that is used for parallel IGBT dynamic flow equalization is provided, and this Method and circuits has realizes the advantage simple, that regulating effect is good.
The invention provides a kind of method that is used for parallel IGBT dynamic flow equalization, wherein, this method may further comprise the steps: the PWM original waveform is delayed time obtains nonsynchronous PWM drive waveforms; And use resulting nonsynchronous PWM drive waveforms to drive parallel IGBT, so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
A kind of circuit that is used for parallel IGBT dynamic flow equalization provided by the invention, wherein, every road delay circuit is used for the PWM original waveform delayed time and obtains nonsynchronous PWM drive waveforms so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
The Method and circuits that is used for parallel IGBT dynamic flow equalization provided by the invention, because nonsynchronous PWM drive waveforms of taking to utilize time-delay to obtain drives parallel IGBT so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous, thereby reach the method for current-sharing purpose, in addition because this circuit adopts hardware circuit to realize time-delay, can reach the time delay that software approach is difficult for the nanosecond of realization, than the method that adopts the resistance compensation, have and realize the advantage simple, that reliability is high, current-sharing is effective.
Description of drawings
Fig. 1 is the grid emitter voltage waveform schematic diagram of two-way parallel IGBT;
Fig. 2 is the circuit structure diagram that is used for parallel IGBT dynamic flow equalization according to of the present invention;
Fig. 3 is according to the rising edge time delay module of the circuit that is used for parallel IGBT dynamic flow equalization of the present invention or the circuit structure diagram of trailing edge time delay module;
Fig. 4 is used to drive the rising edge time delay module of delay circuit of one road IGBT of on-off delay maximum or the circuit structure diagram of trailing edge time delay module according to preferred implementation of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with accompanying drawing.
The invention provides a kind of method that is used for parallel IGBT dynamic flow equalization, wherein, this method may further comprise the steps: the PWM original waveform is delayed time obtains nonsynchronous PWM drive waveforms; And use resulting nonsynchronous PWM drive waveforms to drive parallel IGBT, so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
Wherein, the PWM original waveform is delayed time may further comprise the steps: the PWM original waveform is input in the multichannel delay circuit; Every road delay circuit is delayed time to the rising edge and the trailing edge of the PWM original waveform imported.Here, as shown in Figure 2, the step that delay circuit is delayed time to the rising edge and the trailing edge of PWM original waveform comprises: delay circuit utilizes rising edge time delay module A1 earlier the rising edge of input PWM original waveform to be delayed time; Waveform after utilizing inverter B1 with rising edge time delay module A1 time-delay is anti-phase to become rising edge with convenient adjustment with the trailing edge with the PWM original waveform; Utilize the rising edge of trailing edge time delay module A2 to the waveform after anti-phase, promptly the trailing edge of PWM original waveform is delayed time; Waveform after utilizing another inverter B2 with trailing edge time delay module A2 time-delay is anti-phase, recovers original signal polarity with signal waveform.Rising edge time delay module A1 and trailing edge time delay module A2 can adopt and identical can realize time-delay to the rising edge and the trailing edge of PWM original waveform respectively to the hardware circuit that the rising edge of input waveform is delayed time.Can use the circuit that is used for parallel IGBT dynamic flow equalization provided by the invention to realize the described method that is used for parallel IGBT dynamic flow equalization, its implementation and operation principle will be described below.
As shown in Figure 2, the circuit that is used for parallel IGBT dynamic flow equalization provided by the invention, wherein this circuit comprises the multichannel delay circuit, and every road delay circuit is used for the PWM original waveform delayed time and obtains nonsynchronous PWM drive waveforms so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
Wherein, every road delay circuit comprises the rising edge time delay module A1 that connects in turn, inverter B1, trailing edge time delay module A2 and another inverter B2, the input input PWM original waveform of rising edge time delay module A1, the output of the output of inverter B2 is used for driving the PWM drive waveforms of one road IGBT of parallel IGBT, and rising edge time delay module A1 in the delay circuit of every road and trailing edge time delay module A2 are respectively applied for the rising edge of PWM original waveform and trailing edge delayed time and obtain nonsynchronous PWM drive waveforms so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
Rising edge time delay module A1 can adopt identical circuit structure with trailing edge time delay module A2, as shown in Figure 3, this rising edge time delay module A1 and trailing edge time delay module A2 can comprise adjustable resistance R, capacitor C and with door, the Standard resistance range of adjustable resistance is preferably 0～10k Ω, capacitance is preferably 0.01 μ F, the end of adjustable resistance R is as the input of rising edge time delay module A1 or trailing edge time delay module A2, the other end of adjustable resistance R is connected with an end of capacitor C, the other end ground connection of capacitor C, and the two ends of adjustable resistance R all are connected respectively to input described and door, with the output of the door output as rising edge time delay module A1 or trailing edge time delay module A2.Should with door by to the signal at adjustable resistance R two ends with, can be to the time delay of the rising edge realization nanosecond of the waveform that is input to rising edge time delay module A1 or trailing edge time delay module A2, and adjustable resistance R can be used to control the size of this time delay.
The method of regulating adjustable resistance R is as follows: the value of regulating the adjustable resistance R among rising edge time delay module A1 and the trailing edge time delay module A2 respectively, thereby making this time delay module carry out suitable time-delay to the rising edge of PWM original waveform and trailing edge all reaches simultaneously the rising edge of output waveform (can use oscilloscope to detect) of each road IGBT of the parallel IGBT that is driven and trailing edge to occur, promptly make each road IGBT of parallel IGBT reach break-make simultaneously, finish the current-sharing purpose.
Preferably, adjust for convenient, wherein be used to drive the reference that the delay circuit of one road IGBT of on-off delay maximum can be when regulating the delay circuit output waveform that is used to drive other roads IGBT, the rising edge time delay module A1 of this road delay circuit as a reference and trailing edge time delay module A2 can only be and door, as shown in Figure 4, to guarantee having identical device time-delay with other delay circuit.
Wherein, one road IGBT of on-off delay maximum can determine by the output waveform of oscilloscope measurement parallel IGBT, the road IGBT that opens at last and turn-off at last is one road IGBT of on-off delay maximum, the output waveform of road delay circuit as a reference is as the PWM drive waveforms of the road IGBT that drives this on-off delay maximum, and the output waveform of other delay circuits is as the PWM drive waveforms that drives other each road IGBT in the parallel IGBT.
The waveform that inverter B1 is used for receiving overturns, and makes trailing edge become rising edge and adjusts with convenient, and promptly the trailing edge time delay module also is the rising edge to the waveform that is input to this trailing edge time delay module, and promptly the trailing edge of PWM original waveform is adjusted.The adjusted waveform that inverter B2 is used for receiving overturns, and makes signal waveform return to original signal polarity.Inverter can be realized anti-phase device for any, as not gate.Inverter B1 in each delay circuit is preferably and selects identical device, the inverter B2 in each delay circuit to be preferably to select identical device, to avoid inconsistent and cause producing new time-delay by device.
According to preferred implementation of the present invention, delay circuit as a reference provided by the invention is connected to one road IGBT of on-off delay maximum, other road delay circuits connect after less relatively other roads IGBT of on-off delay separately, the method of regulating adjustable resistance R is as follows: regulate the rising edge time delay module of other delay circuits except that delay circuit as a reference and the adjustable resistance R on the trailing edge time delay module respectively, make the rising edge and the trailing edge of the output waveform of the road IGBT that the rising edge of output waveform (can use oscilloscope to detect) of the parallel IGBT that is driven and trailing edge driven with as a reference road delay circuit respectively reach appearance simultaneously thereby make other delay circuits of described every road carry out suitable time-delay to the rising edge of PWM original waveform and trailing edge.So just make each road output waveform unanimity of parallel IGBT, i.e. each road IGBT break-make and reach the purpose of dynamic current equalizing simultaneously.
Claims (8)
1, a kind of method that is used for parallel IGBT dynamic flow equalization, wherein, this method may further comprise the steps:
The PWM original waveform delayed time obtain nonsynchronous PWM drive waveforms; And
Use resulting nonsynchronous PWM drive waveforms to drive parallel IGBT, so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
2, method according to claim 1, wherein, the PWM original waveform delayed time be may further comprise the steps:
The PWM original waveform is input in the multichannel delay circuit;
Every road delay circuit is delayed time to the rising edge and the trailing edge of the PWM original waveform imported.
3, method according to claim 2, wherein, the step that delay circuit is delayed time to the rising edge and the trailing edge of PWM original waveform comprises:
Delay circuit utilizes rising edge time delay module (A1) earlier the rising edge of input PWM original waveform to be delayed time;
Waveform after utilizing inverter (B1) with rising edge time delay module (A1) time-delay is anti-phase;
Utilize trailing edge time delay module (A2) that the rising edge of the waveform after anti-phase is delayed time;
Waveform after utilizing another inverter (B2) with trailing edge time delay module (A2) time-delay is anti-phase.
4, a kind of circuit that is used for parallel IGBT dynamic flow equalization, it is characterized in that, this circuit comprises the multichannel delay circuit, and every road delay circuit is used for the PWM original waveform delayed time and obtains nonsynchronous PWM drive waveforms so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
5, the circuit that is used for parallel IGBT dynamic flow equalization according to claim 4, wherein, every road delay circuit comprises the rising edge time delay module (A1) that connects in turn, inverter (B1), trailing edge time delay module (A2) and another inverter (B2), the input input PWM original waveform of rising edge time delay module (A1), the output of the output of inverter (B2) is used for driving the PWM drive waveforms of one road IGBT of parallel IGBT, and rising edge time delay module (A1) in the delay circuit of every road and trailing edge time delay module (A2) are respectively applied for the rising edge of PWM original waveform and trailing edge delayed time and obtain nonsynchronous PWM drive waveforms so that the output waveform of each road IGBT of the parallel IGBT that is driven is synchronous.
6, the circuit that is used for parallel IGBT dynamic flow equalization according to claim 5, wherein rising edge time delay module (A1) and trailing edge time delay module (A2) comprise adjustable resistance, electric capacity and with door, one end of adjustable resistance is as the input of rising edge time delay module (A1) or trailing edge time delay module (A2), the other end of adjustable resistance is connected with an end of electric capacity, the other end ground connection of electric capacity, the two ends of adjustable resistance are connected to input described and door, with the output of the door output as rising edge time delay module (A1) or trailing edge time delay module (A2).
7, the circuit that is used for parallel IGBT dynamic flow equalization according to claim 5, wherein be used to drive the rising edge time delay module (A1) of delay circuit of one road IGBT of on-off delay maximum and trailing edge time delay module (A2) for and door, the rising edge time delay module (A1) and the trailing edge time delay module (A2) that are used for driving the delay circuit of other roads of parallel IGBT IGBT comprise adjustable resistance, electric capacity and with door, one end of adjustable resistance is as the input of rising edge time delay module (A1) or trailing edge time delay module (A2), the other end of adjustable resistance is connected with an end of electric capacity, the other end ground connection of electric capacity, the two ends of adjustable resistance are connected to input described and door, with the output of the door output as rising edge time delay module (A1) or trailing edge time delay module (A2).
8, the circuit that is used for parallel IGBT dynamic flow equalization according to claim 5, wherein the inverter (B1) in the different delayed time circuit adopts identical device, and another inverter (B2) in the different delayed time circuit adopts identical device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101653753A CN101420218A (en) | 2007-10-26 | 2007-10-26 | Method and circuit used for parallel IGBT dynamic flow equalization |
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|---|---|---|---|
| CNA2007101653753A CN101420218A (en) | 2007-10-26 | 2007-10-26 | Method and circuit used for parallel IGBT dynamic flow equalization |
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| CN101783582A (en) * | 2010-02-26 | 2010-07-21 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN102684461A (en) * | 2011-03-15 | 2012-09-19 | 英飞凌科技股份有限公司 | Semiconductor device including circuit to compensate for parasitic inductance |
| CN102904557A (en) * | 2012-09-29 | 2013-01-30 | 陆东海 | Switch tube parallel circuit |
| CN102904419A (en) * | 2012-09-25 | 2013-01-30 | 上海交通大学 | Three-phase PWM (Pulse-Width Modulation) wave FPGA (Field Programmable Gate Array) generating device |
| CN103368536A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Signal delay circuit based on MOS (metal oxide semiconductor) transistors |
| CN103715871A (en) * | 2014-01-02 | 2014-04-09 | 上海理工大学 | High-power MOSFET driving circuit |
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| CN112072899A (en) * | 2020-07-23 | 2020-12-11 | 北京交通大学 | Driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals |
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| CN114362487A (en) * | 2021-11-26 | 2022-04-15 | 西安电子科技大学 | Active current-sharing driving control circuit of parallel power device |
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2007
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| CN101783582B (en) * | 2010-02-26 | 2012-08-15 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN101783582A (en) * | 2010-02-26 | 2010-07-21 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN102684461A (en) * | 2011-03-15 | 2012-09-19 | 英飞凌科技股份有限公司 | Semiconductor device including circuit to compensate for parasitic inductance |
| CN102684461B (en) * | 2011-03-15 | 2015-10-21 | 英飞凌科技股份有限公司 | Comprise the semiconductor device of the circuit for compensating stray inductance |
| CN102904419A (en) * | 2012-09-25 | 2013-01-30 | 上海交通大学 | Three-phase PWM (Pulse-Width Modulation) wave FPGA (Field Programmable Gate Array) generating device |
| CN102904419B (en) * | 2012-09-25 | 2015-04-22 | 上海交通大学 | Three-phase PWM (Pulse-Width Modulation) wave FPGA (Field Programmable Gate Array) generating device |
| CN102904557B (en) * | 2012-09-29 | 2015-09-30 | 陆东海 | Switch tube parallel circuit |
| CN102904557A (en) * | 2012-09-29 | 2013-01-30 | 陆东海 | Switch tube parallel circuit |
| CN103368536A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Signal delay circuit based on MOS (metal oxide semiconductor) transistors |
| CN103368536B (en) * | 2013-07-24 | 2016-01-13 | 苏州加古尔微电子科技有限公司 | Based on the signal delay circuit of metal-oxide-semiconductor |
| CN103715871A (en) * | 2014-01-02 | 2014-04-09 | 上海理工大学 | High-power MOSFET driving circuit |
| CN104967349A (en) * | 2015-06-23 | 2015-10-07 | 四川蜀旺科技有限公司 | Circuit capable of reducing loss of switch transistor and driving schedule method |
| CN105703610B (en) * | 2016-03-09 | 2018-05-29 | 西安理工大学 | A kind of digital IGBT parallel connections active current equalizing method |
| CN105703610A (en) * | 2016-03-09 | 2016-06-22 | 西安理工大学 | Digital type IGBT parallel and active current-sharing method |
| CN107612293B (en) * | 2016-07-12 | 2020-03-06 | 株式会社东芝 | Semiconductor module, vehicle, and elevator |
| CN107612293A (en) * | 2016-07-12 | 2018-01-19 | 株式会社东芝 | Semiconductor module, vehicle and lift |
| CN107768364A (en) * | 2017-09-05 | 2018-03-06 | 全球能源互联网研究院有限公司 | A kind of IGBT integrated devices |
| CN107768364B (en) * | 2017-09-05 | 2019-11-15 | 全球能源互联网研究院有限公司 | A kind of IGBT integrated device |
| CN107994634A (en) * | 2017-12-07 | 2018-05-04 | 江苏博强新能源科技股份有限公司 | Waveform-based delay current-limiting controller and use method thereof |
| CN112072899A (en) * | 2020-07-23 | 2020-12-11 | 北京交通大学 | Driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals |
| CN113114028A (en) * | 2021-04-08 | 2021-07-13 | 中国第一汽车股份有限公司 | Driving circuit and driving method of IGBT parallel module and electric automobile |
| CN114362487A (en) * | 2021-11-26 | 2022-04-15 | 西安电子科技大学 | Active current-sharing driving control circuit of parallel power device |
| CN114362487B (en) * | 2021-11-26 | 2024-03-19 | 西安电子科技大学 | Active current-sharing driving control circuit of parallel power device |
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Application publication date: 20090429 |