CN105007062B - A kind of SPM high reliability edge pulse-generating circuit - Google Patents
A kind of SPM high reliability edge pulse-generating circuit Download PDFInfo
- Publication number
- CN105007062B CN105007062B CN201510446658.XA CN201510446658A CN105007062B CN 105007062 B CN105007062 B CN 105007062B CN 201510446658 A CN201510446658 A CN 201510446658A CN 105007062 B CN105007062 B CN 105007062B
- Authority
- CN
- China
- Prior art keywords
- pulse
- input
- high side
- circuit
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Electronic Switches (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The present invention relates to a kind of SPM high reliability edge pulse-generating circuit, based on brand-new circuit design framework, the high side control signal of any pulse width can be applied to, no matter input signal is normal pulse-width, or burst pulse, even Ultra-short pulse, it may ensure that the normal output for resetting RESET pulse signal, fundamentally solve the problems, such as that high side output signal can not reset as caused by burst pulse input signal, reduce the straight-through security risks of high and low side MOSFET, the stability for applying each module work in SPM has been effectively ensured；Moreover, high reliability edge pulse-generating circuit designed by the present invention, it is simple in construction, solve limitation of traditional edge pulse-generating circuit to input pulse width, and then save the multi-stage noise filter circuit in signal transmission path, the transmission delay of signal is reduced, improves operating switch frequency.
Description
Technical field
The present invention relates to for a kind of SPM high reliability edge pulse-generating circuit, belong to intelligent power mould
The drive circuit design field of block.
Background technology
With the continuous progress of electron electric power technology so that many power semiconductors are along high frequency, high-power,
Intelligent and modular direction continues to develop, and terminal client is also more next for the performance, volume and reliability requirement of device
It is higher.SPM is exactly by device for power switching（IGBT or MOSFET）And gate driving circuit（HVIC）It is integrated in
Together, various defencive functions are also integrated with while.While integrated level is lifted, how to meet higher reliability requirement, be
A major challenge of SPM.
As shown in figure 1, a kind of conventional three-phase intelligent power model includes U, V, W three-phase drive circuit.Each phase is driven
Dynamic circuit is by gate driving circuit（HVIC）And high side MOSFET, downside MOSFET, bootstrap diode（BSD）Composition.Grid
The downside input signal LIN of input and high side input signal HIN are respectively converted into control downside MOSFET grid ends by drive circuit
Downside output signal LO and control high side MOSFET grid ends high side output signal HO.Fig. 2 is gate driving circuit（HVIC）
Cut-away view, wherein high side drive circuit by high-voltage level shifters by after input logic unit high side control
Signal HIND（Usually 5V domains）High side control signal is converted into, and then drives high side power device.Due to high side drive circuit
Power supply derive from bootstrap capacitor, so being had higher requirements to power consumption size.It is common in order to reduce the power consumption of level translator
Way is exactly to be latched using pulse（pulse-latch）Level shifting circuit.It is by edge pulse-generating circuit, high voltage level
Change-over circuit and RS latch three parts composition.Edge pulse-generating circuit detects it and inputs the upper of high side control signal HIND
Edge and trailing edge are risen, and exports set SET pulse signal and resets RESET pulse signal, as shown in figure 3, being controlled according to high side
Signal HIND rising edge and trailing edge, respectively produce corresponding to set SET pulse signal and reset RESET pulse signal, so
Afterwards, SET pulse signal and RESET pulse signal is resetted respectively after high voltage level change-over circuit, be sent to extensive after RS latch
Again into control signal.
Traditional edge pulse-generating circuit after simple delay and logical process are done to input signal by obtaining set
SET pulse signal and reset RESET pulse signal.This edge pulse-generating circuit can be just to the input signal of normal width
Really response, but for the burst pulse as caused by system noise or control algolithm etc., or even ultra-narrow input pulse can not be correct
Response.As shown in figure 4, when high side control signal HIND input pulse width is less than certain value, edge pulse-detecting circuit is only
Export set SET pulse signal.Due to it is no reset RESET pulse signal, so RS latch can not normal reset, so as to lead
It is always height to cause high side output signal HO outputs, if now low side control signal LIND inputs are uprised by low, downside output letter
Number LO output is changed into high simultaneously, and high side MOSFET and downside MOSFET are simultaneously turned on, the through current of moment can to MOSFET and
System causes fatal damage, influences the reliability of system.In order to solve the above problems, existing way is the input in circuit
End increase noise filter circuit or RC wave filters, but simply increase wave filter, it can not tackle the problem at its root.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of SPM high reliability edge pulses generation electricity
Road, based on brand-new circuit design framework, the high side control signal of any pulse width can be applied to, can be stablized and accurate
Produce and export the set SET pulse signal corresponding with high side control signal and reset RESET pulse signal.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme：The present invention devises a kind of intelligent power mould
Block high reliability edge pulse-generating circuit, letter is controlled according to the high side exported in SPM by input logic unit
Number, output respectively corresponds to the set SET pulse signal of each rising edge of high side control signal, and corresponding to high side control signal
The reset RESET pulse signal of each trailing edge；The high reliability edge pulse-generating circuit includes being sequentially connected the edge inspection connect
Slowdown monitoring circuit, delay generation circuit and pulse-generating circuit；Wherein, the input of edge sense circuit receives high side control signal,
For detecting the rising edge and trailing edge of high side control signal, produce and export and each rising edge, decline in high side control signal
Along corresponding high side high level effective impulse, then, postpone the input of generation circuit and the output end of edge sense circuit
It is connected, receives the high side high level effective impulse exported by edge sense circuit, for exports and the effective arteries and veins of high side high level
Rush to the unilateral delay low level pulse of the corresponding high side of each high level；One of input of pulse-generating circuit and delay
The output end of generation circuit is connected, and receives the unilateral delay low level pulse of high side, another input of pulse-generating circuit
High side control signal is received, and pulse-generating circuit is according to right between high side control signal and the unilateral delay low level pulse of high side
The logical combination relation answered, produce respectively and export the set SET pulse signal corresponding to each rising edge of high side control signal, with
And the reset RESET pulse signal corresponding to each trailing edge of high side control signal.
As a preferred technical solution of the present invention：The edge sense circuit includes delay circuit and XOR gate B1,
Wherein, the input with delay circuit, an XOR gate B1 input are connected the input of edge sense circuit respectively；It is different
OR gate B1 another input is connected with the output end of delay circuit, and XOR gate B1 output end is as edge sense circuit
Output end.
As a preferred technical solution of the present invention：The delay circuit includes buffer A2, the buffering being sequentially connected in series
Device A3, wherein, the input of buffer A2 input as delay circuit, it is connected with the input of the edge sense circuit
Connect；Buffer A2 output end is connected with buffer A3 input, and buffer A3 output end is as the defeated of delay circuit
Go out end, be connected with another input of the XOR gate B1.
As a preferred technical solution of the present invention：The delay generation circuit includes reference current source Iref, switch
Metal-oxide-semiconductor MN1, electric capacity C1, comparator Comp1 and buffer A1, in reference current source Iref one end and SPM
Positive source is connected, and the reference current source Iref other end is respectively with switching metal-oxide-semiconductor MN1 drain electrode, comparator Comp1 just
It is connected to one end of input, electric capacity C1；Input of the metal-oxide-semiconductor MN1 grid as delay generation circuit is switched, with edge
The output end of detection circuit is connected, and receives the high side high level effective impulse exported by edge sense circuit, switchs metal-oxide-semiconductor
MN1 source electrode is connected and is grounded with the electric capacity C1 other end；Comparator Comp1 reverse input end connection reference voltage, compares
Device Comp1 output end is connected with buffer A1 input, and buffer A1 output end is as delay generation circuit output
End, the output high side unilateral delay low level pulse corresponding with each high level in high side high level effective impulse.
As a preferred technical solution of the present invention：The pulse-generating circuit include nor gate D1, nor gate D2 and
NOT gate E1；Wherein, pulse-generating circuit receives the defeated of the unilateral delay low level pulse of high side from the delay generation circuit
Enter end, AND OR NOT gate D1 one of input, nor gate D2 one of input are connected respectively；Pulses generation electricity
Road receives the input of the high side control signal, respectively AND OR NOT gate D1 another input, NOT gate E1 input phase
Connection；NOT gate E1 output end AND OR NOT gate D2 another input is connected；Nor gate D1 output end is produced as pulse
One of output end of raw circuit, output reset RESET pulse signal；Nor gate D2 output end is as pulse-generating circuit
Another output end, export set SET pulse signal.
A kind of SPM high reliability edge pulse-generating circuit as described above of the invention, using above technical side
Case compared with prior art, has following technique effect：The present invention designs a kind of SPM high reliability edge pulse
Generation circuit, based on brand-new circuit design framework, the high side control signal of any pulse width can be applied to, no matter inputting
Signal is normal pulse-width, or burst pulse, even Ultra-short pulse, may ensure that and is resetting RESET pulse signal just
Often output, fundamentally solves the problems, such as that high side output signal can not reset as caused by burst pulse input signal, reduce
Security risk straight-through high and low side MOSFET, the stabilization for applying each module work in SPM is effectively ensured
Property；Moreover, the high reliability edge pulse-generating circuit designed by the present invention, it is simple in construction, solve traditional edge arteries and veins
Limitation of the generation circuit to input pulse width is rushed, and then saves the multi-stage noise filter circuit in signal transmission path, is subtracted
The small transmission delay of signal, improves operating switch frequency.
Brief description of the drawings
Fig. 1 is the cut-away view of three-phase intelligent power model；
Fig. 2 is the cut-away view of gate driving circuit；
Fig. 3 be traditional edge pulse-generating circuit normal input signal under timing diagram；
Fig. 4 be traditional edge pulse-generating circuit narrow width input signal under timing diagram；
Fig. 5 is the high-level schematic functional block diagram of present invention design SPM high reliability edge pulse-generating circuit；
Fig. 6 is that edge sense circuit shows in present invention design SPM high reliability edge pulse-generating circuit
It is intended to；
Fig. 7 is to postpone showing for generation circuit in present invention design SPM high reliability edge pulse-generating circuit
It is intended to；
Fig. 8 is pulse-generating circuit in present invention design SPM high reliability edge pulse-generating circuit
Schematic diagram；
Fig. 9 is based on normal input signal under present invention design SPM high reliability edge pulse-generating circuit
Under timing diagram；
Figure 10 is based on narrow width input under present invention design SPM high reliability edge pulse-generating circuit
Timing diagram under signal；
Figure 11 is defeated based on ultra-narrow width under present invention design SPM high reliability edge pulse-generating circuit
Enter the timing diagram under signal.
Embodiment
The embodiment of the present invention is described in further detail with reference to Figure of description.
As shown in figure 5, a kind of SPM high reliability edge pulse-generating circuit designed by the present invention, in reality
Among application process, according to the high side control signal HIND exported in SPM by input logic unit, export respectively
It is each corresponding to the set SET pulse signal of each rising edges of high side control signal HIND, and corresponding to high side control signal HIND
The reset RESET pulse signal of trailing edge；The high reliability edge pulse-generating circuit includes being sequentially connected the Edge check connect
Circuit, delay generation circuit and pulse-generating circuit；Wherein, as shown in fig. 6, edge sense circuit includes delay circuit and XOR
Door B1, delay circuit include buffer A2, the buffer A3 being sequentially connected in series；Wherein, buffer A2 input is as deferred telegram
The input on road, buffer A2 output end are connected with buffer A3 input, and buffer A3 output end is as delay
The output end of circuit；The input of the edge sense circuit input with delay circuit, XOR gate B1 respectively an input
It is connected；XOR gate B1 another input is connected with the output end of delay circuit, and XOR gate B1 output end is as side
Along the output end of detection circuit；The input of edge sense circuit receives high side control signal HIND, based on above-mentioned design structure,
Detect high side control signal HIND rising edge and trailing edge, produce and export with each rising edge on high side control signal HIND,
The corresponding high side high level effective impulse EG of trailing edge, then, as shown in fig. 7, delay generation circuit includes reference current source
Iref, switch metal-oxide-semiconductor MN1, electric capacity C1, comparator Comp1 and buffer A1, reference current source Iref one end and intelligent power
Positive source in module is connected, and the reference current source Iref other end is respectively with switching metal-oxide-semiconductor MN1 drain electrode, comparator
Comp1 positive input, electric capacity C1 one end are connected；Switch input of the metal-oxide-semiconductor MN1 grid as delay generation circuit
End, is connected with the output end of edge sense circuit, receives the high side high level effective impulse EG exported by edge sense circuit,
Switch metal-oxide-semiconductor MN1 source electrode is connected with the electric capacity C1 other end and is grounded VSS；Comparator Comp1 reverse input end linker
Quasi- voltage Vref, comparator Comp1 output end are connected with buffer A1 input, and buffer A1 output end, which is used as, prolongs
Slow generation circuit output end, the output high side unilateral delay low electricity corresponding with each high level on high side high level effective impulse EG
Flat pulse DL；As shown in figure 8, one of input of pulse-generating circuit is connected with postponing the output end of generation circuit,
The unilateral delay low level pulse DL of high side is received, another input of pulse-generating circuit receives high side control signal HIND,
And pulse-generating circuit is according to corresponding logical groups between high side control signal HIND and the unilateral delay low level pulse DL of high side
Conjunction relation, produce respectively and export the set SET pulse signal corresponding to each rising edges of high side control signal HIND, and correspondingly
In the reset RESET pulse signal of each trailing edges of high side control signal HIND；Wherein, pulse-generating circuit include nor gate D1,
Nor gate D2 and NOT gate E1；Pulse-generating circuit reception comes the unilateral delay low level pulse DL's of high side of self-dalay generation circuit
Input, AND OR NOT gate D1 one of input, nor gate D2 one of input are connected respectively；Pulses generation
Circuit receives the input of the high side control signal HIND, respectively AND OR NOT gate D1 another input, NOT gate E1 it is defeated
Enter end to be connected；NOT gate E1 output end AND OR NOT gate D2 another input is connected；Nor gate D1 output end conduct
One of output end of pulse-generating circuit, output reset RESET pulse signal；Nor gate D2 output end is produced as pulse
Another output end of raw circuit, exports set SET pulse signal, wherein, set SET pulse signal and reset RESET pulse
Electric capacity C1, reference current source Iref and the reference voltage V ref that the width of signal is depended in delay generation circuit.
The SPM high reliability edge pulse-generating circuit of above-mentioned technical proposal design, based on brand-new circuit
Design architecture, the high side control signal of any pulse width can be applied to, no matter input signal is normal pulse-width, still
Burst pulse, even Ultra-short pulse, may ensure that reset RESET pulse signal normal output, fundamentally solve by
The problem of high side output signal can not reset caused by burst pulse input signal, reduce the straight-through reliabilities of high and low side MOSFET
Risk, the stability for applying each module work in SPM is effectively ensured；Moreover, designed by the present invention
High reliability edge pulse-generating circuit, it is simple in construction, solve traditional edge pulse-generating circuit to input pulse width
Limitation, and then the multi-stage noise filter circuit in signal transmission path is saved, the transmission delay of signal is reduced, improves work
Make switching frequency.
The SPM high reliability edge pulse-generating circuit structure of above-mentioned technical proposal specific design, in reality
Application work in, edge sense circuit detection high side control signal HIND rising edge and trailing edge, and control and believe in high side
Number HIND rising edges and trailing edge export very narrow high side high level effective impulse EG when arriving, for controlling delay generation circuit
Discharge and recharges of the middle reference current source Iref to electric capacity C1, electric capacity C1 magnitude of voltage and the base received by rear class comparator Comp1
Quasi- voltage Vref makes comparisons, the caused unilateral delay low level pulse DL of high side, and final pulse generation circuit is unilateral according to high side
Postpone the logical combination relation between low level pulse DL and high side control signal HIND, produce and exported corresponding to high side respectively
The set SET pulse signal of each rising edges of control signal HIND, and answering corresponding to high side control signal each trailing edges of HIND
Position RESET pulse signal.As shown in figure 9, if high side control signal HIND width tw is much larger than tp, edge sense circuit pin
To high side control signal HIND rising and falling edges, high side high level effective impulse EG is exported, when the effective arteries and veins of high side high level
EG is rushed as height, postpones the switch metal-oxide-semiconductor MN1 conductings in generation circuit, electric capacity C1 is discharged, node VC voltage is 0V, high side
Unilateral delay low level pulse DL outputs are low.When high side high level effective impulse EG becomes low by height, switch metal-oxide-semiconductor MN1 is closed
Close, reference current source Iref is charged to electric capacity C1, and node VC voltage rise, the charging interval, which depends on high side high level, to be had
Imitate the low level width between pulse two high impulses of EG.When node VC voltage is more than the benchmark that comparator Comp1 is received
During voltage Vref, the unilateral delay low level pulse DL outputs of high side are uprised by low；The unilateral delay low level pulse DL's of high side is low
Level width tp is exactly the set SET pulse signal that we require and the width for resetting RESET pulse signal.Node VC voltage
When next high side high level effective impulse EG high level arrives, just 0V can be set to again, then resume waiting for height
Side high level effective impulse EG low level arrives and the charging to electric capacity C1；Pulse-generating circuit export we requirement put
Position SET pulse signal and reset RESET pulse signal.
As shown in Figure 10, as the set SET that high side control signal HIND width tw is sufficiently small, and even less than we require
During the width tp of pulse signal and reset RESET pulse signal, edge sense circuit is directed to high side control signal HIND rising
And trailing edge, continuous high side high level effective impulse EG is exported, due to high side high level effective impulse EG two high level arteries and veins
Low level width between punching is narrow, and the electric capacity C1 on node VC does not have fully charged, and VC voltages are less than comparator Comp1 institutes
The reference voltage V ref of reception.The set SET pulse signal width of pulse-generating circuit output is with high side control signal HIND's
Pulse width is basically identical, but the reset RESET pulse signal width exported then keeps meeting the width tp that we require.This
Sample avoids only set SET pulse signal, and reset RESET pulse signal it is very narrow even without situation, also just from root
High side is reduced in sheet and risk that downside MOSFET is simultaneously turned on.
As shown in figure 11, under the conditions of worse, if high side control signal HIND width tw is even less than edge
The output high side high level effective impulse EG of circuit width is detected, because high side control signal HIND width is too small, edge inspection
Slowdown monitoring circuit can not correctly identify high side control signal HIND rising edges and trailing edge, and it exports high side high level effective impulse EG
It is basically identical with input high side control signal HIND.MOS is switched in high side high level effective impulse EG control delay generation circuits
Discharge and recharges of the pipe MN1 to electric capacity C1.The SET pulse signal and high side control signal HIND basic one of pulse-generating circuit output
Cause, but the reset RESET pulse signal width exported then keeps meeting the width tp that we require.So avoid to only have
Set SET pulse signal, and reset RESET pulse signal it is very narrow even without situation, also just fundamentally reduce high side
The risk simultaneously turned on downside MOSFET.
Embodiments of the present invention are explained in detail above in conjunction with accompanying drawing, but the present invention is not limited to above-mentioned implementation
Mode, can also be on the premise of present inventive concept not be departed from those of ordinary skill in the art's possessed knowledge
Make a variety of changes.
Claims (3)
1. a kind of SPM high reliability edge pulse-generating circuit, according in SPM by input logic list
The high side control signal of member output, respectively output correspond to the set SET pulse signal of each rising edge of high side control signal, and
Corresponding to the reset RESET pulse signal of each trailing edge of high side control signal；It is characterized in that：The high reliability edge pulse production
Raw circuit includes being sequentially connected the edge sense circuit connect, delay generation circuit and pulse-generating circuit；Wherein, Edge check electricity
The input on road receives high side control signal, for detecting the rising edge and trailing edge of high side control signal, produce and export with
The corresponding high side high level effective impulse of each rising edge, trailing edge, then, postpones the defeated of generation circuit in high side control signal
Enter end with the output end of edge sense circuit to be connected, receive the high side high level effective impulse exported by edge sense circuit,
For exporting the high side unilateral delay low level pulse corresponding with each high level in high side high level effective impulse；Pulses generation
One of input of circuit is connected with postponing the output end of generation circuit, receives the unilateral delay low level pulse of high side,
Another input of pulse-generating circuit receives high side control signal, and pulse-generating circuit is according to high side control signal and height
Corresponding logical combination relation between the unilateral delay low level pulse in side, produce and export each corresponding to high side control signal respectively
The set SET pulse signal of rising edge, and the reset RESET pulse signal corresponding to each trailing edge of high side control signal；
Wherein, the edge sense circuit includes delay circuit and XOR gate B1, wherein, the input difference of edge sense circuit
One input of input, XOR gate B1 with delay circuit is connected；XOR gate B1 another input and deferred telegram
The output end on road is connected, the output end of XOR gate B1 output end as edge sense circuit；
And the pulse-generating circuit includes nor gate D1, nor gate D2 and NOT gate E1；Wherein, pulse-generating circuit receives
The unilateral delay low level pulse of high side from the delay generation circuit, difference AND OR NOT gate D1 one of input,
Nor gate D2 one of input is connected；Pulse-generating circuit receives the high side control signal, respectively AND OR NOT gate
D1 another input, NOT gate E1 input is connected；NOT gate E1 output end AND OR NOT gate D2 another input
It is connected；One of output end of the nor gate D1 output end as pulse-generating circuit, output reset RESET pulse letter
Number；Another output end of nor gate D2 output end as pulse-generating circuit, export set SET pulse signal.
A kind of 2. SPM high reliability edge pulse-generating circuit according to claim 1, it is characterised in that：Institute
Buffer A2, buffer A3 that delay circuit includes being sequentially connected in series are stated, wherein, buffer A2 input is as delay circuit
Input, it is connected with the input of the edge sense circuit；Buffer A2 output end and buffer A3 input phase
Connection, buffer A3 output end are connected as the output end of delay circuit, with another input of the XOR gate B1.
A kind of 3. SPM high reliability edge pulse-generating circuit according to claim 1, it is characterised in that：Institute
Stating delay generation circuit includes reference current source Iref, switch metal-oxide-semiconductor MN1, electric capacity C1, comparator Comp1 and buffer A1, ginseng
Examine current source Iref one end with the positive source in SPM to be connected, reference current source Iref other end difference
It is connected with switch metal-oxide-semiconductor MN1 drain electrode, comparator Comp1 positive input, electric capacity C1 one end；Switch metal-oxide-semiconductor MN1
Grid as delay generation circuit input, be connected with the output end of edge sense circuit, receive by Edge check electricity
The high side high level effective impulse of road output, switch metal-oxide-semiconductor MN1 source electrode are connected and are grounded with the electric capacity C1 other end；Compare
Device Comp1 reverse input end connection reference voltage, comparator Comp1 output end are connected with buffer A1 input,
Buffer A1 output end is relative with each high level in high side high level effective impulse as delay generation circuit output end, output
The unilateral delay low level pulse of high side answered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510446658.XA CN105007062B (en) | 2015-07-28 | 2015-07-28 | A kind of SPM high reliability edge pulse-generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510446658.XA CN105007062B (en) | 2015-07-28 | 2015-07-28 | A kind of SPM high reliability edge pulse-generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105007062A CN105007062A (en) | 2015-10-28 |
| CN105007062B true CN105007062B (en) | 2018-02-23 |
Family
ID=54379606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510446658.XA Active CN105007062B (en) | 2015-07-28 | 2015-07-28 | A kind of SPM high reliability edge pulse-generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105007062B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811923B (en) * | 2016-02-29 | 2018-05-04 | 中国电子科技集团公司第五十八研究所 | A kind of clock duty cycle adjustment circuit |
| CN107835000B (en) * | 2017-12-08 | 2024-02-06 | 成都前锋电子仪器有限责任公司 | Output circuit for pulse code pattern generator |
| CN110557014A (en) * | 2019-10-16 | 2019-12-10 | 上海沪工焊接集团股份有限公司 | Wide voltage power factor correction circuit |
| CN112924762A (en) * | 2021-01-27 | 2021-06-08 | 杭州瑞盟科技有限公司 | Pulse width detection circuit |
| CN113556027B (en) * | 2021-06-25 | 2023-05-02 | 上海晶丰明源半导体股份有限公司 | Half-bridge driving circuit and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672990A (en) * | 1996-01-26 | 1997-09-30 | United Microelectronics Corporation | Edge-trigger pulse generator |
| CN1808907A (en) * | 2004-12-22 | 2006-07-26 | 三星电子株式会社 | Phase-locked loops and its method, phase frequency detector and its method |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| CN102037642A (en) * | 2008-05-21 | 2011-04-27 | 硅实验室公司 | Predictive feedback compensation for PWM switching amplifiers |
| CN204794929U (en) * | 2015-07-28 | 2015-11-18 | 周海波 | Intelligence power module high reliability border pulse -generating circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275446B1 (en) * | 2000-08-25 | 2001-08-14 | Micron Technology, Inc. | Clock generation circuits and methods |
| KR100392337B1 (en) * | 2001-01-03 | 2003-07-22 | 주식회사 효성 | A circuits for generating minimum on/of pulse width |
-
2015
- 2015-07-28 CN CN201510446658.XA patent/CN105007062B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672990A (en) * | 1996-01-26 | 1997-09-30 | United Microelectronics Corporation | Edge-trigger pulse generator |
| CN1808907A (en) * | 2004-12-22 | 2006-07-26 | 三星电子株式会社 | Phase-locked loops and its method, phase frequency detector and its method |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| CN102037642A (en) * | 2008-05-21 | 2011-04-27 | 硅实验室公司 | Predictive feedback compensation for PWM switching amplifiers |
| CN204794929U (en) * | 2015-07-28 | 2015-11-18 | 周海波 | Intelligence power module high reliability border pulse -generating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105007062A (en) | 2015-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105007062B (en) | A kind of SPM high reliability edge pulse-generating circuit | |
| CN105356727B (en) | Switching tube drive control method and control circuit for Switching Power Supply | |
| CN101552563B (en) | Device and method for controlling constant-current output in switch power supply | |
| CN1248415C (en) | Half-bridge driver and power conversion system with such driver | |
| US20010036085A1 (en) | Soft switching DC-to-DC converter and controlling method thereof | |
| CN106849621B (en) | A kind of system and method for realizing gate driving circuit | |
| CN105048790A (en) | Power tube control system and drive circuit for driving external power tube | |
| CN105048791A (en) | Power tube control system and external power tube driving circuit for switching power supply | |
| CN107592013A (en) | Control circuit and method applied to bootstrap capacitor power loss recovery in DC DC converters | |
| CN101677240B (en) | Isolated gate bipolar transistor driving circuit | |
| CN102769453A (en) | High-voltage side gate drive circuit capable of resisting noise interference | |
| CN102647177A (en) | High-voltage side gate driving circuit capable of resisting common-mode noise interference | |
| CN104638882A (en) | Signal level shift circuit and direct-to-alternating current buck conversion control circuit | |
| CN106535412B (en) | The digital simulation light adjusting circuit that a kind of port shares | |
| CN102769454A (en) | Noise interference-proof high-side gate drive circuit | |
| CN1097344C (en) | CMOS driver circuit | |
| CN107612528A (en) | A kind of pulse bandwidth filtering circuit arrangement | |
| CN108063435B (en) | Intelligent power module, air conditioner controller and air conditioner | |
| CN101771384B (en) | Non-dead time power amplifier output-stage circuit | |
| CN204794929U (en) | Intelligence power module high reliability border pulse -generating circuit | |
| CN108390549A (en) | A kind of gate drive circuit reducing dead time | |
| JP2007185050A (en) | Dc-dc converter and its control method | |
| CN108233690B (en) | Intelligent power module, air conditioner controller and air conditioner | |
| CN108736863A (en) | A kind of output driving circuit | |
| CN104104370B (en) | A kind of pwm signal power on and off protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160706 Address after: 100020, No. 3, 1 gate, No. 102, 1 North Hospital, eight Li Li village, Beijing, Chaoyang District Applicant after: Jin Xuecheng Address before: 702, room 210011, block A, No. 611, Gulou, Nanjing, Zhongshan North Road, Jiangsu Applicant before: Zhou Haibo |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210203 Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing Weihao integrated circuit design Co.,Ltd. Address before: 100020 Beijing Chaoyang District eight Li Zhuang Bei Li 1 hospital 3 Building 1 door 102. Patentee before: Jin Xuecheng |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Howell analog integrated circuit (Beijing) Co.,Ltd. Address before: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee before: Beijing Weihao integrated circuit design Co.,Ltd. |