CN113472328A - Power switch for burning OTP (one time programmable) of high-speed analog-to-digital converter - Google Patents
Power switch for burning OTP (one time programmable) of high-speed analog-to-digital converter Download PDFInfo
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- CN113472328A CN113472328A CN202111036350.XA CN202111036350A CN113472328A CN 113472328 A CN113472328 A CN 113472328A CN 202111036350 A CN202111036350 A CN 202111036350A CN 113472328 A CN113472328 A CN 113472328A
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- power switch
- nmos tube
- buffer
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention discloses a power switch for burning OTP (one time programmable) of a high-speed analog-to-digital converter, which belongs to the field of power switches and comprises NMOS (N-channel metal oxide semiconductor) transistors M1 and M2, a PMOS (P-channel metal oxide semiconductor) transistor M3, resistors R1-R5, a buffer I1 and an inverter I2; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, and the drain electrode of the NMOS tube M1 is connected with the grid electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with the output end of the inverter I2, and the source electrode of the NMOS tube M2 is connected with the common ground DVSS; the grid electrode of the PMOS tube M3 is connected with the first end of the resistor R5, the source electrode is connected with the first end of the resistor R3, and the drain electrode is connected with the working voltage DVDD through the resistor R4; the second terminal of the resistor R3 and the second terminal of the resistor R5 are both connected to the programming voltage VPP. The resistor R1 is connected with the resistor R2 in series, the input end of the buffer I1 is connected between the resistor R1 and the resistor R2, and the output end of the buffer I1 is connected with the input end of the inverter I2; the first end of the resistor R1 is connected to the programming voltage VPP, the second end is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the common ground DVSS.
Description
Technical Field
The invention relates to the technical field of power switches, in particular to a power switch for burning OTP (one time programmable) of a high-speed analog-to-digital converter.
Background
In a high-speed analog-to-digital converter, a register is often required to be configured to perform performance debugging and modify a working mode, and after the register is debugged, a fixed value needs to be burned into an OTP (One Time programmable) to fix the value of the register.
Higher voltages are required when programming an OTP, generally exceeding the supply voltage during normal operation. And when the chip works normally, the stored value needs to be read from the OTP by using a normal power supply voltage. This results in different supply voltages being required for the OTP module during burn and normal operation. Therefore, the voltage selection must be performed according to the operation mode of the chip, and the selection needs a power switch capable of withstanding high voltage.
Disclosure of Invention
The present invention is directed to a power switch for burning OTP in a high speed adc, so as to solve the problems in the background art.
In order to solve the technical problem, the invention provides a power switch for burning OTP in a high-speed analog-to-digital converter, which comprises NMOS transistors M1 and M2, a PMOS transistor M3, resistors R1-R5, a buffer I1 and an inverter I2;
the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, and the drain electrode of the NMOS tube M1 is connected with the grid electrode of the PMOS tube M3;
the grid electrode of the NMOS tube M2 is connected with the output end of the inverter I2, and the source electrode of the NMOS tube M2 is connected with the common ground DVSS;
the grid electrode of the PMOS tube M3 is connected with the first end of the resistor R5, the source electrode is connected with the first end of the resistor R3, and the drain electrode is connected with the working voltage DVDD through the resistor R4;
the resistor R1 is connected with the resistor R2 in series, the input end of the buffer I1 is connected between the resistor R1 and the resistor R2, and the output end of the buffer I1 is connected with the input end of the inverter I2.
Optionally, a first end of the resistor R1 is connected to the programming voltage VPP, a second end of the resistor R2 is connected to the first end of the resistor R2, and a second end of the resistor R2 is connected to the common ground DVSS.
Optionally, the second end of the resistor R3 and the second end of the resistor R5 are both connected to the programming voltage VPP.
Optionally, the programming voltage VPP is applied from an off-chip PAD.
Optionally, the buffer I1 is a buffer with schmitt trigger.
Optionally, the gate of the NMOS transistor M1 is connected to the operating voltage DVDD.
The power switch for burning OTP in a high-speed analog-to-digital converter comprises NMOS transistors M1 and M2, a PMOS transistor M3, resistors R1-R5, a buffer I1 and an inverter I2; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, and the drain electrode of the NMOS tube M1 is connected with the grid electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with the output end of the inverter I2, and the source electrode of the NMOS tube M2 is connected with the common ground DVSS; the grid electrode of the PMOS tube M3 is connected with the first end of the resistor R5, the source electrode is connected with the first end of the resistor R3, and the drain electrode is connected with the working voltage DVDD through the resistor R4; the second terminal of the resistor R3 and the second terminal of the resistor R5 are both connected to the programming voltage VPP. The resistor R1 is connected with the resistor R2 in series, the input end of the buffer I1 is connected between the resistor R1 and the resistor R2, and the output end of the buffer I1 is connected with the input end of the inverter I2; the first end of the resistor R1 is connected to the programming voltage VPP, the second end is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the common ground DVSS. This power switch circuit can be according to whether appling of off-chip voltage is automatic judgement current operating condition to decide to burn the OTP module or read, when debugging the chip, the chip has a PAD pin to be connected to inside VPP, and this pin is unsettled, can pass through internal circuit configuration register this moment, thereby debug the chip performance, only need exert high voltage at this pin after the debugging is accomplished and can accomplish the burn record to the OTP module, and the circuit is simple, convenient to use.
Drawings
Fig. 1 is a schematic diagram of a power switch for burning OTP in a high-speed analog-to-digital converter according to the present invention.
Detailed Description
The power switch for burning OTP of high speed adc according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a power switch for burning OTP (one time programmable) of a high-speed analog-to-digital converter, which has a structure shown in figure 1 and comprises NMOS (N-channel metal oxide semiconductor) transistors M1 and M2, a PMOS (P-channel metal oxide semiconductor) transistor M3, resistors R1-R5, a buffer I1 and an inverter I2; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, and the drain electrode of the NMOS tube M1 is connected with the grid electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with the output end of the inverter I2, and the source electrode of the NMOS tube M2 is connected with the common ground DVSS; the grid electrode of the PMOS tube M3 is connected with the first end of the resistor R5, the source electrode is connected with the first end of the resistor R3, and the drain electrode is connected with the working voltage DVDD through the resistor R4; the second end of the resistor R3 and the second end of the resistor R5 are both connected to the programming voltage VPP. The resistor R1 is connected with the resistor R2 in series, the input end of the buffer I1 is connected between the resistor R1 and the resistor R2, and the output end of the buffer I1 is connected with the input end of the inverter I2; the first end of the resistor R1 is connected with the programming voltage VPP, the second end is connected with the first end of the resistor R2, and the second end of the resistor R2 is connected with the common ground DVSS.
As shown in fig. 1, the voltage DVDD is a voltage required by the circuit to operate normally, the voltage VPP is a voltage required by the OTP programming, the programming voltage VPP is connected to the off-chip PAD, and the DVSS is a common ground. The circuit has two working modes, which are described in detail as follows:
1. burning OTP: when the OTP module needs to be provided with higher voltage during burning, the voltage VPP is provided from the outside and is input into the chip through the off-chip PAD, at the moment, the resistor R1 and the resistor R2 divide the voltage to ensure that the generated voltage cannot cause the grid of a tube in the rear buffer I1 not to be broken down, and the buffer I1 is a buffer Smt _ buf with Schmidt trigger. The divided voltage is identified as logic high level by a later stage circuit, at the moment, the grid electrode of the NMOS tube M2 is logic low level, the NMOS tube M2 is turned off, the grid electrode voltage of the PMOS tube M3 is VPP, the PMOS tube M3 is turned off at the moment, the externally applied voltage VPP is directly connected to the OTP module, and the OTP module is burned by high voltage. In the circuit, the NMOS transistor M1 is a protection tube to prevent the breakdown of the NMOS transistor M2 directly bearing the voltage VPP, and the resistor R3 and the resistor R4 are ESD protection resistors.
2. And (4) normal operation: during normal operation, a normal power supply voltage needs to be provided for the OTP module, no voltage is applied to an off-chip PAD, and the voltage VPP is generated by the on-chip DVDD. The initial time voltage VPP is 0, at this time, the gate of the NMOS transistor M2 is at a high level, the NMOS transistor M2 is turned on, the gate of the PMOS transistor M3 is at a logic low level, the PMOS transistor M3 is turned on, and at this time, VPP is connected to DVDD, so that the voltage applied to the OTP module is equal to DVDD, thereby ensuring the normal read function of OTP. Note that the voltage division by resistor R1 and resistor R2 is to ensure that the voltage division is a logic low when VPP is equal to DVDD.
The invention provides a power switch for burning OTP of a high-speed analog-to-digital converter, which can provide high voltage during the OTP burning, provide low voltage during the normal work of a chip to ensure normal reading and writing, and provide voltage VPP during the burning by an off-chip PAD; at the moment, the circuit can automatically cut off the connection between the recording voltage VPP and the DVDD, directly transmits the recording voltage VPP to the OTP module, then works normally, the PAD outside the chip is suspended, the DVDD is automatically connected to the recording voltage VPP inside the chip, and then the recording voltage VPP is transmitted to the OTP module, and the reading of the OTP module is realized. The circuit can automatically judge whether VPP needs to be connected to DVDD according to whether the programming voltage VPP is applied or not, so that the normal working state of the OTP module is ensured.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A power switch for burning OTP in a high-speed analog-to-digital converter is characterized by comprising NMOS transistors M1 and M2, a PMOS transistor M3, resistors R1-R5, a buffer I1 and an inverter I2;
the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, and the drain electrode of the NMOS tube M1 is connected with the grid electrode of the PMOS tube M3;
the grid electrode of the NMOS tube M2 is connected with the output end of the inverter I2, and the source electrode of the NMOS tube M2 is connected with the common ground DVSS;
the grid electrode of the PMOS tube M3 is connected with the first end of the resistor R5, the source electrode is connected with the first end of the resistor R3, and the drain electrode is connected with the working voltage DVDD through the resistor R4;
the resistor R1 is connected with the resistor R2 in series, the input end of the buffer I1 is connected between the resistor R1 and the resistor R2, and the output end of the buffer I1 is connected with the input end of the inverter I2.
2. The power switch of claim 1, wherein a first terminal of the resistor R1 is connected to the programming voltage VPP, a second terminal is connected to a first terminal of the resistor R2, and a second terminal of the resistor R2 is connected to the common ground DVSS.
3. The power switch of claim 1, wherein a second terminal of the resistor R3 and a second terminal of the resistor R5 are both connected to a programming voltage VPP.
4. The power switch for burning OTP of a high speed analog-to-digital converter as claimed in claim 2 or 3, wherein the burning voltage VPP is applied by an off-chip PAD.
5. The power switch for burning OTP for high speed analog to digital converter of claim 1 wherein the buffer I1 is a buffer with schmitt trigger.
6. The power switch of claim 1, wherein the gate of the NMOS transistor M1 is connected to a working voltage DVDD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111036350.XA CN113472328B (en) | 2021-09-06 | 2021-09-06 | Power switch for burning OTP (one time programmable) of high-speed analog-to-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111036350.XA CN113472328B (en) | 2021-09-06 | 2021-09-06 | Power switch for burning OTP (one time programmable) of high-speed analog-to-digital converter |
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| Publication Number | Publication Date |
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| CN113472328A true CN113472328A (en) | 2021-10-01 |
| CN113472328B CN113472328B (en) | 2021-11-16 |
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Citations (7)
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|---|---|---|---|---|
| JP2007228228A (en) * | 2006-02-23 | 2007-09-06 | Matsushita Electric Ind Co Ltd | High-speed switching circuit |
| CN102176805A (en) * | 2011-03-11 | 2011-09-07 | 苏州卓能微电子技术有限公司 | Accurate light emitting diode (LED) driving high-temperature protection circuit |
| CN102916667A (en) * | 2011-08-02 | 2013-02-06 | 中国科学院微电子研究所 | Broadband programmable gain amplifier with step length of 2dB |
| CN110459257A (en) * | 2019-08-19 | 2019-11-15 | 珠海创飞芯科技有限公司 | OTP in-line memory and its programmed method, read method |
| US10554112B1 (en) * | 2019-04-04 | 2020-02-04 | Navitas Semiconductor, Inc. | GaN driver circuit |
| CN110829801A (en) * | 2018-08-08 | 2020-02-21 | 半导体组件工业公司 | Circuit and method for controlling power converter |
| CN112511142A (en) * | 2020-12-10 | 2021-03-16 | 中国电子科技集团公司第十四研究所 | Fully-integrated NMOS (N-channel metal oxide semiconductor) tube driving circuit |
-
2021
- 2021-09-06 CN CN202111036350.XA patent/CN113472328B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007228228A (en) * | 2006-02-23 | 2007-09-06 | Matsushita Electric Ind Co Ltd | High-speed switching circuit |
| CN102176805A (en) * | 2011-03-11 | 2011-09-07 | 苏州卓能微电子技术有限公司 | Accurate light emitting diode (LED) driving high-temperature protection circuit |
| CN102916667A (en) * | 2011-08-02 | 2013-02-06 | 中国科学院微电子研究所 | Broadband programmable gain amplifier with step length of 2dB |
| CN110829801A (en) * | 2018-08-08 | 2020-02-21 | 半导体组件工业公司 | Circuit and method for controlling power converter |
| US10554112B1 (en) * | 2019-04-04 | 2020-02-04 | Navitas Semiconductor, Inc. | GaN driver circuit |
| CN110459257A (en) * | 2019-08-19 | 2019-11-15 | 珠海创飞芯科技有限公司 | OTP in-line memory and its programmed method, read method |
| CN112511142A (en) * | 2020-12-10 | 2021-03-16 | 中国电子科技集团公司第十四研究所 | Fully-integrated NMOS (N-channel metal oxide semiconductor) tube driving circuit |
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| CN113472328B (en) | 2021-11-16 |
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Address after: Building C, No.888, Huanhu West 2nd Road, Lingang New District, Pudong New Area pilot Free Trade Zone, Shanghai Patentee after: Shanghai Xinchi Technology Group Co.,Ltd. Address before: 510000 room 552, room 406, No. 1, Yichuang street, Huangpu District, Guangzhou City, Guangdong Province (Zhongxin Guangzhou Knowledge City) Patentee before: Guangdong Xinchi integrated circuit technology Co.,Ltd. |