JP2007228228A - High-speed switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up a switching speed by eliminating a restriction on a transistor size. <P>SOLUTION: A drain terminal of an NMOS transistor 5 is connected with a power supply terminal 1 via a resistor 3, and also connected with a drain terminal of a PMOS transistor 7 and each gate terminal of a PMOS transistor 9 and an NMOS transistor 10 that become an inverter circuit. Logic buffer circuits 11, 12 respectively have a transmission delay time and are used as a delay circuit, and are connected to each drain terminal of the PMOS transistor 9 and the NMOS transistor 10. Each output of the logic buffer circuits is connected to a gate terminal of the PMOS transistor 7 via an inverter 8. Potential changes of a voltage Vd are controlled by delaying with the delay circuit corresponding to input to a gate terminal of the NMOS transistor 5, and by switching a parallel connection between the resistor 3 and a resistor 6 in load resistance of the NMOS transistor 5 by turning on/off the PMOS transistor 7. It is possible to achieve a high-speed switching circuit by properly setting the transmission delay time of the delay circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high-speed switching circuit that transmits an input logic signal and speeds up the change rate of its high and low levels.

  There is a conventional high-speed switching circuit as described in, for example, Patent Document 1, and a circuit configuration diagram of a switching circuit called DCFL (Direct Coupled FET Logic) disclosed in FIG. 1 of Patent Document 1 is shown. 3 shows.

  In FIG. 3, the drain terminal of the NMOS transistor 5 is connected to the power supply terminal 1 through the resistor 3, and is connected to the source terminal of the NMOS transistor 15 and the gate terminal of the NMOS transistor 10. Furthermore, the drain terminal (output terminal 14) of the NMOS transistor 10 is connected to the power supply terminal 1 via the resistor 16, and the drain terminal of the NMOS transistor 10 is connected to the gate terminal of the NMOS transistor 15. The drain terminal of the NMOS transistor 15 is connected to the power supply terminal 1 via the resistor 6. Here, the gate terminal of the NMOS transistor 5 is the input terminal 4.

  In the conventional example configured as described above, when the gate terminal of the NMOS transistor 5 rises from the low level to the high level, the voltage Vd at the drain terminal of the NMOS transistor 5 decreases due to the NMOS transistor 5 being turned on. . Accordingly, since the NMOS transistor 10 is turned off, the drain terminal of the NMOS transistor 10 rises from the low level to the high level. Then, the NMOS transistor 15 is turned on, the drain current increases through the resistor 6, and the load on the NMOS transistor 5 is equivalently reduced. Therefore, the low level of the voltage Vd at the drain terminal of the NMOS transistor 5 becomes a higher voltage. .

  When the gate terminal of the NMOS transistor 5 changes from the high level to the low level, the NMOS transistor 5 changes from the on state to the off state, and the voltage Vd at the drain terminal of the NMOS transistor increases. Then, the NMOS transistor 10 is turned on, and the drain terminal (output terminal 14) of the NMSO transistor 10 is changed to a low level, so that the NMOS transistor 15 is turned off and the resistor 6 becomes irrelevant to the voltage Vd of the drain terminal of the NMOS transistor 5. . Accordingly, when the voltage Vd at the drain terminal of the NMOS transistor 5 rises, the resistor 6 is disconnected in the rising process, but a current supply from the resistor 3 exists, so that a certain voltage gain is ensured.

As described above, the potential of the voltage Vd at the drain terminal of the NMOS transistor 5 is increased on the low level side, and a certain voltage gain can be ensured. As a result, the logic amplitude is reduced and high-speed switching operation is possible.
Japanese Patent No. 2545807

  However, in the conventional switching circuit configuration, the transistor size is required to be limited in order to increase the switching speed. For example, the gate width Wg2 of the NMOS transistor 15 needs to be set to about 1/2 to 1/3 times the gate width Wg1 of the NMOS transistor 5, and substantially the same configuration is necessary except for the gate width. Further, the value of the resistor 6 shown in FIG. 3 needs to be set to, for example, 1 to 3 times the value of the resistor 3, and there are many restrictions such that a certain degree of restriction is imposed on the threshold voltage of the NMOS transistor 15.

  Further, in order to reduce the logical amplitude of the voltage Vd at the drain terminal of the NMOS transistor 5, the connection / disconnection of the resistor 6 is switched by the NMOS transistor 15 so that the load resistance of the NMOS transistor 5 is only the resistor 3 or the resistor 3 The resistor 6 is set to be connected in parallel. However, when the current capability of the NMOS transistor 5 is not increased, the resistor 3 and the resistor 6 are connected in parallel when the NMOS transistor 5 is turned on, so that the voltage Vd at the drain terminal of the NMOS transistor 5 decreases from the high level to the low level. Time may increase. Therefore, even when the low level of the voltage Vd at the drain terminal of the NMOS transistor 5 is slightly increased to reduce the logic amplitude, there are cases where the effect is canceled when the transistor is not optimized, and the switching speed is not increased. A problem occurs.

  The present invention is directed to solving the problems of the background art, and an object of the present invention is to provide a high-speed switching circuit that can increase the switching speed without particularly limiting the transistor size. And

  To achieve the above object, a high-speed switching circuit according to the present invention includes a first transistor that applies an input signal to a control terminal, and a first transistor that is connected between an output terminal and a power supply terminal of the first transistor. A load circuit, a second load circuit and a second transistor connected in series between an output terminal of the first transistor and a power supply terminal, an output terminal of the first transistor, and a control terminal of the second transistor And a delay circuit connected between the two.

  Further, the delay circuit in the high-speed switching circuit is constituted by at least one or more logic buffer circuits, and the first load circuit and / or the second load circuit is constituted by a constant current source.

  According to the said structure, a high-speed switching operation | movement can be performed by setting appropriately the transmission delay time of a delay circuit.

  According to the present invention, the size of the transistors constituting the circuit is not particularly limited, and the impedance conversion means corresponding to the output level can be operated in an appropriate time according to the transmission delay time of the delay circuit. There is an effect that switching operation becomes possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a high-speed switching circuit according to an embodiment of the present invention. Here, components having the same functions corresponding to the components described in FIG. 3 showing the conventional example are denoted by the same reference numerals.

  As shown in FIG. 1, the drain terminal of the NMOS transistor 5 is connected to the power supply terminal 1 through the resistor 3, and the drain terminal of the PMOS transistor 7 and the gate terminals of the PMOS transistor 9 and the NMOS transistor 10 constituting the inverter circuit. It is connected to the. Further, as a delay circuit, the logic buffer circuit 11 and the logic buffer circuit 12 whose transmission delay time is Δtd are configured and connected to the drain terminals of the PMOS transistor 9 and the NMOS transistor 10 so as to have a transmission delay time of 2 × Δtd. Has been.

  In FIG. 1, the broken line shown at the output of the logical buffer circuit 11 and the input of the logical buffer circuit 12 and the broken line shown at the output of the logical buffer circuit 13 are Δtd or 3 × Δtd. A connection method in the case of such a configuration is shown. That is, when the transmission delay time is set to Δtd, the output of the logic buffer circuit 11 is connected to the input of the inverter 8 and the logic buffer circuit 12 and the logic buffer circuit 13 are not connected. When the transmission delay time is 3 × Δtd, the logic buffer circuit 11, the logic buffer circuit 12, and the logic buffer circuit 13 are connected, and the output of the logic buffer circuit 13 is connected to the input of the inverter 8.

  The output of the inverter 8 is connected to the gate terminal of the PMOS transistor 7, and the source terminal of the PMOS transistor 7 is connected to the power supply terminal 1 via the resistor 6. Here, the gate terminal of the NMOS transistor 5 is the input terminal 4.

  The operation of the embodiment configured as described above will be described with reference to FIG. FIG. 2 shows the time change of the voltage Vd at the drain terminal of the NMOS transistor 5 shown in FIG. 1 and the resistors (resistors 3 and 6) connected to the drain terminal.

  As shown in FIG. 2, before the time t0, since the gate terminal of the NMOS transistor 5 is at the low level, the NMOS transistor 5 is turned off, and the voltage Vd at the drain terminal of the NMOS transistor 5 is at the high level. Since the NMOS transistor 10 is in the on state and the PMOS transistor 9 is in the off state, the input of the logic buffer circuit 11 and the output of the logic buffer circuit 12 are at the high level, so the output of the inverter 8 is at the low level and the PMOS transistor 7 is off. It is in a state.

  Next, when the gate terminal of the NMOS transistor 5 changes from the low level to the high level at time t0, the NMOS transistor 5 changes from the off state to the on state, and current starts to flow to the drain terminal of the NMOS transistor 5 through the resistor 3. In this case, since the PMOS transistor 7 is still in the off state, the drain terminal of the NMOS transistor 5 only has to flow current from the resistor 3, and no current flows from the resistor 6. Therefore, since the NMOS transistor 5 drives a relatively large resistance (resistor 3) from the high level to the low level, the voltage Vd becomes steep as indicated by the slope A in FIG. 2, and the potential decreases rapidly.

  Here, if the time from the time t0 when the potential of the drain terminal voltage Vd of the NMOS transistor 5 decreases and the output of the inverter circuit composed of the PMOS transistor 9 and the NMOS transistor 10 changes from the low level to the high level is ignored, After the transmission delay time 2 × Δtd generated in the buffer circuit 11 and the logic buffer circuit 12, the output of the inverter 8 changes from the high level to the low level. Then, since the PMOS transistor 7 is turned on after time t1, the load resistance of the NMOS transistor 5 is connected in parallel with the resistor 3 and the resistor 6, and the potential drop of the voltage Vd at the drain terminal of the NMOS transistor 5 becomes gentle.

  Further, if the transmission delay time 2 × Δtd is set to 3 × Δtd, for example, the time t1 in FIG. 2 moves further to the right, and it is possible to change to the low level while maintaining the steep slope A state. The fall time of the voltage Vd becomes faster.

  Next, between time t1 and time t2, the NMOS transistor 5 and the PMOS transistor 7 are in the on state, and the load resistance of the NMOS transistor 5 changes with the parallel connection of the resistor 3 and the resistor 6. When the gate terminal of the NMOS transistor 5 changes from high level to low level at time t2, the NMOS transistor 5 changes from on to off. In this case, since the load resistance of the NMOS transistor 5 is maintained in a low impedance state in which the resistors 3 and 6 are connected in parallel, the voltage Vd at the drain terminal of the NMOS transistor 5 is charged through the low impedance resistor. As indicated by the slope B in FIG. 2, the slope changes from a low level to a high level with a steep slope.

  If the time for the voltage Vd of the drain terminal of the NMOS transistor 5 to rise from the time t2 and the output of the inverter circuit composed of the PMOS transistor 9 and the NMOS transistor 10 change from the high level to the low level is ignored, the logic buffer circuit 11 The output of the inverter 8 changes from the low level to the high level after the transmission delay time 2 × Δtd generated in the logic buffer circuit 12. Here, if the transmission delay time 2 × Δtd is set to 3 × Δtd, for example, the time t3 in FIG. 2 moves further to the right, and can be changed to a high level while maintaining the steep slope B state. The rise time of the voltage Vd becomes earlier.

  In the above-described embodiment, the resistor 3 and the resistor 6 are used. However, the same effect can be obtained by using a constant current source instead of the resistor.

  The high-speed switching circuit according to the present invention does not particularly require restriction on the size of the transistors constituting the circuit, and the impedance conversion means according to the output level is operated in an appropriate time according to the transmission delay time of the delay circuit, so that the high-speed switching Speed is obtained, and it is useful for speeding up the change speed of the high and low levels along with the transmission of the input logic signal.

The circuit diagram which shows the high-speed switching circuit in embodiment of this invention The figure which shows the operation | movement waveform of the high-speed switching circuit in this Embodiment Circuit diagram showing conventional high-speed switching circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Ground terminal 3, 6, 16 Resistance 4 Input terminal 5, 10, 15 NMOS transistor 7, 9 PMOS transistor 8 Inverter 11, 12, 13 Logic buffer circuit 14 Output terminal

Claims (3)

  A first transistor for applying an input signal to a control terminal; a first load circuit connected between an output terminal of the first transistor and a power supply terminal; and an output terminal of the first transistor and the power supply terminal A second load circuit and a second transistor connected in series with each other, and a delay circuit connected between the output terminal of the first transistor and the control terminal of the second transistor. A high-speed switching circuit.   2. The high-speed switching circuit according to claim 1, wherein the delay circuit includes at least one logic buffer circuit.   2. The high-speed switching circuit according to claim 1, wherein the first load circuit and / or the second load circuit is constituted by a constant current source.

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