JP4559826B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit for converting a logic level, and more particularly, to a circuit having a low power consumption and low voltage operation.

  Conventionally, there is a level shift circuit described in Patent Document 1. The configuration of this level shift circuit is shown in FIG.

  The level shift circuit shown in FIG. 2 includes two N-type transistors N5 and N6, two P-type transistors P1 and P2 having cross-couple connections whose gates are connected to the other drain, and first and second transistors. Inverters INV1 and INV2 are provided. The first inverter INV1 includes an N-type transistor N13 whose source is grounded and a P-type transistor P11 whose source is connected to the low voltage source VDD, and is configured by connecting the drains and gates of these transistors. Has been. The inverter INV2 also includes an N-type transistor N14 whose source is grounded and a P-type transistor P12 whose source is connected to the low voltage source VDD, and is configured by connecting the drains and gates of these transistors. . The first and second inverters INV1 and INV2 invert the input signal of the input terminal IN and operate with a low voltage source VDD such as 1.5V.

  The elements other than the first and second inverters INV1 and INV2 are elements on the high voltage side operating with a high voltage source VDD3 such as 3.3V, and the two N-type transistors N5 and N6 are respectively The source receives mutually complementary signals, that is, an inverted signal of the input signal from the first inverter INV1, and a signal having the same level as the input signals from the first and second inverters. The gates of the N-type transistors N5 and N6 are connected to the low voltage source VDD. The P-type transistors P1 and P2 have sources connected to the high voltage source VDD3, drains connected to the drains of the N-type transistors N5 and N6, respectively, and the connection point between the N-type transistor N6 and the P-type transistor P2 is the output terminal OUT. It is connected to the.

Next, the operation of the level shift circuit will be described. When the input signal is at the H (voltage of the low voltage source VDD) level and its inverted signal is at the L (VSS = 0V) level, the N-type transistor N5 is ON, the N-type transistor N6 is OFF, the P-type transistor P1 is OFF, P The type transistor P2 is turned on, and the H (VDD3) level is output to the output terminal OUT. Conversely, when the input signal is at L (VSS = 0 V) level and its inverted signal is at H (VDD) level, the N-type transistor N5 is OFF, the N-type transistor N6 is ON, the P-type transistor P1 is ON, and the P-type transistor P2 is turned off, and the L (VSS = 0V) level is output to the output terminal OUT. The operation as described above is performed, and the level shift circuit of FIG. 14 outputs a signal obtained by level-shifting the input signal of the low voltage source VDD to the signal of the high voltage source VDD3.
Japanese Patent Laid-Open No. 4-40798

  However, the conventional level shift circuit shown in FIG. 14 does not operate when the voltage of the low voltage source VDD is set low, for example, near the threshold voltage of the N-type transistors N5 and N6. Therefore, if the threshold voltages of the N-type transistors N5 and N6 are changed and set to a low threshold voltage of 0 V, for example, the level shift circuit of FIG. Performs the desired level shift operation well.

  Consider the operation of the level shift circuit of FIG. 14 when the threshold voltages of the N-type transistors N5 and N6 are set low. For example, when the input signal is L level, the drain voltage of the N-type transistor N5 becomes the voltage of the high voltage source VDD3, the N-type transistor N5 is turned off, and the potential of the source node W3 of the N-type transistor N5 is ( VDD-threshold voltage). However, if the threshold voltage of the N-type transistor N5 varies due to variations in temperature, manufacturing process, etc., and the threshold voltage decreases to a negative value, the potential of the node W3 increases to reduce the voltage of the low voltage source VDD. May exceed. In this case, a current flows from the node W3 to the low voltage source VDD via the parasitic diode in the inverter INV1, and the power consumption increases.

  An object of the present invention is to consider the source of the N-type transistors when the threshold voltages of the N-type transistors N5 and N6 on the high voltage side are set low in consideration of setting the power supply voltage of the low voltage source VDD low. An object of the present invention is to provide a level shift circuit capable of preventing an increase in power consumption by preventing a current from flowing into the low voltage source VDD even when the potential exceeds the voltage of the low voltage source VDD.

  In order to achieve the above object, in the present invention, the input signal of the low voltage source VDD is not input to the sources of the first and second N-type transistors on the high voltage source side as in the prior art, but to the source input. Instead, a configuration in which the low voltage source side N-type transistor is input to the gate is employed to prevent the current from flowing into the low voltage source VDD, and the low voltage source side N type transistor and the high voltage source side N type transistor. In the meantime, a configuration in which a protection circuit for limiting the voltage applied to the drain of the low voltage source side N-type transistor is inserted is employed to prevent the breakdown of the low voltage source side N type transistor.

That is, in the level shift circuit according to the first aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gate, one end is grounded, and the other end is the first and first. Two low-voltage side N-type transistors for signal input respectively connected to two nodes, one end connected to the third and fourth nodes, and the other end connected to the fifth and sixth nodes, respectively Two high voltage side N-type transistors whose gates are supplied with the voltage of the low voltage source , one end connected to the high voltage source, and the other end connected to the fifth and sixth nodes, A power supply circuit that supplies the voltage of the high voltage source to one of the fifth and sixth nodes and simultaneously cuts off the supply of the high voltage source to the other; and the first node and the third node And between the second node and the fourth node, the first node The beauty voltage of the second node, characterized in that a protection circuit for limiting to less than or equal to the voltage of the low voltage source.

  According to a second aspect of the present invention, in the level shift circuit according to the first aspect, one end of the protection circuit is connected to the first and second nodes, and the other end is the third and fourth nodes. Each having two protective N-type transistors connected to each other.

  According to a third aspect of the present invention, in the level shift circuit according to the second aspect, the two N-type transistors for protection in the protection circuit are supplied with the voltage of the low voltage source at their gates. Features.

According to a fourth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gate, one end is grounded, and the other end is connected to the first and second nodes. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high-voltage side N-type transistors to which the voltage of the voltage source is supplied, one end connected to the high voltage source, the other end connected to the fifth and sixth nodes, respectively, the fifth and sixth A power supply circuit for supplying the voltage of the high voltage source to one of the nodes at the same time and shutting off the supply of the high voltage source to the other, between the first node and the third node, and the second node Between the first node and the fourth node, the voltage of the first and second nodes is A protection circuit for limiting the voltage to a voltage of a low voltage source or less, wherein the protection circuit has one end connected to the first and second nodes, and the other end connected to the third and fourth nodes, respectively. Two protective N-type transistors, and the two protective N-type transistors of the protective circuit have their complementary first and second input signals via a delay circuit at the gates thereof. Each of which is inputted.

According to a fifth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high-voltage side N-type transistors to which the voltage of the voltage source is supplied, one end connected to the high voltage source, the other end connected to the fifth and sixth nodes, respectively, the fifth and sixth A power supply circuit for supplying the voltage of the high voltage source to one of the nodes at the same time and shutting off the supply of the high voltage source to the other, between the first node and the third node, and the second node Between the first node and the fourth node, the voltage of the first and second nodes is A protection circuit for limiting the voltage to a voltage of a low voltage source or less, wherein the protection circuit has one end connected to the first and second nodes, and the other end connected to the third and fourth nodes, respectively. Each of the protection N-type transistors of the protection circuit has the complementary first and second input signals directly input to the gates thereof, respectively. It is characterized by that.

According to the sixth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gate, one end is grounded, and the other end is connected to the first and second nodes. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high-voltage side N-type transistors to which the voltage of the voltage source is supplied, one end connected to the high voltage source, the other end connected to the fifth and sixth nodes, respectively, the fifth and sixth A power supply circuit for supplying the voltage of the high voltage source to one of the nodes at the same time and shutting off the supply of the high voltage source to the other, between the first node and the third node, and the second node Between the first node and the fourth node, the voltage of the first and second nodes is Serial and a protection circuit for limiting to less than or equal to the voltage of the low voltage source, the protection circuit has a cathode connected respectively to said first and second nodes, the anode is respectively connected to said third and fourth nodes And having two protective diodes .

In the level shift circuit according to the seventh aspect of the invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gates, one end is grounded, and the other end is the first and second inputs. Two low-voltage side N-type transistors for signal input respectively connected to the node, one end connected to the third and fourth nodes, and the other end connected to the fifth and sixth nodes, Two complementary input signals having the low voltage source as a power source are input to the gate, and the first and second input signals are at a high potential level. A high voltage side N-type transistor, one end is connected to a high voltage source, the other end is connected to each of the fifth and sixth nodes, and the voltage of the high voltage source is connected to one of the fifth and sixth nodes. Power supply circuit that cuts off the supply of the high voltage source to the other And between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is the voltage of the low voltage source. And a protection circuit limited to the following.

According to an eighth aspect of the present invention, in the level shift circuit according to the seventh aspect, one end of the protection circuit is connected to the first and second nodes, and the other end is the third and fourth nodes. Each having two protective N-type transistors connected to each other.

According to a ninth aspect of the present invention, in the level shift circuit according to the eighth aspect, the two protection N-type transistors of the protection circuit are supplied with the voltage of the low voltage source at their gates. Features.

In the level shift circuit according to the tenth aspect, complementary first and second input signals having a low voltage source as a power source are respectively input to the gates, one end is grounded, and the other end is the first and second. Two low-voltage side N-type transistors for signal input respectively connected to the node, one end connected to the third and fourth nodes, and the other end connected to the fifth and sixth nodes, Two complementary input signals having the low voltage source as a power source are input to the gate, and the first and second input signals are at a high potential level. A high voltage side N-type transistor, one end is connected to a high voltage source, the other end is connected to each of the fifth and sixth nodes, and the voltage of the high voltage source is connected to one of the fifth and sixth nodes. Power supply to cut off the supply of the high voltage source to the other at the same time And a voltage between the first node and the third node and between the second node and the fourth node, and the voltages of the first and second nodes are A protection circuit for limiting the voltage to less than a voltage, the protection circuit having two ends connected to the first and second nodes, respectively, and the other end connected to the third and fourth nodes, respectively. The N-type transistors for protection are provided, and the two first-type and second-type input signals are input to the gates of the two N-type transistors for protection in the protection circuit via the delay circuits, respectively. It is characterized by that.

In the level shift circuit according to the eleventh aspect of the invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gates, one end is grounded, and the other end is the first and second inputs. Two low-voltage side N-type transistors for signal input respectively connected to the node, one end connected to the third and fourth nodes, and the other end connected to the fifth and sixth nodes, Two complementary input signals having the low voltage source as a power source are input to the gate, and the first and second input signals are at a high potential level. A high voltage side N-type transistor, one end is connected to a high voltage source, the other end is connected to each of the fifth and sixth nodes, and the voltage of the high voltage source is connected to one of the fifth and sixth nodes. Power supply to cut off the supply of the high voltage source to the other at the same time And a voltage between the first node and the third node and between the second node and the fourth node, and the voltages of the first and second nodes are A protection circuit for limiting the voltage to less than a voltage, the protection circuit having two ends connected to the first and second nodes, respectively, and the other end connected to the third and fourth nodes, respectively. A protective N-type transistor is provided, and each of the protective N-type transistors of the protection circuit has the complementary first and second input signals directly input to the gates thereof. .

In a level shift circuit according to a twelfth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are respectively input to the gates, one end is grounded, and the other end is the first and second inputs. Two low-voltage side N-type transistors for signal input respectively connected to the node, one end connected to the third and fourth nodes, and the other end connected to the fifth and sixth nodes, Two complementary input signals having the low voltage source as a power source are input to the gate, and the first and second input signals are at a high potential level. A high voltage side N-type transistor, one end is connected to a high voltage source, the other end is connected to each of the fifth and sixth nodes, and the voltage of the high voltage source is connected to one of the fifth and sixth nodes. Power supply to cut off the supply of the high voltage source to the other at the same time And a voltage between the first node and the third node and between the second node and the fourth node, and the voltages of the first and second nodes are A protection circuit for limiting the voltage to less than or equal to a voltage, wherein the protection circuit has two protections, each having a cathode connected to the first and second nodes and an anode connected to the third and fourth nodes, respectively. It has a diode for use.

In the invention described in claim 13, complementary first and second input signals having a low voltage source as a power source are respectively input to the gate, one end is grounded, and the other end is connected to the first and second nodes. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high voltage sides N that are turned on when the complementary first and second input signals having a voltage source as a power source are input and the first and second input signals are at a high potential level. A transistor having one end connected to the high voltage source and the other end connected to the fifth and sixth nodes, respectively, and simultaneously supplying the voltage of the high voltage source to one of the fifth and sixth nodes. A power supply circuit that cuts off the supply of the high voltage source, and the first Protection between the first node and the third node and between the second node and the fourth node to limit the voltage of the first and second nodes to a voltage of the low voltage source or less. and a circuit, the two high-voltage N-type transistors, respectively, to the gate, characterized in that the stop mode signal which becomes a low potential level when stopping the level shift circuit is inputted.

According to the fourteenth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high voltage sides N that are turned on when the complementary first and second input signals having a voltage source as a power source are input and the first and second input signals are at a high potential level. A transistor having one end connected to the high voltage source and the other end connected to the fifth and sixth nodes, respectively, and simultaneously supplying the voltage of the high voltage source to one of the fifth and sixth nodes. A power supply circuit that cuts off the supply of the high voltage source, and the first Protection between the first node and the third node and between the second node and the fourth node to limit the voltage of the first and second nodes to a voltage of the low voltage source or less. The two high-voltage side N-type transistors have the complementary first and second input signals input to their gates via delay circuits, respectively.

According to the fifteenth aspect of the present invention, complementary first and second input signals having a low voltage source as a power source are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. The two low-voltage side N-type transistors for signal input, one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate connected to the low-voltage side N-type transistor Two high voltage sides N that are turned on when the complementary first and second input signals having a voltage source as a power source are input and the first and second input signals are at a high potential level. A transistor having one end connected to the high voltage source and the other end connected to the fifth and sixth nodes, respectively, and simultaneously supplying the voltage of the high voltage source to one of the fifth and sixth nodes. A power supply circuit that cuts off the supply of the high voltage source, and the first Protection between the first node and the third node and between the second node and the fourth node to limit the voltage of the first and second nodes to a voltage of the low voltage source or less. The two high-voltage side N-type transistors are characterized in that the complementary first and second input signals are directly inputted to the gates thereof, respectively.

A sixteenth aspect of the present invention is the level shift circuit according to any one of the first to fifteenth aspects, wherein the level shift circuit is disposed between the third and fourth nodes and the low voltage source, respectively. The first and second clamp circuits are provided for clamping the third and fourth nodes to the voltage of the low voltage source, respectively.

The invention according to claim 17 is the level shift circuit according to any one of claims 1 to 16 , wherein each of the two high-voltage side N-type transistors has a threshold voltage of the two signals. It is characterized by being set lower than the threshold voltage of the low voltage side N-type transistor for input.

As described above, in the first to 17th aspects of the present invention, two N-type transistors for complementary signal input are connected in series to the two N-type transistors on the high voltage side, respectively. Each N-type transistor has a configuration in which a low-voltage complementary signal is input to the gates thereof, so there is no current path from the source terminal of the high-voltage N-type transistor to the complementary signal generating inverter. Therefore, the current is prevented from flowing from the source terminal of the N-type transistor on the high voltage side to the low voltage source VDD via the parasitic diode of the inverter for generating the complementary signal as in the prior art.

  Moreover, even if the voltage at the source terminal of the high-voltage side N-type transistor becomes a high voltage exceeding the voltage of the low-voltage source VDD, these high-voltage side N-type transistors and the complementary signal input N-type transistor Since a protection circuit is inserted between the N-type transistor and the N-type transistor for complementary signal input, the drain potential of the N-type transistor for complementary signal input is limited to less than the voltage of the low voltage source VDD. It is reliably prevented that a potential higher than the voltage of the low voltage source VDD is applied between the terminals of the type transistor.

Further, in the invention described in claim 16 , a clamp circuit is connected to the sources of the two N-type transistors on the high voltage side, and each clamp circuit sets the source potential of these N-type transistors to the low voltage source VDD. Therefore, even if the source potential of the N-type transistor on the high voltage side exceeds the voltage of the low voltage source VDD, the source potential can be limited to the voltage of the low voltage source VDD or less. . Therefore, it is possible to reliably prevent the voltage of the low voltage source VDD from being applied between the terminals of the protection circuit.

In addition, in the invention according to claim 17 , since the threshold voltages of the two N-type transistors on the high voltage side are set low, the level shift circuit is configured even if the voltage of the low voltage source VDD is set low. Works reliably.

As described above, according to the level shift circuit of the first to seventeenth aspects of the present invention, the current flows from the source terminal of the high voltage side N-type transistor through the parasitic diode of the inverter for generating the complementary signal to the low voltage source VDD. And the power consumption can be reduced, and even if the voltage of the source terminal of the N-type transistor on the high voltage side becomes a high voltage exceeding the voltage of the low voltage source VDD, the complementary signal Since the N-type transistor for complementary signal input receiving at the gate is protected by the protection circuit, it is surely prevented that a potential higher than the voltage of the low voltage source VDD is applied between the terminals of the N-type transistor for complementary signal input. Thus, the operation of the level shift circuit can be ensured.

According to the sixteenth aspect of the present invention, the source potentials of the two N-type transistors on the high voltage side are each clamped to the voltage of the low voltage source VDD at the maximum by the clamp circuit. It is possible to reliably prevent the voltage of the low voltage source VDD from being applied.

In addition, according to the seventeenth aspect of the present invention, since the threshold voltages of the two N-type transistors on the high voltage side are set low, this level shift circuit can be used even when the voltage of the low voltage source VDD is set low. Can be secured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  In the figure, IN is a signal input terminal, INV1 is an inverter that inverts the signal input to the input terminal IN, INV2 is an inverter that inverts the signal input to the inverter INV1, for example 1.5V, etc. The low voltage source VDD operates.

  In FIG. 1, N1 and N2 are a pair of complementary signal N-type transistors on the low voltage side, and their sources are grounded. An inverted signal (one of the first and second signals constituting the complementary signal) XIN of the inverter INV1 is input to the gate of one N-type transistor (first N-type transistor) N1, and the other An inverted signal (the other of the first and second signals constituting the complementary signal) XXIN of the inverter INV2 is input to the gate of the N-type transistor (second N-type transistor) N2.

  A protective N-type transistor (third N-type transistor) N3 is connected to the drain of the signal input N-type transistor N1, and the connection point is defined as a first node W1. A low voltage source VDD is connected to the gate of the protective N-type transistor N3. Similarly, a protective N-type transistor (fourth N-type transistor) N4 is connected to the drain of the signal input N-type transistor N2, and the connection point is defined as a second node W2. A low voltage source VDD is connected to the gate of the protective N-type transistor N4.

  In the level shift circuit of FIG. 1, all the elements other than the inverters INV1 and INV2, the N-type transistors N1 and N2 for inputting complementary signals, and the two N-type transistors N3 and N4 for protection are, for example, This is an element on the high voltage side that operates with a high voltage source VDD3 such as 3.3V.

  A high voltage side N-type transistor (fifth N-type transistor) N5 is connected to the drain of the protective N-type transistor N3, and the connection point is defined as a third node W3. The low voltage source VDD is input to the gate of the N-type transistor N5 on the high voltage side. A high voltage side N-type transistor (sixth N-type transistor) N6 is connected to the drain of the protective N-type transistor N4, and the connection point is defined as a fourth node W4. The low voltage source VDD is input to the gate of the N-type transistor N6 on the high voltage side.

  In FIG. 1, P1 and P2 are a pair of P-type transistors, the source is connected to the high voltage source VDD3, the gates are cross-coupled to the other drain, and the drains are each N-side on the high voltage side. Connected to the drains of the type transistors N5 and N6. A connection point between the one P-type transistor (first P-type transistor) P1 and the high-voltage side N-type transistor N5 is a fifth node W5, and the other P-type transistor (second P-type transistor) P2 A connection point with the high-voltage side N-type transistor N6 is defined as a sixth node W6. The output terminal OUT is connected to the node W6. The two P-type transistors P1 and P2 constitute a power supply circuit A, and the two protection N-type transistors N3 and N4 constitute a protection circuit B.

  The threshold voltage of the N-type transistors N1 and N2 for complementary signal input is set to a normal value, for example, 0.3v. On the other hand, the threshold voltage of the N-type transistors N5 and N6 on the high voltage side is set to 0 V, for example, which is lower than the threshold voltage (0.3 v) of the N-type transistors N1 and N2 for complementary signal input. Further, the threshold voltages of the two N-type transistors N3 and N4 constituting the protection circuit B are set to, for example, 0.3 V similarly to the N-type transistors N1 and N2 for complementary signal input. Further, the threshold voltage of the pair of P-type transistors P1 and P2 is set to a normal value, for example, 0.7v.

  The operation of the level shift circuit configured as described above will be described below. First, in a steady state when the signal potential of the input terminal IN is at the H (VDD) level, the N-type transistor N1 is OFF, the N-type transistor N2 is ON, the N-type transistor N4 is ON, the N-type transistor N6 is ON, and the P-type The transistor P1 is ON, the P-type transistor P2 is OFF, the N-type transistor N5 is OFF, and the N-type transistor N3 is OFF. The fifth node W5 is at the potential of the high voltage VDD3 (3.3V), and the sixth node W6 is 0V. As a result, L (0 V) level is output from the output terminal OUT.

  At this time, the two N-type transistors N1 and N2 for signal input are composed of elements on the low voltage side having a withstand voltage against the low voltage source VDD, and the threshold voltage thereof is a normal value of 0.3v. If these transistors N1 and N2 are composed of elements on the high voltage side having a withstand voltage with respect to the high voltage source VDD3, the threshold voltage becomes a normal value of, for example, 0.7v. Therefore, in the present embodiment, even if the voltage of the low voltage source VDD is set to be low (0.4 v = 0.7 v−0.3 v) by the low threshold voltage, the level shift circuit of FIG. Operate.

  In addition, when one of the low voltage side N-type transistors N1 for signal input is in the OFF state, the high voltage side N-type transistor N5 is also in the OFF state, and the potential of the fifth node W5 (high voltage) Since the voltage VDD3 (3.3V) is not applied to the low-voltage-side N-type transistor N1 for signal input in the OFF state, the low-voltage-side N-type transistor N1 is not destroyed. Further, the low voltage VDD is connected to the gate of the high-voltage side N-type transistor N5. Even if the voltage of the low-voltage source VDD is set to be even lower, the high-voltage side N-type transistor N5. Since the threshold voltage is 0 V lower than the normal value, the high voltage side N-type transistor N5 operates well.

  Further, when the threshold voltage of the high-voltage side N-type transistor N5 varies due to factors such as temperature and manufacturing process variations and falls below 0v and becomes negative, the potential of the node W3 exceeds the voltage of the low-voltage power supply VDD. Even in this case, since the potential of the node W1 becomes a voltage of (VDD−threshold voltage = VDD−0.3v) by the protective N type transistor N3, the N type for signal input is used. It is prevented that a voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the transistor N1.

  Further, since the inverted signal XIN that has passed through the inverter INV1 is input to the gate of the N-type transistor N1 for signal input, current is prevented from flowing from the node W3 to the low voltage source VDD through the parasitic diode of the inverter INV1.

  Contrary to the above, in the steady state when the signal potential of the input terminal IN is at L (0 V) level, the N-type transistor N1 is ON, the N-type transistor N2 is OFF, the N-type transistor N3 is ON, and the N-type transistor N5 is ON, P-type transistor P1 is OFF, P-type transistor P2 is ON, N-type transistor N6 is OFF, and N-type transistor N4 is OFF. The fifth node W5 is at 0V, and the sixth node W6 is at the high voltage VDD3 (3.3V). As a result, H (3.3 V) level is output from the output terminal OUT.

  At that time, even if the voltage of the low voltage source VDD is set to be further lower, the two N-type transistors N1 and N2 for signal input are constituted by the elements on the low voltage side, and the threshold voltage is 0.3 V. The level shift circuit of FIG. 1 operates as expected, and the high-voltage side N-type transistor N6 is in the OFF state, and the low-voltage side N-type transistor N2 is connected to the voltage of the high voltage source VDD3. That the N-type transistor N6 on the high voltage side operates well even when the voltage of the low voltage source VDD is further increased, the signal potential of the input terminal IN described above is H. This is the same as in the steady state at the (VDD) level.

  Furthermore, the threshold voltage of the high-voltage side N-type transistor N6 varies due to factors such as temperature and manufacturing process variations. If the threshold voltage of the high-voltage side N-type transistor N6 decreases, even if the potential of the node W4 exceeds the voltage of the low voltage source VDD, the protective N The potential of the node W2 becomes (VDD−threshold voltage) by the type transistor N4, and it is prevented that a voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the N-type transistor N2 for signal input.

  Further, since the inverted signal IN from the inverter INV2 is input to the gate of the N-type transistor N2 for signal input, current is prevented from flowing from the node W4 to the low voltage source VDD through the parasitic diode of the inverter INV2.

  The threshold voltages of the two N-type transistors N5 and N6 on the high voltage side are low, for example, set to around 0V. Therefore, even if the voltage of the low voltage source VDD is set low, the level shift circuit of FIG. 1 can operate reliably.

(First modification)
FIG. 2 shows a first modification of the first embodiment.

  This modification is obtained by changing the internal configuration of the power supply circuit A of the first embodiment. That is, in the power supply circuit A of FIG. 2, P1 and P2 are a pair of P-type transistors, the source is connected to the high voltage source VDD3, the gate is cross-coupled to the other drain, The drains of N-type transistors N5 and N6 are connected. The connection point between one of these P-type transistors (first P-type transistor) P1 and N-type transistor N5 is the fifth node W5, and the other P-type transistor (second P-type transistor) P2 is connected to the N-type transistor. A connection point with N6 is defined as a sixth node W6.

  P3 and P4 are current cut-off transistors composed of a pair of P-type transistors, the source is connected to the high voltage source VDD3, and the drains are connected to the sources of the P-type transistors P1 and P2, respectively. The connection point between this one current cutoff transistor (third P-type transistor) P3 and the first P-type transistor P1 is the seventh node W7, and the other current cutoff transistor (fourth P-type transistor) P4 A connection point with the second P-type transistor P2 is an eighth node W8. The gate of the one current cutoff transistor P3 is connected to the sixth node W6 via the inverter INV3, and the gate of the other current cutoff transistor P4 is connected to the sixth node via the inverters INV3 and INV4. W6 is connected. An output terminal OUT is connected to the output side of the inverter INV4. In addition, P5 is a resistor composed of a P-type transistor whose gate is grounded, and has one end connected to the seventh node W7 and the other end connected to the eighth node W8.

  In the level shift circuit of FIG. 2 configured as described above, the low power supply side N-type transistors N1 and N2, the high power supply side N-type transistors N5 and N6, and the protection circuit B for inputting complementary signals are an important part of the present invention. And, it is the same as the first embodiment. Further, the operation of the power supply circuit A is different from that of the first embodiment, but is different from the important part of the present invention, and the description thereof is omitted.

(Second modification)
FIG. 3 shows a second modification of the first embodiment.

  In this modification, the internal configuration of the power supply circuit A of the first embodiment is further changed to another configuration.

  That is, the power supply circuit A in FIG. 3 includes a supply circuit configured by a pair of P-type transistors P6 and P7, an intermittent circuit configured by a pair of N-type transistors N7 and N8, and a P that operates as a resistor. A precharge circuit including a type transistor P8. One P-type transistor P6 has a source connected to the high voltage source VDD3 and a drain connected to the fifth node W11. The other P-type transistor P7 has a source connected to the high voltage source VDD3 and a drain connected to the sixth node W12. In the precharge circuit, one N-type transistor N7 is arranged between the fifth node W11 and the N-type transistor N5 in the figure, and the other N-type transistor N8 is connected to the sixth node W12 and the N-type transistor N5. Between the n-type transistor N6. Further, the P-type transistor P8 is connected to the drains (fifth and sixth nodes W11, W12) of the two P-type transistors P6, P7.

  3 further includes a flip-flop circuit having first and second two-input NAND circuits NAND1 and NAND2, and a precharge control circuit constituted by two inverters INV5 and INV6. . The first NAND circuit NAND1 receives the potential of the fifth node W11 and the output signal of the second NAND circuit NAND2, and the second NAND circuit NAND2 receives the potential of the sixth node W12, The output signal of NAND circuit NAND1 is received. The outputs of these first and second NAND circuits become the output of the flip-flop circuit. The precharge control circuit controls the operation of the precharge circuit, and one inverter INV5 receives the output of the first NAND circuit NAND1 of the flip-flop circuit and inverts the inverted signal. Output to the gates of the P-type and N-type transistors P6 and N7 of the precharge circuit. The other inverter INV6 receives and inverts the output of the second NAND circuit NAND2 of the flip-flop circuit, and outputs this inverted signal to the gates of the P-type and N-type transistors P7 and N8 of the precharge circuit.

  In the level shift circuit of FIG. 3 configured as described above, the low power supply side N-type transistors N1 and N2, the high power supply side N-type transistors N5 and N6, and the protection circuit B for inputting complementary signals are an important part of the present invention. And, it is the same as the first embodiment. Further, the operation of the power supply circuit A is different from that of the first embodiment, but is different from the important part of the present invention, and the description thereof is omitted.

(Second Embodiment)
FIG. 4 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  In the figure, the protection circuit B of the level shift circuit of the first embodiment of FIG. 1 is constituted by a diode. That is, the N-type transistors N3 and N4 in FIG. 1 are replaced with protective diodes D1 and D2, respectively. The diode D1 has a cathode connected to the node W1 and an anode connected to the node W3. Similarly, the diode D2 has a cathode connected to the node W2 and an anode connected to the node W4.

  In the level shift circuit configured as described above, the potentials of the nodes W1 and W2 are lower than the potentials of the nodes W3 and W4 by the threshold voltages of the diodes D1 and D2, respectively. A voltage exceeding the voltage of the low voltage source VDD is not applied between the terminals of the N-type transistors N1 and N2. Other operations and functions of the circuit are the same as those in the first embodiment.

  As shown in FIG. 5, each of the diodes D1 and D2 can be composed of N-type transistors N9 and N10. The N-type transistor N9 is connected between the node W1 and the node W3, and the gate is connected to the node W3. The other N-type transistor N10 is connected between the node W2 and the node W4, and its gate is connected to the node W4.

  Furthermore, as shown in FIG. 6, each of the diodes D1 and D2 can be constituted by P-type transistors P9 and P10. The P-type transistor P9 is connected between the node W1 and the node W3, the gate is connected to the node W1, and the back bias node is connected to the node W3. The other P-type transistor P10 is connected between the node W2 and the node W4, the gate is connected to the node W2, and the back bias node is connected to the node W4.

(Third embodiment)
FIG. 7 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  In the present embodiment, a stop mode input signal terminal STOP is added to the gates of the N-type transistors N5 and N6 on the high voltage side of the level shift circuit of the first embodiment shown in FIG. .

  The operation and function of the level shift circuit when a stop mode signal of H (1.5 V) level (voltage of the low voltage source VDD) is input to the stop mode input terminal STOP is the same as that of the first embodiment. is there. When a stop mode signal of L (0 V) level is input to the stop mode input terminal STOP, the N-type transistors N5 and N6 on the high voltage side are turned off to stop this level shift circuit, and the high voltage source This prevents a through current from flowing from VDD3 to ground.

  As in the second embodiment, the protection circuit B employs the diode shown in FIG. 4, 5 or 6 instead of connecting the low voltage source VDD to the gates of the N-type transistors N3 and N4. You may do it.

(Fourth embodiment)
FIG. 8 is a diagram showing a specific configuration of the level shift circuit of the fourth embodiment.

  This figure is inputted to the gates of high voltage side N-type transistors N5 and N6, respectively, to the gates of signal input N-type transistors N1 and N2 in the level shift circuit of the first embodiment of FIG. In this configuration, one and the other of the complementary input signals are respectively input via the delay circuit 15. Other configurations are the same as those of the first embodiment.

  In the present embodiment, when the signal potential of the input terminal IN is at the H (VDD) level, the L (0 V) level is input to the gate of the high voltage side N-type transistor N5 after a predetermined fixed delay time. The The H (VDD) level is input to the gate of the other high-voltage side N-type transistor N6 through a predetermined constant delay time. N-type transistor N1 is OFF, N-type transistor N2 is ON, N-type transistor N4 is ON, N-type transistor N6 is ON, P-type transistor P1 is ON, P-type transistor P2 is OFF, N-type transistor N5 is OFF, N The type transistor N3 is ON. The fifth node W5 is at the potential (3.3V) of the high voltage source VDD3, and the sixth node W6 is 0V. As a result, L (0 V) level is output from the output terminal OUT. At this time, since the potential of the first node W1 is 0 V, no voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the N-type transistor N1 for signal input.

  On the other hand, when the signal potential of the input terminal IN is at L (0 V) level, the H (VDD) level is input to the gate of the high-voltage side N-type transistor N5 after a predetermined constant delay time. The L (0 V) level is input to the gate of the other high-voltage side N-type transistor N6 through a predetermined constant delay time. N-type transistor N1 is ON, N-type transistor N2 is OFF, N-type transistor N3 is ON, N-type transistor N5 is ON, P-type transistor P1 is OFF, P-type transistor P2 is ON, N-type transistor N6 is OFF, N The type transistor N4 is ON. The fifth node W5 is 0V, and the sixth node W6 is the potential (3.3V) of the high voltage source VDD3. As a result, H (3.3 V) level is output from the output terminal OUT. At this time, since the potential of the second node W2 is 0 V, no voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the N-type transistor N2 for signal input. Other functions are the same as those in the first embodiment.

  As in the second embodiment, a diode may be employed as the protection circuit B instead of connecting the low voltage source VDD to the gates of the protective N-type transistors N3 and N4.

(Fifth embodiment)
FIG. 9 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  This figure shows a configuration in which the output signal of the delay circuit 15 is input to the gates of the protective N-type transistors N3 and N4 in the level shift circuit of the fourth embodiment shown in FIG. .

  In the level shift circuit of the present embodiment, when the signal potential of the input terminal IN is at the H (VDD) level, the gates of the protective N-type transistor N3 and the high-voltage side N-type transistor N5 are connected to a predetermined constant level. The L (0 V) level is input after a delay time. The H (VDD) level is input to the gates of the other N-type transistor N4 for protection and the N-type transistor N6 on the high voltage side through a predetermined constant delay time. N-type transistor N1 is OFF, N-type transistor N2 is ON, N-type transistor N4 is ON, N-type transistor N6 is ON, P-type transistor P1 is ON, P-type transistor P2 is OFF, N-type transistor N5 is OFF, N The type transistor N3 is OFF. The fifth node W5 is at the potential (3.3V) of the high voltage source VDD3, and the sixth node W6 is 0V. As a result, L (0 V) level is output from the output terminal OUT. At this time, since the potential of the first node W1 is 0 V, no voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the N-type transistor N1 for signal input.

  On the other hand, when the signal potential of the input terminal IN is at L (0 V) level, the protective N-type transistor N3 and the gate of the high-voltage side N-type transistor N5 receive H (VDD) after a predetermined fixed delay time. ) The level is entered. The L (0 V) level is input to the gates of the other N-type transistor N4 for protection and the N-type transistor N6 on the high voltage side through a predetermined constant delay time. N-type transistor N1 for signal input is ON, N-type transistor N2 is OFF, N-type transistor N3 for protection is ON, N-type transistor N5 is ON, P-type transistor P1 is OFF, P-type transistor P2 is ON, N The type transistor N6 is OFF and the N type transistor N4 is OFF. The fifth node W5 is at 0V, and the sixth node W6 is at the high voltage VDD3 (3.3V). As a result, H (3.3 V) level is output from the output terminal OUT. At this time, since the potential of the second node W2 becomes 0V, no voltage exceeding the low voltage source VDD is applied between the terminals of the N-type transistor N2 for signal input. Other functions are the same as those in the first embodiment.

(Sixth embodiment)
FIG. 10 is a diagram showing a specific configuration of the level shift circuit according to the sixth embodiment.

  This figure shows that in the level shift circuit of the first embodiment shown in FIG. 1, the gates of N-type transistors N5 and N6 on the high voltage side are respectively input to the gates of N-type transistors N1 and N2 for signal input. The complementary signal to be input is input. Other configurations are the same as those in the first embodiment.

  The operation of the level shift circuit of this embodiment is similar to that of the fourth embodiment shown in FIG. 8 in that the N-type transistor N5 on the high voltage side is after the N-type transistor N1 for signal input is turned on or off. Instead of turning on or off after a predetermined fixed delay time, both the N-type transistors N1 and N5 for signal input and high voltage are turned on or off at the same time. Similarly, the other N-type transistor N6 on the high voltage side does not turn on or off after a predetermined fixed delay time after the N-type transistor N2 for signal input is turned on or off. Both N-type transistors N2 and N6 for high voltage are turned ON or OFF simultaneously. Other circuit operations and functions are the same as those in the fourth embodiment.

  As in the second embodiment, a diode may be employed as the protection circuit B instead of connecting the low voltage source VDD to the gates of the protective N-type transistors N3 and N4.

(Seventh embodiment)
FIG. 11 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  In the level shift circuit of the sixth embodiment shown in FIG. 10, the gate of the N-type transistors N3 and N4 for protection is also connected to the gates of the N-type transistors N1 and N2 for signal input, respectively. Complementary signal is input.

  Compared with the fifth embodiment shown in FIG. 9, the operation of this level shift circuit is such that both the protective and high-voltage N-type transistors N3 and N5 are turned on or off by the N-type transistor N1 for signal input. After that, the signal input, protection, and high-voltage side N-type transistors N1, N3, and N5 are all turned on or off at the same time, instead of turning on or off after a predetermined fixed delay time. Similarly, both the protective and high-voltage N-type transistors N4 and N6 are not turned on or off after a predetermined fixed delay time after the signal-input N-type transistor N2 is turned on or off. The N-type transistors N2, N4, and N6 for signal input, protection, and high voltage are all turned on or off simultaneously. The operation and function of other circuits are the same as those in the fifth embodiment.

(Eighth embodiment)
FIG. 12 is a diagram showing a specific configuration of the level shift circuit of the present embodiment.

  The level shift circuit of this embodiment is the same as that of the level shift circuit of the first embodiment shown in FIG. 1 except that the second level shift circuit is connected between the node W3 and the low voltage source VDD and between the node W4 and the low voltage source VDD. The first and second clamp circuits 16 are added.

  FIG. 13 shows an example of the clamp circuit 16. In FIG. 6A, a diode is constituted by the diode D3, and in FIG. 4B, it is constituted by one or more transistors (in the figure, two N-type transistors N11 and N12).

  The N-type transistors N5 and N6 on the high voltage side have variations in threshold voltage due to variations in temperature and manufacturing process. Due to these variations, the potentials of the nodes W3 and W4 exceed the voltage of the low voltage source VDD. In this embodiment, when the potentials of the nodes W3 and W4 become higher than the voltage of the low voltage source VDD, the charges of the nodes W3 and W4 escape to the low voltage source VDD by the clamp circuit 16 in this embodiment. Therefore, no voltage exceeding the voltage of the low voltage source VDD is applied between the terminals of the protective N-type transistors N3 and N4. Other operations and functions of the circuit are the same as those in the first embodiment.

  In this embodiment, the clamp circuit 16 is added to the configuration of the level shift circuit of the first embodiment. However, the clamp circuit 16 may be added to the level shift circuit of the second to seventh embodiments. Of course it is good.

  As described above, the present invention can prevent the current from flowing from the source terminal of the N-type transistor on the high voltage side to the low voltage source through the parasitic diode of the inverter for generating the complementary signal, and the N voltage on the high voltage side. Even if the voltage at the source terminal of the transistor is higher than the voltage of the low voltage source, the N-type transistor for complementary signal input that receives the complementary signal at the gate is protected by the protection circuit, so the low voltage source is reduced. Even when the voltage is applied, it is useful as a level shift circuit or the like that can ensure operation while reducing power consumption.

It is a figure which shows the structure of the level shift circuit of the 1st Embodiment of this invention. It is a figure which shows the 1st modification of the level shift circuit of the embodiment. It is a figure which shows the 2nd modification of the level shift circuit of the embodiment. It is a figure which shows the structure of the level shift circuit of the 2nd Embodiment of this invention. It is a figure which shows the specific structure of the level shift circuit which comprised the diode used for the level shift circuit of the embodiment with the N-type transistor. It is a figure which shows the specific structure of the level shift circuit which comprised the diode used for the level shift circuit of the embodiment with the P-type transistor. It is a figure which shows the structure of the level shift circuit of the 3rd Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 4th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 5th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 6th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 7th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 8th Embodiment of this invention. (A) is a figure which shows an example which comprised the clamp circuit used for the level shift circuit of the embodiment with the diode, (b) is a figure which shows an example which comprised the clamp circuit with the transistor. It is a figure which shows the structure of the conventional level shift circuit.

IN input terminal OUT output terminal VDD Low voltage source VDD3 High voltage source D1 to D3 Diodes N1 and N2 N-type transistors for complementary signal input N3 and N4 N-type transistors for protection N5 and N6 N-type transistors on the high voltage side P1 P12 P-type transistor INV1 to INV6 Inverter NAND1, NAND2 NAND circuit NOR1, NOR2 NOR circuit W1 to W14 Intermediate node A Power supply circuit B Protection circuit STOP Stop mode terminal 15 Delay circuit 16 Clamp circuit

Claims (17)

Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
Two high-voltage side N-type transistors having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate supplied with the voltage of the low voltage source When,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. A level shift circuit comprising a protection circuit for limiting. The level shift circuit according to claim 1, wherein
The protection circuit is
A level shift circuit comprising two protective N-type transistors each having one end connected to the first and second nodes and the other end connected to the third and fourth nodes, respectively. . The level shift circuit according to claim 2, wherein
The level shift circuit, wherein the two N-type transistors for protection of the protection circuit are supplied with the voltage of the low voltage source at their gates. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
Two high-voltage side N-type transistors having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate supplied with the voltage of the low voltage source When,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
Two protective N-type transistors each having one end connected to the first and second nodes and the other end connected to the third and fourth nodes,
2. The level shift circuit according to claim 1, wherein the two first N-type transistors for protection of the protection circuit receive the complementary first and second input signals via the delay circuit, respectively, at their gates. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
Two high-voltage side N-type transistors having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate supplied with the voltage of the low voltage source When,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
Two protective N-type transistors each having one end connected to the first and second nodes and the other end connected to the third and fourth nodes,
The level shift circuit according to claim 1, wherein the complementary first and second input signals are directly input to the gates of the N-type transistors for protection of the protection circuit, respectively. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
Two high-voltage side N-type transistors having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate supplied with the voltage of the low voltage source When,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
A level shift circuit comprising two protective diodes each having a cathode connected to the first and second nodes and an anode connected to the third and fourth nodes, respectively. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With protective circuit to limit
A level shift circuit characterized by that. The level shift circuit according to claim 7, wherein
The protection circuit is
Two protective N-type transistors having one end connected to the first and second nodes and the other end connected to the third and fourth nodes, respectively.
A level shift circuit characterized by that. The level shift circuit according to claim 8, wherein
The two N-type transistors for protection of the protection circuit are supplied with the voltage of the low voltage source at their gates.
A level shift circuit characterized by that. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
Two protective N-type transistors having one end connected to the first and second nodes and the other end connected to the third and fourth nodes, respectively.
The complementary first and second input signals are respectively input to the gates of the two N-type transistors for protection of the protection circuit via a delay circuit.
A level shift circuit characterized by that. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
Two protective N-type transistors having one end connected to the first and second nodes and the other end connected to the third and fourth nodes, respectively.
The complementary first and second input signals are directly input to the gates of the protective N-type transistors of the protection circuit, respectively.
A level shift circuit characterized by that. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source And two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The protection circuit is
Two protective diodes each having a cathode connected to the first and second nodes and an anode connected to the third and fourth nodes, respectively.
A level shift circuit characterized by that. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
Each of the two high-voltage side N-type transistors has a gate receiving a stop mode signal that becomes a low potential level when the level shift circuit is stopped. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The level shift circuit, wherein the two high-voltage side N-type transistors have the complementary first and second input signals inputted to their gates through a delay circuit, respectively. Complementary first and second input signals, each having a low voltage source as a power source, are input to the gate, one end is grounded, and the other end is connected to the first and second nodes, respectively. A low-voltage side N-type transistor of
The complementary first and second input signals having one end connected to the third and fourth nodes, the other end connected to the fifth and sixth nodes, respectively, and the gate as the power source of the low voltage source Two high-voltage side N-type transistors that are turned on when the first and second input signals are at a high potential level,
One end is connected to the high voltage source, the other end is connected to the fifth and sixth nodes, respectively, and the voltage of the high voltage source is supplied to one of the fifth and sixth nodes, while the other is A power supply circuit for cutting off the supply of the high voltage source;
It is arranged between the first node and the third node and between the second node and the fourth node, and the voltage of the first and second nodes is made lower than the voltage of the low voltage source. With a protective circuit to limit,
The level shift circuit, wherein the two high-voltage side N-type transistors have the complementary first and second input signals directly input to their gates, respectively. In the level shift circuit according to any one of claims 1 to 15 ,
First and second clamping circuits are disposed between the third and fourth nodes and the low voltage source, respectively, and clamp the third and fourth nodes to the voltage of the low voltage source. A level shift circuit characterized by that. In the level shift circuit according to any one of claims 1 to 16 ,
The level shift circuit characterized in that the threshold voltage of each of the two high-voltage side N-type transistors is set lower than the threshold voltage of the two low-voltage side N-type transistors for signal input.

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