JP2017147561A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control an impedance of output terminals to a value sufficient to practical use, and thereby, to enable a load connected with the output terminals to be effectively operated.SOLUTION: Transistors MP1, MP3, MN3, and MN1 are cascade-connected between a power supply VDD and the GND, and transistors MP2, MP4, MN4, and MN2 are cascade-connected between the power supply VDD and the GND. Gates of the transistors MN1 and MN2 are connected with differential input terminals IN1 and IN2. Drains of the transistors MN1 and MN2 are connected with output terminals OUT5 and OUT6 of a differential third set. Further, the transistors MP5 and MP6 are connected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a level shift circuit that converts an input voltage level to a voltage of another level and outputs the converted voltage.

  In recent years, miniaturization of MOS transistors has progressed, and the withstand voltage has also been lowered. The breakdown voltage of the MOS transistor includes the maximum voltage at which the gate oxide film does not break down, the maximum voltage at which no avalanche breakdown occurs when a reverse bias is applied to the PN junction, and the maximum drain voltage that can maintain device reliability. It is determined from the source voltage VDS.

  This withstand voltage has two values: the maximum voltage that can be applied instantaneously and the voltage that degrades the characteristics when applied over a long period of time. To do. The drain-source voltage VDS applied to the MOS transistor must basically be less than or equal to this operating rating. However, due to various problems, the power supply voltage cannot be reduced as the element is miniaturized, and the electric field applied to the element is only increasing.

  As a result of only the miniaturization of the element as described above, a case where a voltage output exceeding the operation rating of the element is required was created, and in order to solve this, for example, a level shift circuit shown in FIG. (See Patent Document 1).

  In FIG. 4, MP1, MP2, MP3, and MP4 are Pch type MOS transistors, and MN1, MN2, MN3, and MN4 are Nch type MOS transistors. The transistors MP1, MP3, MN3, and MN1 are cascaded between the first power supply VDD and the second power supply GND, and the transistors MP2, MP4, MN4, and MN2 are also cascaded between the first power supply VDD and the second power supply GND. Yes. The transistors MP1 and MP2 form a latch circuit by cross-connecting the gate and drain thereof, and the gates of the transistors MP3, MP4, MN3, and MN4 are commonly connected to the third power supply VB.

  The differential input terminals IN1 and IN2 are connected to the gates of the transistors MN1 and MN2, respectively. The first differential output terminals OUT1 and OUT2 are connected to the common drains of the transistors MP3 and MN3 and the common drains of the transistors MP4 and MP4, respectively. The differential second output terminals OUT3 and OUT4 are connected to the drains of the transistors MP1 and MP2, respectively. The differential third output terminals OUT5 and OUT6 are connected to the drains of the transistors MN1 and MN2, respectively.

  In the level shift circuit of FIG. 4, the first power supply VDD = 6V, the second power supply GND = 0V, and the third power supply VB = 3V are set, and the rated operating voltage of each transistor is 3V, that is, the drain-source voltage VDS. Is 3V and its threshold voltage is 0.5V.

  When a voltage of “H” (high level, same below) = 3V is input to the input terminal IN1, and “L” (low level, same below) = 0V is input to IN2, the transistor MN1 is turned on and the transistor MN2 is turned off. For this reason, the transistors MN3, MP4, and MP1 are turned on, and the transistors MN4, MP3, and MP2 are turned off. Therefore, the output terminals are OUT1 = GND, OUT2 = VDD, OUT3 = VB, OUT4 = VDD, OUT5 = GND, and OUT6 = VB.

  On the other hand, when a voltage of “L” is input to the input terminal IN1 and “H” is input to the input terminal IN2, the transistor MN1 is turned off and the transistor MN2 is turned on. For this reason, the transistors MN3, MP4, and MP1 are turned off, and the transistors MN4, MP2, and MP3 are turned on. Therefore, the output terminals are OUT1 = VDD, OUT2 = GND, OUT3 = VDD, OUT4 = VB, OUT5 = VB, and OUT6 = GND. The voltage waveform of each of the above output terminals is shown in FIG.

JP 11-205123 A

  By the way, in the level shift circuit of FIG. 4, when the input terminals IN1 = “L” and IN2 = “H” and the transistors MN1 and MN3 are turned off, the third power supply VB is almost the operation rating of each MOS transistor. When the voltage is set, the drain-source voltage VDS of the transistors MN1 and MN3 is not always within the operation rating.

  For this reason, at the moment when the transistors MN1 and MN3 are turned off, the voltage of the output terminal OUT5 is biased toward either the GND side or the VB side, and the output terminal OUT5 has a high impedance. A transition time occurs until the voltage falls within the operating rating of each MOS transistor. At this time, if a transition time exceeding the operating rating is required, the reliability of the MOS transistor is adversely affected.

  At this time, the output terminal OUT5 can be regarded as an output terminal having the potential of the voltage VB. However, when the input terminals IN1 = "L" and IN2 = "H", the transistors MN1 and MN3 are both turned off. OUT5 has an extremely high output impedance. For this reason, the output current of the output terminal OUT5 is only the leakage current of the transistors MN1 and MN3. Therefore, if the load of this output terminal OUT5 is a capacity | capacitance, for example, it will take much time for the charge. This problem also occurs on the output terminal OUT6 side when the transistors MN2 and MN4 are turned off.

  In order to solve this, it is necessary to separately provide a buffer circuit at the output terminal OUT5. This problem also occurs on the output terminal OUT6 side when the transistors MN2 and MN4 are turned OFF when the input terminal IN1 = "H" and IN2 = "L".

  An object of the present invention is to make it possible to control the impedance of an output terminal to a value that is practical enough so that a load connected to the output terminal can be operated effectively.

  To achieve the above object, a level shift circuit according to a first aspect of the present invention includes a first conductivity type first transistor having a source connected to a first power supply, and a drain of the first conductivity type first transistor. A first conductivity type third transistor having a source connected to the first conductivity type, a second conductivity type third transistor having a drain connected to the drain of the first conductivity type third transistor, and the second conductivity type second transistor. A first cascade connection circuit is constituted by a first transistor of a second conductivity type having a drain connected to a source of three transistors and a source connected to a second power source, and a source is connected to the first power source. A second transistor of the first conductivity type, a fourth transistor of the first conductivity type whose source is connected to the drain of the second transistor of the first conductivity type, and a drain of the fourth transistor of the first conductivity type. And a second conductivity type fourth transistor having a drain connected to a source of the second conductivity type fourth transistor and a source connected to the second power source. A cascade connection circuit is formed, and the gate of the first conductivity type first transistor and the drain of the first conductivity type second transistor are connected in common, and the gate of the first conductivity type second transistor, The drains of the first conductivity type first transistors are connected in common, the first conductivity type third transistor, the first conductivity type fourth transistor, the second conductivity type third transistor, and the second Each gate of the fourth conductive type transistor is connected to a third power source, and the second conductive type first transistor gate and the second conductive type second transistor gate are connected. Is connected to the differential input terminal, and the drain of the second conductive type first transistor and the drain of the second conductive type second transistor are connected to the differential third output terminal, In the level shift circuit in which the voltage of the power supply is set to a voltage between the voltage of the first power supply and the voltage of the second power supply, the source is connected to the drain of the first transistor of the second conductivity type, and the gate is The first conductivity type fifth transistor connected to the gate of the second conductivity type first transistor, the drain connected to the third power source, and the source connected to the drain of the second conductivity type second transistor. And a first conductivity type sixth transistor having a gate connected to the gate of the second conductivity type second transistor and a drain connected to the third power source.

  According to a second aspect of the present invention, in the level shift circuit according to the first aspect, the potential difference between the voltage of the first power source and the voltage of the third power source, and the voltage of the third power source and the voltage of the second power source The first, second, third, fourth, fifth, and sixth transistors of the first conductivity type and the first, second, third, and fourth transistors of the second conductivity type It is set within the rated operating voltage.

  According to the level shift circuit of the first and second aspects of the present invention, the differential third output terminal is controlled to an impedance sufficient for practical use by connecting the first and fifth conductive type fifth and sixth transistors. The load connected to the output terminals can be operated effectively.

1 is a circuit diagram showing a level shift circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the level shift circuit of 2nd Example of this invention. It is a circuit diagram which shows the level shift circuit of 3rd Example of this invention. It is a circuit diagram which shows the level shift circuit of the example of a prior art circuit. It is a voltage waveform diagram of each output terminal of the level shift circuit of the conventional circuit example. FIG. 5 is a waveform diagram of a drain-source voltage VDS of a transistor MP3, where FIG. 1A shows the conventional level shift circuit of FIG. 4 to which the transistor MP7 is not connected, and FIG. This is the case of the level shift circuit of the first embodiment.

<First embodiment>
FIG. 1 shows a level shift circuit according to a first embodiment of the present invention. In FIG. 1, MP1, MP2, MP3, and MP4 are Pch type MOS transistors, and MN1, MN2, MN3, and MN4 are Nch type MOS transistors. The transistors MP1, MP3, MN3, and MN1 are connected in cascade between the first power supply VDD and the second power supply GND, and the transistors MP2, MP4, MN4, and MN2 are also connected in cascade between the first power supply VDD and the second power supply GND. Has been. The transistors MP1 and MP2 form a latch circuit by cross-connecting the gate and the drain, and the gates of the transistors MP3, MP4, MN3, and MN4 are connected to the third power supply VB. The above is the same as the level shift circuit described in FIG.

  In the level shift circuit of this embodiment, PMOS transistors MP5, MP6, MP7, and MP8 are further connected. The transistor MP5 has a gate connected to the gate of the transistor MN1, a source connected to the third power supply VB, and a drain connected to the drain of the transistor MN1. The MOS transistor MP6 has a gate connected to the gate of the transistor MN2, a source connected to the third power supply VB, and a drain connected to the drain of the transistor MN2. The transistor MP7 has a gate connected to the drain of the transistor MP3, a drain connected to the third power supply VB, and a source connected to the source of the transistor MP3. The transistor MP8 has a gate connected to the drain of the transistor MP4, a drain connected to the third power supply VB, and a source connected to the source of the transistor MP4.

  The differential input terminals IN1 and IN2 are connected to the gates of the transistors MN1 and MN2, respectively. The first differential output terminals OUT1 and OUT2 are connected to the common drains of the transistors MP3 and MN3 and the common drains of the transistors MP4 and MP4, respectively. The differential second output terminals OUT3 and OUT4 are connected to the drains of the transistors MP1 and MP2, respectively. The differential third output terminals OUT5 and OUT6 are connected to the drains of the transistors MN1 and MN2, respectively.

  Here, for convenience, the highest voltage that does not cause deterioration of the characteristics of the transistor even when applied to the drain-source voltage VDS of each MOS transistor for a certain period is defined as the operating rated voltage of the element. When the rated operating voltage is 3V, the voltage of the third power supply VB is also 3V. At this time, differential voltages of “L” = 0 V and “H” = 3 V are input to the input terminals IN1 and IN2. In addition, the voltage value of the first power supply VDD is 6V, which is twice the voltage value of the third power supply VB. The threshold voltage of each MOS transistor is 0.5V.

  Now, an operation when “H” and “L” signals are respectively input to the input terminals IN1 and IN2 in the steady state will be described.

  At this time, since the transistor MN1 is ON, the transistor MP5 is OFF and the transistor MN3 is ON. When the transistors MN1 and MN3 are turned on, the output terminal OUT1 becomes 0V and the transistor MP7 is turned on. Since the transistor MP7 is turned on, the output terminal OUT3 becomes 3V. Therefore, the transistor MP3 is turned off and the transistor MP2 is turned on.

  On the other hand, since the input terminal IN2 is “L”, the transistor MN2 is turned off and the transistor MP6 is turned on. Since the transistor MP6 is turned ON, the output terminal OUT6 becomes 3V, and the transistor MN4 is turned OFF. Since the transistors MN2 and MN4 are OFF and the transistor MP2 is ON, the output terminal OUT4 is 6V and the transistor MP4 is ON. Since the output terminal OUT4 is 6V, the transistor MP1 is turned off. Since the transistors MP2 and MP4 are turned on and the transistors MN2 and MN4 are turned off, the transistor MP8 is turned off.

  That is, when a signal of “H” is input to the input terminal IN1, and “L” is input to IN2, the output terminals are OUT1 = 0V, OUT2 = 6V, OUT3 = 3V, OUT4 = 6V, OUT5 = 0V, OUT6. = 3V voltage.

  At this time, the output impedance of the output terminal OUT3 having a voltage of 3V is determined by the ON resistance of the transistor MP7, and the output impedance of the output terminal OUT6 having a voltage of 3V is determined by the ON resistance of the transistor MP6. That is, the output terminals OUT3 and OUT6 do not become high impedance.

  Next, a transient state after the moment when the input terminal IN1 is switched from “L” to “H” will be described. When the input terminal IN1 is switched to “H”, the transistor MN1 is turned on and the transistor MP5 is turned off. Then, the output terminal OUT5 becomes 0V, and the transistor MN3 is turned on.

  At this moment, when considering the cascade-connected transistors on the transistor MN1 side, the transistors MN1, MN3, MP3, MP1, and MP7 are turned on and MP6 is turned off. Therefore, the transistors MN1, MN3, MP3, MP1, and MP7 are turned on so that the voltage of the output terminal OUT3 at this moment is 5.5V or less (the voltage applied between the gate and the source of the transistor MP2 is 0.5V). Set the resistance. As a result, the transistor MP2 is turned on.

  Further, since the input terminal IN2 is switched from “H” to “L”, the transistor MN2 is turned off and the transistor MP6 is turned on. Since the transistor MP4 was turned off before “L” was inputted to the input terminal IN1 and “H” was inputted to the input terminal IN2, the transistor MN2 is turned off and the transistor MP6 is turned on, so that the output terminal OUT6 is turned on. The voltage becomes 3V, and the transistor MN4 is turned OFF.

  At the moment when the transistor MP2 is turned ON, the voltage at the output terminal OUT4 rises from 3V because the voltage between VDD and VB is divided by the ON resistances of the transistors MP2 and MP8. When the output terminal OUT4 becomes 3.5V or higher, the transistor MP4 is turned on. At this time, the series impedance of the load impedance of the output terminal OUT2 and the ON resistance of the transistor MP4 is added to the load of the output terminal OUT4.

  If the ON resistance of the transistor MP4 is set to be sufficiently smaller than the load impedance of the output terminal OUT2, the output terminal OUT2 and the output terminal OUT4 have substantially the same potential, so that the transistor MP8 is turned off. Since the transistors MP2 and MP4 are turned on and the transistors MN2, MN4 and MP8 are turned off, the output terminal OUT4 and the output terminal OUT2 become 6V, and the transistor MP1 is turned off.

  In the transient state from the moment when the input terminal IN1 switches from “L” to “H” to the steady state, the transition time of the potential of the output terminal OUT3 is determined by the ON resistance of the transistor MP7 and the load capacitance of the output terminal OUT3. Further, the transition time of the potential of the output terminal OUT6 is determined by the ON resistance of the transistor MP6 and the load capacitance of the output terminal OUT6.

  In the transition time, for example, since the output terminal OUT3 was 6V in the previous state, the output terminal OUT1 transits from 6V to 3V, and the output terminal OUT1 transits from 6V to 0V.

  Here, if the transistor MP7 is not provided, the transition time of the output terminal OUT3 is driven only by the leakage currents of the transistors MP1 and MP3, and therefore becomes longer than the transition time of the output terminal OUT1. That is, there is a time during which the output terminal OUT3 exceeds 3V although the output terminal OUT1 changes to 0V. During this time, a voltage exceeding the rated operating voltage of 3 V is applied to the transistor MP3 between the drain and source. The longer the time during which the drain-source voltage VDS of the MOS transistor exceeds the rated operating voltage, the worse the reliability of the MOS transistor.

  However, in this embodiment, the transition time of the potential of the output terminal OUT3 is greatly reduced by the ON resistance of the transistor MP7, thereby improving the reliability of the level shift circuit.

  FIG. 5 shows a simulation waveform of the drain-source voltage VDS of the transistor MP3. In this simulation, unlike the above description, the operation rating of the transistor MP3 is 2.5V. In the conventional circuit (a) without the transistor MP7, the peak value is large when the voltage changes, and it takes time to settle down to 2.5V. On the other hand, in the circuit of this embodiment shown in (b) when the transistor MP7 is connected, it can be seen that the peak value at the time of voltage change is small and the time until it settles to 2.5V is extremely short.

  Next, consider the power supply voltage at which the level shift circuit of this embodiment can operate. In order to switch the logic of each output terminal voltage at the moment when the input terminal IN1 switches from “L” to “H”, the transistor MP2 needs to be turned on. In order to turn on the transistor MP2, the potential difference between the first power supply VDD and the output terminal OUT3 must be 0.5 V or more. That is, when VB = 3V, VDD needs to be 3.5V or more.

  Here, when the transistor MP7 is not provided, the transistors MP2 and MP3 need to be turned on in order to switch the logic of each output terminal voltage at the moment when the input terminal IN1 is switched from “L” to “H”. If the transistor MP3 cannot be turned on, the potential of the output terminal OUT3 does not drop even if the transistors MN1 and MN3 are turned on, and the transistor MP2 cannot be turned on. Even if the transistor MP3 is turned on, the transistor MP2 cannot be turned on unless the potential difference between the first power supply VDD and the output terminal OUT3 is larger than the threshold voltage of the transistor MP2.

  In order to turn on the transistor MP3, the voltage of the output terminal OUT3 needs to be 3.5V or more when VB = 3V. To turn on the transistor MP2, the voltage between the first power supply VDD and the voltage of the output terminal OUT3 is required. Since the difference needs to be 0.5 or more, the condition of the voltage VDD that satisfies these conditions is that VDD is 4 V or more.

  That is, by connecting the transistor MP7 as in the present embodiment, the voltage required for the voltage VDD is reduced by the threshold voltage of the transistor MP3 as compared to the case where the transistor MP7 is not provided.

  This means that, for example, when the voltage VDD is output from the output terminals OUT2 and OUT4 of the level shift circuit, the range in which the voltage drop that occurs when the load is heavy is allowed to be widened. By expanding the allowable range, the voltage VDD can operate the level shift circuit normally with less current output capability than the conventional circuit.

  For example, a booster circuit is generally used to generate the voltage VDD, but the current output capability of the booster circuit is in a trade-off relationship with its cost, and a booster circuit having a higher current output capability is designed. The difficulty level also increases. Therefore, the expansion of the allowable range in the level shift circuit of the present embodiment contributes to a reduction in design man-hours due to a cost reduction of the booster circuit and a decrease in design difficulty.

<Second embodiment>
FIG. 2 shows a level shift circuit according to a second embodiment of the present invention. In FIG. 2, MP11, MP12, MP13, and MP14 are Pch type MOS transistors, and MN11, MN12, MN13, and MN14 are Nch type MOS transistors. The transistors MP11, MP13, MN13, and MN11 are cascaded between the first power supply VDD and the second power supply VSS, and the transistors MP12, MP14, MN14, and MN12 are also cascaded between the first power supply VDD and the second power supply VSS. Yes. The transistors MN11 and MN12 form a latch circuit by cross-connecting the gate and drain thereof, and the gates of the transistors MP13, MP14, MN13, and MN14 are connected to the third power supply VB.

  In the level shift circuit of this embodiment, PMOS transistors MN15, MN16, MN17, and MN18 are further connected. The transistor MN15 has a gate connected to the gate of the transistor MP11, a source connected to the third power supply GND, and a drain connected to the drain of the transistor MP11. The transistor MN16 has a gate connected to the gate of the transistor MP12, a source connected to the third power supply GND, and a drain connected to the drain of the transistor MP12. The transistor MN17 has a gate connected to the drain of the transistor MN13, a drain connected to the third power supply GND, and a source connected to the source of the transistor MN13. The transistor MN18 has a gate connected to the drain of the transistor MN14, a drain connected to the third power supply GND, and a source connected to the source of the transistor MN14.

  The differential input terminals IN11 and IN12 are connected to the gates of the transistors MP11 and MP12, respectively. The first differential output terminals OUT11 and OUT12 are connected to the common drains of the transistors MP13 and MN13 and the common drains of the transistors MP14 and MN14, respectively. The differential second output terminals OUT13 and OUT14 are connected to the drains of the transistors MN11 and MN12, respectively. The third differential output terminals OUT15 and OUT16 are connected to the drains of the transistors MP11 and MP12, respectively.

  Also in this embodiment, the highest voltage that does not cause deterioration of the characteristics of the transistor even if it is applied to the drain-source voltage VDS of each MOS transistor for a certain period is used as the rated operating voltage of the element for convenience. If the rated operating voltage is 3V, the first power supply VDD is also 3V. At this time, voltages of “L” = 0V and “H” = 3V are input to the input terminals IN11 and IN12. Further, the second power supply VSS is set to a voltage that is -1 times the first power supply VDD, and is set to -3V. The threshold voltage of each MOS transistor is 0.5V.

  Now, the operation when the “H” signal is input to the input terminal IN11 and the “L” signal is input to the IN12 in the steady state will be described.

  At this time, since the input terminal IN11 is “H”, the transistor MP11 is turned off, the transistor MN15 is turned on, and the output terminal OUT15 becomes 0V. Then, the transistor MP13 is turned off.

  On the other hand, since the input terminal IN12 is “L”, the transistor MP12 is turned on and the transistor MN16 is turned off. Since the output terminal OUT16 becomes 3V when the transistor MP12 is turned on, the transistor MP14 is turned on. When the transistors MP12 and MP14 are turned on, the output terminal OUT12 becomes 3V, and the transistor MN18 is turned on.

  When the transistor MN18 is turned on, the output terminal OUT14 becomes 0V, and the transistor MN14 is turned off. When the output terminal OUT14 becomes 0V, the transistor MN11 is turned on. When the transistors MP11 and MP13 are turned off and the transistor MN11 is turned on, the output terminal OUT13 becomes -3V and the transistor MN13 is turned on. When the transistor MN13 is turned on, the output terminal OUT11 becomes -3V, and the transistor MN17 is turned off.

  That is, when a signal of “H” is input to the input terminal IN11 and “L” is input to the IN12, the output terminals are OUT11 = −3V, OUT12 = 3V, OUT15 = 0V, OUT16 = 3V, OUT13 = −3V. , OUT14 = 0V.

  At this time, the output impedance of the output terminal OUT15 whose voltage is 0V is determined by the ON resistance of the transistor MN15, and the output impedance of the output terminal OUT14 whose voltage is 0V is determined by the ON resistance of the transistor MN18. That is, the output terminals OUT15 and OUT14 do not become high impedance.

  Next, a transient state after the moment when the input terminal IN11 is switched from “L” to “H” will be described. When the input terminal IN11 is switched to “H”, the input terminal IN12 is switched from “H” to “L”, the transistor MP12 is turned on, and the transistor MN16 is turned off. Since the transistor MP12 is turned on, the output terminal OUT16 becomes 3V, and the transistor MP14 is turned on.

  At this moment, when considering the cascade-connected MOS transistors on the transistor MP12 side, the transistors MP12, MP14, MN14, MN1, and MN18 are ON, and the transistor MN16 is OFF. If the ON resistance of each MOS transistor is set so that the voltage of the output terminal OUT14 at this moment becomes −2.5 V or more, the transistor MN11 is turned on.

  Further, since the input terminal IN11 is switched from “L” to “H”, the transistor MP11 is turned off and the transistor MN15 is turned on. Since the transistor MN13 was turned off before “L” was input to the input terminal IN11 and “H” was input to the IN12, the transistor MP11 was turned off and the transistor MN15 was turned on, so that the output terminal OUT15 was set to 0V. Thus, the transistor MP13 is turned OFF.

  At the moment when the transistor MN11 is turned on, the voltage at the output terminal OUT13 falls from 0V because the voltage between GND and VSS is divided by the ON resistance of the transistors MN11 and MN17. When the voltage at the output terminal OUT13 falls below -0.5V, the transistor MN13 is turned on. At this time, the series impedance of the load impedance of the output terminal OUT11 and the ON resistance of the transistor MN13 is added to the load of the output terminal OUT13.

  If the ON resistance of the transistor MN13 is set to be sufficiently smaller than the load impedance of the output terminal OUT11, the output terminals OUT11 and OUT13 have substantially the same potential, so that the transistor MN17 is turned OFF. Since the transistors MN11 and MN13 are turned on and the transistors MP11, MP13, and MN17 are turned off, the output terminals OUT13 and OUT11 become −3 V, and the transistor MN12 is turned off.

  In the transition time from the moment when the input terminal IN12 switches from “H” to “L” to the steady state, the transition time of the potential of the output terminal OUT15 is determined by the ON resistance of the transistor MN15 and the load capacitance of the output terminal OUT15. The transition time of the potential of the output terminal OUT14 is determined by the ON resistance of the transistor MN18 and the load capacitance of the output terminal OUT14.

  In the transition time, for example, since the output terminal OUT15 was 3V in the previous state, the output terminal OUT11 transits from 3V to 0V.

  Here, if the transistor MN15 is not provided, the transition time of the output terminal OUT15 is driven only by the leakage currents of the transistors MP11 and MP13, and therefore becomes longer than the transition time of the output terminal OUT11. That is, there is a time during which the output terminal OUT15 exceeds 0V even though the output terminal OUT11 has changed to -3V. During this time, a voltage exceeding the rated operating voltage of 3 V is applied across the drain and source of the transistor MP13. The longer the time during which the VDS of the MOS transistor exceeds the operating rated voltage, the longer the reliability of the MOS transistor.

  However, in this embodiment, the transition time of the potential of the output terminal OUT15 is greatly reduced by the ON resistance of the transistor MN15. As a result, the reliability of the level shift circuit is improved.

  Next, consider the power supply voltage at which the level shift circuit of this embodiment can operate. In order to switch the logic of each output terminal voltage at the moment when the input terminal IN12 switches from “H” to “L”, the transistor MN11 needs to be turned on. In order to turn on the transistor MN11, the potential difference between the output terminal OUT14 and the second power supply VSS must be 0.5 V or more. That is, when GND = 0V, VSS needs to be −0.5V or less.

  Here, when the transistor MN18 is not provided, the transistors MN11 and MN14 need to be turned on in order to switch the logic of each output terminal voltage at the moment when the input terminal IN12 is switched from “H” to “L”. If the transistor MN14 cannot be turned on, the potential of the output terminal OUT14 does not rise even if the transistors MP12 and MP14 are turned on, and the transistor MN11 cannot be turned on. Even if the transistor MN14 is turned on, the transistor MN11 cannot be turned on unless the potential difference between the output terminal OUT14 and the second power supply VSS is larger than the threshold voltage of the transistor MN11.

  In order to turn on the transistor MN14, when GND = 0V, the voltage of the output terminal OUT14 needs to be −0.5V or less. To turn on the transistor MN11, the voltage of the output terminal OUT14 is from the second power supply VSS. Therefore, the condition of the second power supply VSS that satisfies these conditions is −4 V or less.

  That is, by connecting the transistor MN18 as in the present embodiment, the voltage required for the second power supply VSS is reduced by the threshold voltage of the transistor MN14.

  This means that, for example, when the voltage of the second power supply VSS is output from the output terminals OUT12 and OUT14 of the level shift circuit, the range in which the voltage drop that occurs when the load is heavy can be increased. By expanding the allowable range, the second power supply VSS can operate the level shift circuit normally with a smaller current output capability than the conventional circuit.

  For example, a negative voltage generation circuit such as a charge pump circuit is generally used to generate the second power supply VSS, but the current output capability of the negative voltage generation circuit is in a trade-off relationship with its cost and is higher. A negative voltage generation circuit having a current output capability is also more difficult to design. Therefore, the expansion of the allowable range in the level shift circuit of the present embodiment contributes to a reduction in design man-hours due to a cost reduction of the booster circuit and a decrease in design difficulty.

<Third embodiment>
FIG. 3 shows a third embodiment of the present invention in which the power supplies VDD, GND, and VSS in the second embodiment are replaced with GND, VB, and VSS, respectively. The third power supply VB is a power supply to which a voltage between the first power supply GND and the second power supply VSS is applied. Here, for example, GND = 0V, VB = -3V, and VSS = -6V. The operation is the same as in the second embodiment.

MN1 to MN4, MN11 to MN18: Nch type MOS transistors MP1 to MP8, MP11 to MP14: Pch type MOS transistors VDD: first power source GND: second power source in FIGS. 1 and 4, third power source in FIG. Then, the first power supply VSS: the second power supply VB: the third power supply OUT1-OUT6, OUT11-OUT16: output terminals IN1, IN2, IN11, IN12: input terminals

Claims (2)

A first conductivity type first transistor having a source connected to a first power source; a first conductivity type third transistor having a source connected to a drain of the first conductivity type first transistor; and the first conductivity type. A third transistor of the second conductivity type having a drain connected to the drain of the third transistor of the type, and a second transistor having a drain connected to the source of the second transistor of the second conductivity type and a source connected to the second power source. A first cascade circuit is constituted by the first transistor of the conductive type,
A first conductivity type second transistor having a source connected to the first power supply; a first conductivity type fourth transistor having a source connected to a drain of the first conductivity type second transistor; A second conductivity type fourth transistor having a drain connected to a drain of the conductivity type fourth transistor; a drain connected to a source of the second conductivity type fourth transistor; and a source connected to the second power source. A second cascade connection circuit is configured by the second transistor of the second conductivity type,
The gate of the first conductivity type first transistor and the drain of the first conductivity type second transistor are connected in common, and the gate of the first conductivity type second transistor and the first conductivity type first transistor. The transistor drains are connected in common,
Each gate of the first conductivity type third transistor, the first conductivity type fourth transistor, the second conductivity type third transistor, and the second conductivity type fourth transistor is connected to a third power source. And
A gate of the first transistor of the second conductivity type and a gate of the second transistor of the second conductivity type are connected to a differential input terminal;
A drain of the second conductivity type first transistor and a drain of the second conductivity type second transistor are connected to a differential third output terminal;
In the level shift circuit in which the voltage of the third power supply is set to a voltage between the voltage of the first power supply and the voltage of the second power supply,
A first conductivity type second transistor having a source connected to the drain of the second conductivity type first transistor, a gate connected to the gate of the second conductivity type first transistor, and a drain connected to the third power source. 5 transistors,
A first conductivity type second transistor having a source connected to the drain of the second conductivity type second transistor, a gate connected to the gate of the second conductivity type second transistor, and a drain connected to the third power source. 6 transistors,
A level shift circuit comprising: The level shift circuit according to claim 1, wherein
The potential difference between the voltage of the first power source and the voltage of the third power source, and the potential difference between the voltage of the third power source and the voltage of the second power source are first, second, third, and second of the first conductivity type. 4. A level shift circuit, wherein the level shift circuit is set within an operation rated voltage of the first, second, third, and fourth transistors of the fourth, fifth, and sixth transistors and the second conductivity type.

Images