JPH07226505A - High-withstand voltage insulated-gate type field-effect transistor and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to form a low-cost, high-performance and high- withstand voltage semiconductor integrated circuit as a high-withstand voltage MIS transistor can be formed on the same substrate along with a low-withstand voltage transistor of high-speed operation because the gate insulating film of the high-withstand voltage MIS transistor can be made thin. CONSTITUTION:A high-withstand voltage transistor 15 and a low-withstand voltage transistor 14 are formed on a P-type substrate and an N+ or - drain region 6 is formed between channel and N<+> drain regions 7 of the transistor 15 for making it possible to form the film thickness of a gate oxide film 3 of the transistor 15 in a thickness equal with that of a gate oxide film 3 of the transistor 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a MIS type semiconductor integrated circuit device, and switches high voltage of a semiconductor integrated circuit device for a power supply having a constant voltage output function or a constant current output function and a thermal head driver IC. And a configuration of a high breakdown voltage semiconductor integrated circuit device having the high breakdown voltage insulated gate field effect transistor, a high breakdown voltage semiconductor integrated circuit device having the transistor integrated on the same substrate, and a semiconductor integrated circuit device having a load driving function.

[0002]

2. Description of the Related Art Heretofore, as a MOS type semiconductor integrated circuit device in such a field, the most basic three-terminal power supply semiconductor integrated circuit device having a constant voltage output will be described here as an example. , CMOS, mainly composed of an output transistor, a reference voltage circuit, an error amplifier, and a feedback resistor, and an input terminal (Vin, a power supply input higher than the output voltage and supplied from an arbitrary or unstable voltage source) and an output. A semiconductor integrated circuit device (referred to as a three-terminal regulator, a voltage regulator, Vr, or the like) including terminals (Vout, 3V, 5V, etc.) and a GND terminal (ground) is known. Particularly important electrical characteristics are the operation rated voltage (how high the voltage of Vin is, the desired operation is performed, 7V to 12V is general, and it is convenient to be able to improve to 18V or 24V. There is a certain value) and an output current (Iout, a current value indicating to what current value a constant voltage output can be output. About 100 mA is general, and it is convenient to improve from 300 mA to about 500 mA).

FIG. 31 In a general MOS transistor, the gate insulating film thickness (gate Tox) and gm (so-called transconductance of MOS, K
Although it is sometimes referred to as a value or a drain current drivability, etc., gm is a graph showing a relationship of a value normalized by W / L of the gate) and an operating rated voltage at the same time.

The rated operating voltage of the MOS type semiconductor integrated circuit device is almost determined by the electric field applied to the gate insulating film (MO
The breakdown voltage of the S transistor includes drain withstand voltage and punch through withstand voltage, which will be described later), that is, TDDB (Time Depend).
ence Dielectric Breakdow
n, time dependency of insulation film breakdown) is about 3 MV / to secure sufficient reliability (which is said to be 10 years)
This is because the electric field strength needs to be equal to or lower than cm. Therefore, as can be seen from the figure, in the case of 7V rating, for example, 250 Å is sufficient for the gate insulating film, but in order to make the 24V rating, the gate insulating film must be 800 Å or more. Therefore, as shown in FIG.
(Field Effect Transistor) will have a high breakdown voltage structure. In FIG. 2, an N ⁺ source region 72 and a drain region 73 are provided on the surface of a substrate 71, and the N ⁺ drain region 73 is surrounded by a lightly doped N ⁻ type drain region 74. A gate electrode 76 is provided on the channel region on the surface of the substrate 71 between the source region 72 and the N ⁻ type drain region 74 via a gate oxide film 75. Electrodes 77 and 78 are provided on the source region 72 and the drain region 73. Gate oxide film 75
Has a film thickness of about 1000 Å, so that it does not break even if the drain voltage is high. Further, an N ⁻ type drain region 74 is provided to increase the surface junction breakdown voltage when the drain voltage is high. Then, as can be seen from the graph of FIG. 31, a large decrease in gm will occur.

[0005]

As described above, in the semiconductor integrated circuit device in such a field,
If you try to increase the rated voltage, the current drive capacity will decrease,
As a result, in the case of a MOS transistor, the channel width (referred to as W width) of the gate must be increased, which leads to an increase in element area (referred to as chip size).
The problem is that the cost will increase. Alternatively, the size of the chip must be increased and the PKG (an outer case in which the chip of the semiconductor integrated circuit device is housed, which is referred to as DIP or SOT molded with plastic resin or ceramic) must be accommodated. , PKG becomes large, it takes up space even when assembled on a circuit board, and reliability that hot carriers generated by high drain voltage application are trapped in the gate oxide film and the channel current changes with time. There was a sex problem.

Further, since the thick insulating film is operated in a high electric field, there is a problem that the gate insulating film is easily broken. Furthermore, in an integrated circuit provided on the same substrate as the low-voltage semiconductor device, if the gate insulating film of the low-voltage semiconductor device is also formed as the gate insulating film of the high-voltage semiconductor device, the manufacturing process becomes complicated. In addition, the driving ability of the low-voltage semiconductor device cannot be improved by the thick gate insulating film, and therefore, there is a problem that it cannot operate at high speed.

Therefore, the present invention is to improve the channel current per unit channel width and prevent the channel current from changing over time in order to solve the conventional problems as described above. further,
It is to obtain a semiconductor device with high breakdown voltage of a high quality gate insulating film. A further object of the present invention is to obtain a semiconductor integrated circuit device in which a low-voltage semiconductor device that operates at high speed and a high-voltage semiconductor device are provided on the same substrate by a simple manufacturing process.

[0008]

In order to solve the above problems, the present invention employs the following means. As a first means, a high breakdown voltage insulated gate field effect transistor (hereinafter,
It is called HVMISFET. High Voltage Metal Insulat
or Semiconductor Field Effect Transistor), the thickness of the gate insulating film is reduced from 100 Å to 200 Å and the surface concentration of the drain region overlapping with the gate electrode is easily depleted from 5 × 10 ¹⁶ atoms / cm ³ to 5 × 10 ¹⁸ atoms The density was set to between 1 / cm ³ .

As a second means, a second gate electrode for high breakdown voltage is provided on a part of the drain region and the channel region through a very thin insulating film of 50 to 200 Å, and the source region and the channel region are provided. On a part of 100-2
The structure has a gate electrode with a very thin insulating film of 00Å.

As a third means, a part of the drain region of the high breakdown voltage semiconductor device is formed of a lightly doped drain region,
By thickening only the insulating film between the gate electrode and the drain region having a low concentration, the gate insulating film of the high breakdown voltage semiconductor device has a very thin film thickness between 100Å and 200Å.

As a fourth means, the gate insulating films of the low-voltage semiconductor device and the high-voltage semiconductor device provided on the same substrate both use a thin insulating film having the same thickness between 100Å and 200Å. did. As a fifth means, the gate insulating film thickness of the output transistor is at least partially thinner than the gate insulating film thickness of other transistors (transistors forming the error amplifier or the reference voltage circuit) on the same substrate. It is to collect. For example, the gate insulating film thickness of the output transistor is Vo of Vr.
Vout of 3V, which is defined by the value of ut
If it is a product, it is divided by 3 MV / cm, and 100 Å for 5V products, 170 Å for 5V products and 500 Å for 15V products. Vin rises from 0V and reaches a predetermined Vo
This is because Vgs (the potential applied between the gate and the substrate) is almost equal to Vout when it becomes ut. On the other hand, the gate insulating film thickness of other transistors is equal to or more than the value obtained by dividing the rating by 3 MV / cm as described above, and is 800 Å or more for the 24 V rating.

As a sixth means, the gate insulating film thickness of the output transistor is further equal to or larger than the drain withstand voltage (drain withstand voltage at the gate end, which will be described later in detail) divided by 8 MV / cm. That is, if the drain breakdown voltage is 30 V, it is 370Å or more.

As a seventh means, the gate insulating film of the output transistor is composed of several kinds of materials and has a multilayer structure. Although details will be described later, for example, an ONO structure (the bottom layer is SiO ₂ and the middle is a silicon nitride film Si
_x N _y, it is the upper layer in SiN film is that take structural) a SiO ₂ again. Further, in the present ONO film, SiO ₂ on the positive electric field side is made thinner than SiO ₂ on the opposite side of ONO in a state where an electric field is applied between the gate electrode and the substrate. In other words, if the output transistor is a P-channel type MOS, it means that the SiO ₂ on the Si substrate side is thinned. The opposite is true for an N-channel type. T
This is because it is more advantageous in terms of DDB.

As an eighth means, the output transistor and the other transistors have a structure in which the gate insulating film on the drain at the gate end is partially thickened. The so-called LOCOS process (Local Oxi)
A thick oxide film for isolation between elements by the date of silicon may be used as it is, or an oxide film by another CVD or the like may be used, but for convenience sake, it is referred to as a LOCOS drain structure.

As a ninth means, immediately below the thick oxide film of the LOCOS drain structure, there is an impurity region having a lower concentration than the drain region of the same conductivity type as the drain (referred to as field-doped drain, FD drain, etc.), The FD
The drain is surrounded by a region of 1.0 μm or more from the end of the drain region of the high-concentration impurity region.
The drain has a concentration different from that of the same conductivity type of the so-called field-doped region under the thick oxide film (LOCOS oxide film) for element isolation, and the FD drain has a certain distance or more from the field-doped region of the opposite conductivity type. They are separated and adjacent to each other. Further, the impurity region having a low concentration may be formed not only immediately below the thick oxide film but also immediately below the drain region having a high concentration (referred to as a well drain). Transistors and other transistors have a low concentration region as a double structure as an impurity region of a drain. So-called DDD (double diffusion structure, Double Diffuse)
d Drain) structure. A region having a low concentration is called a thin drain.

As an eleventh means, the thin drain and the field-doped region of the opposite conductivity type are adjacent to each other with a distance of 1 μm or more.

[0017]

The high withstand voltage MISF is achieved by adopting the first to fourth means.
In ET, since the gate insulating film is formed of an insulating film thinner than 200Å, the channel current per unit channel width can be improved. Furthermore, since the insulating film on the drain region to which a high breakdown voltage is applied is also formed of an insulating film thinner than 200Å, it is difficult for hot electrons to be captured and the influence on the channel current when captured is high. Since it is also smaller, the reliability can be improved.

Further, since the gate insulating film of the low-voltage semiconductor device provided on the same substrate can also be constituted by a thin insulating film, the process is simple, and the low-voltage semiconductor device can operate at high speed. There is. By adopting the fifth means, the gm of the output transistor can be made larger than the other transistors, and therefore the W width can be significantly reduced, and the size (surface area, Vr) of the semiconductor integrated circuit device such as Vr can be reduced. The area of the output transistor, which occupies a large proportion in the chip size), can be saved, and as a result, the chip size can be saved, the manufacturing cost can be reduced, and the space can be saved.

By adopting the sixth means, the ESD tolerance (Elec) which tends to be a problem in the MOS type semiconductor integrated circuit device.
It is possible to sufficiently secure the tro Static Destroy (electrostatic breakdown voltage). In other words, considering the above-mentioned Vr semiconductor integrated circuit device having an operating rating of 24V, since the rating is 24V, the breakdown voltage of the output transistor and the transistors forming all other circuit elements must be about 26V with a margin. (This may be referred to as an absolute maximum rating.) Then, the withstand voltage of the ESD protection diode, D1 to D3 in FIG. 17, must be higher than that, and thus about 28V is required.
Then, both the output transistor and the other transistors need a drain breakdown voltage of about 30V.
This 30V is 8 because it is the most destroyed by D destruction.
The thickness is divided by MV / cm to obtain a film thickness of 370Å or more. By doing so, the drain breakdown voltage is provided before the gate insulating film, and the protection diode is broken down before the drain breakdown voltage to protect the semiconductor integrated circuit device from the ESD stress.

[0020] By taking the seventh means, the SiN film dielectric constant per unit film thickness of approximately twice the SiO _2, if the total film thickness of the same, more of the ONO structure is SiO ₂
A gm larger than that of one transistor can be obtained, and the area of the output transistor can be further reduced. By the way, S
The maximum durable electric field of the iN film is considered to be the same as that of the SiO ₂ film, but the mechanism of the leak current (breakdown voltage) flow is greatly different, that is, the SiO ₂ has a FN current (Fowle).
r-Nordheim) while SiN is Po
It shows ol-Frenkel type conductivity, which means that once a current path occurs in some beat, that part becomes a conductive path hereafter. Therefore, when SiN is used, the advantage can be exhibited only by sandwiching with SiO ₂ .

By adopting the eighth means, a desired transistor breakdown voltage for achieving a desired rating can be realized. There are three major factors that determine the breakdown withstand voltage of a MOS transistor. The first is the punch-through withstand voltage. This does not need to be considered now because the gate length (referred to as L length, gate length, etc.) need only be sufficiently long. The second is the so-called drain breakdown voltage at the gate end. Considering the off state of the transistor, the depletion layer extended to the substrate side by the electric field applied to the drain has its gate turned off, so that it acts on the accumulation side with respect to the substrate and limits the extension of the depletion layer. Therefore, the breakdown here is the earliest. The third is a junction on the opposite side of the drain region from the gate side. It is a junction with a field dope. Here, the concentration of the field dope mainly determines the junction breakdown voltage. Now, regarding the drain breakdown voltage, by increasing the thickness of the insulating film in that portion, the degree to which the gate acts on the substrate in accumulating is reduced and the desired drain breakdown voltage can be realized.

By adopting the ninth means, it is necessary to consider the breakdown of the junction between the drain and the field dope as described above. However, if the concentration of the field dope is lowered too much, a sufficient isolation breakdown voltage between elements can be obtained. Therefore, it is possible to achieve both the junction breakdown voltage and the element isolation breakdown voltage by separating them by a certain distance in this way. Further, since no heat treatment is added in the LOCOS drain structure, the threshold (VTH)
The impurity profile of the channel region introduced for control does not easily collapse, and a good low VTH transistor can be realized. Furthermore, LOCO
By forming the FD drain in the S drain structure separately from the field dope for isolation, it is possible to prevent the series resistance of the drain from increasing.

By adopting the tenth means, the thin drain can improve the depletion layer on the drain side this time as well, and the desired drain breakdown voltage can be realized. It is possible to further reduce the area without increasing the L length. By adopting the eleventh means, it is necessary to consider the breakdown of the junction between the drain and the field dope in the DDD structure as well, but if the concentration of the field dope is reduced too much, a sufficient isolation breakdown voltage (field isolation) is obtained. VTH) of
Therefore, it is possible to achieve both the junction breakdown voltage and the element isolation breakdown voltage by separating them by a certain distance or more.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a low breakdown voltage transistor 1 of the first embodiment.
4 is a cross-sectional view of an integrated circuit in which 4 and a high breakdown voltage transistor 15 are provided on the surface of the same substrate 1. FIG. Transistors 14 and 15
Are both insulated gate field effect transistors, and FIG. 1 shows an example of a low breakdown voltage and high breakdown voltage MOS transistor provided on the surface of a P-type silicon substrate. Low breakdown voltage operates at a voltage lower than that including the power supply voltage,
Is to be applied. Specifically, it means to operate by the voltage of a normal 5V power source, a 3V power source, or a 1.5V power source. The high breakdown voltage refers to a state in which a voltage higher than the power supply voltage is applied, and specifically, if the power supply voltage is 5 V, this voltage is double this voltage.
It refers to the operation in the voltage range of V or higher. The low withstand voltage MOS transistor 14 is approximately 150 Å on the surface of the P-type silicon substrate 1.
The gate electrode 12 made of a polycrystalline silicon film is formed through the gate insulating film 3 made of a silicon oxide film (SiO ₂ film) of the above, and the N ⁺ type source regions 8 and N ⁺ are self-aligned with the gate electrode 12. Type drain region 11, N ⁻ type source region 9
And N ⁻ -type drain region 10 is provided on the surface of the substrate 1. Since the low-voltage MOS transistor is often used for signal processing logic, it needs to operate at high speed.

Therefore, it is desirable that electrons, which are carriers, move from the source region 8 to the drain region 11 in a short time. Therefore, in general, the length of the channel region, which is the semiconductor substrate surface between the source region and the drain region,
That is, the channel length is shortened.

The N ⁻ type source region 9 and drain region 10 provided in FIG. 1 are provided to prevent deterioration of the transistor due to hot carriers generated when the channel length is shortened. Therefore, the channel length is 2μ
When the power supply voltage is as long as 3 m or less and when the power supply voltage is as low as 3 V or less, the N ⁻ type source region 9 and the drain region 10 are not necessary because deterioration due to hot electrons is small. The gate insulating film 3 has a thickness of about 150, which does not break down for 10 years or more when 5 V is applied to the gate electrode 12.
Å is selected. For breakdown, the electric field applied to the gate insulating film 3 may be set to about 3.5 MV / cm or less.

Next, a high breakdown voltage MOS which is important for the present invention.
The structure of the transistor 15 will be described. High breakdown voltage MO
The S transistor 15 is also provided on the surface of the P-type silicon substrate 1 like the low breakdown voltage transistor 14. Low voltage M
The structural difference from the OS transistor is that a part of the drain region has a low concentration of N in order to obtain high breakdown voltage characteristics.
The ± -type drain region 6 is provided, and the insulating film 2 thereabove is used as a field insulating film and is thicker than the gate insulating film 3. The N ± type means that the N type impurity concentration is lower than the impurity concentration shown by the N ⁺ type and is higher than the impurity concentration shown by the N ⁻ type. The impurity concentration represented by the relationship of N ⁺ type> N ± type> N ⁻ type is defined as N ± type.

The gate insulating film 3 is formed of an oxide film having a film thickness of 100 Å to 200 Å which is the same as that of the low breakdown voltage transistor 14. For example, even if a high voltage of 50 V, which is 10 times the power supply voltage, is applied to the drain region 7, the drain region 6 having a low concentration in contact with the gate oxide film 3 is depleted, so that 50 V is directly applied to the gate insulation. It is designed not to be applied to the membrane 3. The high voltage of 50 V applied to the drain region 7 is applied not to the gate insulating film 3 but to the lightly doped N ±
It is applied to the field insulating film provided on the drain region 6.

Therefore, the thickness of the gate insulating film 3 may be designed so that it will not be destroyed for 10 years or more when a power supply voltage is applied to the gate electrode 13. If the power supply voltage is 5V, it is the same as the low breakdown voltage transistor, so about 150Å
It can be made as thin as a film. The concentration of the N ± drain region 6 is high as a whole, for example, 10 ¹⁹ atoms / c
When it is as high as m ² or more, the drain voltage is almost applied to the gate insulating film 3 as it is, so that the gate insulating film must be thicker than about 1000 Å at which it is not destroyed.

The high breakdown voltage MOS transistor of the present invention is
Thin drain region 6 under and near the gate oxide film 3
By the concentration of 10 ¹⁸ atoms / cm ² and a low concentration, allowed the thickness of the gate insulating film 3 so as not to directly apply the drain voltage to the gate insulating film 3. Since the gate insulating film 3 can be made very thin, the low breakdown voltage / low voltage transistor 14 and the high breakdown voltage / high voltage transistor 15 can be easily formed on the surface of the same substrate 1 as shown in FIG.
FIG. 3 is a simple electric circuit diagram of an integrated circuit in which a power supply voltage VDD drive transistor and a high breakdown voltage transistor having twice or more the power supply voltage are provided on the same substrate. For example, a thermal head driver IC. High voltage transistor 40
And a control circuit for controlling the gate voltage is one chip. The control circuit operates at a power supply voltage of 5V. A high voltage of 50 V is applied to the drain region of the high breakdown voltage transistor 40 via a load R (thermal head).

In the circuit shown in FIG. 3, when the high breakdown voltage transistor 40 is in the OFF state, a high voltage of 50 V is applied to the drain electrode. Therefore, high breakdown voltage characteristics are required. On the other hand, when the high breakdown voltage transistor 40 is in the ON state, the drain electrode has a ground potential of approximately Vss, so that the high breakdown voltage is not applied. Therefore, O
It suffices to satisfy the high breakdown voltage characteristics only in the FF state. In the case of a thermal head IC, 1 for the thermal head that is the load R
It is necessary to pass a large current of 0 mA or more. Generally MOS
The transistor has a low current drive capability. However, if the high breakdown voltage MOS transistor of the present invention is used, the gate insulating film can be made very thin, so that the current driving capability can be obtained in a small area. The gate insulating film of the high breakdown voltage transistor may be a nitride oxide film instead of a silicon oxide film, or may be a composite film of an oxide film and a nitride film.

FIG. 4 is a diagram showing the gate oxide film thickness dependency of the current driving capability K value of the gate voltage with respect to the breakdown voltage of the drain voltage and the drain current of the high breakdown voltage transistor. By thinning the gate oxide film 3,
It shows that the current drivability K value can be increased without decreasing the drain breakdown voltage. Current drive capability can generally be doubled by halving the gate oxide thickness.
The high withstand voltage MOS transistor of the present invention has a slow increase rate of the current driving capability K value as the gate oxide film is made thinner. The reason is that a thin drain region 6 and a thin source region 4 are connected in series to the current path in the channel region in order to achieve a high breakdown voltage.

FIG. 5 is a sectional view of a high voltage MOS transistor according to the second embodiment. A high breakdown voltage source region 4 or a thin concentration drain region 6 for high breakdown voltage, which is directly connected to a current path, is improved to have a low resistance structure. FIG. The source region 5 is formed of the same N ⁺ type diffusion region as the low breakdown voltage transistor. The drain region has a high breakdown voltage structure so as to withstand a high drain voltage application. The drain region in contact with or in the vicinity of the gate insulating film 3 is formed of a lightly doped N-type drain region 42 in order to obtain high breakdown voltage characteristics. This N ⁻ type drain region 42
Are formed between the heavily doped N ⁺ type drain region 7 forming the drain electrode and the channel region. A field oxide film 2 is formed on the N ⁻ type drain region 42. Wherein the high breakdown voltage transistor of Figure 5, a low concentration N ^- 10 ¹⁹ inside the type drain region 42 atoms /
That is, the N ± type drain region 41 having a high concentration of about cm ² is provided. This N ± type drain region 41
Are provided under the thick field oxide film 2.
It is not provided in the inclined portion of the field oxide film 2 called the bird's beak region. N ⁻ type drain region 4
The 2 and N ± type drain regions 41 are both provided in self-alignment with the field oxide film 2. By using the high breakdown voltage transistor structure as shown in FIG. 5, the series resistance connected to the channel region becomes small. Therefore, the channel drain region of the gate voltage and the current driving capability are further improved.

FIG. 6 is a sectional view of a high voltage MOS transistor according to the third embodiment. The gate insulating film 53 is 100
It is formed with a very thin film thickness of Å ~ 200Å. Therefore, the resistance of the channel region between the N ⁻ type source region 52 and the N ⁻ type drain region 55 can be made very small. Further, in order to improve the current driving capability of the high breakdown voltage transistor, it is necessary to reduce the resistance of the source region 52 and the drain region 55, which are arranged in series in the channel region and have a low concentration. In the high breakdown voltage transistor of FIG. 5, a deep N ⁻ type drain region 56 is formed so as to cover a part of the lightly doped drain region 55 and the N ⁺ type drain region 57. The drain resistance can be reduced by providing the deep region 56.
In particular, since the N ⁻ type drain region 55 and the N ⁺ type drain region 57 are formed in self-alignment with the field oxide film 2, there is a drawback that the resistance of the connection region is high. As shown in FIG. 5, the N ⁻ -type drain region 55 and the N ⁺ -type drain region 5 are formed.
By enclosing the connection region with 7 with this deep N ⁻ type drain region 56, this drawback of high resistance is solved.

Further, the structure of the source region is formed differently from the structure of the drain region. Even in the low breakdown voltage transistor, when the channel length is formed with a length of submicron, deterioration due to generation of hot electrons becomes a problem even if the power supply voltage is as low as 5V. So L
There is no choice but to use a transistor called a DD (Lightly Doped Drain) structure. In the high breakdown voltage transistor of the present invention shown in FIG. 5, the source region has this LDD structure. That is, by forming the source region in the same structure as the low breakdown voltage transistor, it can be easily formed on the same substrate. Since the length of the N ⁻ type source region 52 is very short,
It does not cause a decrease in current drive capability.

In FIG. 6, a deep and thin N ⁻ type drain region 56 is provided in self-alignment with the field oxide film 2. That is, by using the field oxide film 2 as a mask and simultaneously implanting an impurity having a large diffusion coefficient such as phosphorus and an impurity having a small diffusion coefficient such as arsenic, a deep N ⁻ type drain region 56 and a shallow deep drain region 56 are formed. 57 and 57 are formed in self-alignment with the field oxide film 2. Therefore, all drain regions 55, 56
And 57 are formed in self-alignment with the field oxide film 2.

FIGS. 7A and 7B are sectional views of a part of a high breakdown voltage MOS transistor showing the principle that the high breakdown voltage transistor of the present invention can obtain high breakdown voltage characteristics with a gate insulating film of 100 Å to 200 Å. is there. First, from (a),
FIG. 6 is a cross-sectional view in the vicinity where the gate insulating film 3 and the lightly doped N ⁻ type drain region 6 are in contact with each other. 5 as drain voltage
When a large voltage such as 0 V is applied, a depletion layer of 50 V in a reverse bias applied state is formed between the substrate 1 and the N ⁻ type drain region 6. A depletion layer 61 is formed on the substrate 1 side, and a depletion layer 62 is formed on the N ⁻ type drain region 6 side. The depletion layer is an electrically high resistance region similarly to the gate insulating film 3. As shown in FIG. 7A, the portion under the gate insulating film 3 and a portion of the bird's beak (slope portion) of the field insulating film 2 are completely depleted. Therefore, the drain voltage of 50 V is applied only to the point B which is the end of the depletion layer. Since the insulating film above the point B is a thick film between the field insulating film and the gate insulating film as shown in the figure, the breakdown voltage is high. The film thicknesses of the N ⁻ type drain region 6 and the field insulating film 2 may be set so that the film thickness above the point B is about 3.5 MV / cm or less with respect to the drain voltage. In the case of 50V, the film thickness of the field insulating film 2 is 200
0 Å, N ⁻ -type drain region concentration is 10 ¹⁸ atoms /
It must be set to cm ² or less.

Further, as shown in FIG. 7 (b), FIG.
Need not have a thick insulating film. This is because, as shown in FIG. 7B, the depletion layer extends to the N ⁺ type drain region from directly below the gate electrode, and the high voltage is applied between the point C and the gate electrode end. Therefore, the high voltage is not directly applied to the film thickness of the gate insulating film 3, but the high voltage is applied to the film thickness larger than the actual film thickness. The junction between the N ⁺ type drain region 7 and the substrate immediately below the gate oxide film is separated from immediately below the gate electrode, and the distance between point C and the gate electrode end (film thickness)
May be set to about 3.5 MV / cm or less with respect to the drain voltage, and the concentration of the N ⁻ type drain region 6 and the junction position with the substrate may be set.

FIG. 8 is a sectional view in order of the processes, showing a method for manufacturing the high breakdown voltage MOS transistor shown in FIG. First, as shown in FIG. 8A, a nitride film 8 for performing normal selective oxidation is used.
2 is patterned through the resist film 83. First, phosphorus is ion-implanted using the nitride film 82 as a mask. Next, a resist is formed on the entire surface, and the resist etching is performed again, so that the sidewalls 84 of the resist are formed so as to separate the nitride film as shown in FIG. 8B.
This sidewall may be formed of a nitride film or an oxide film or another film such as polycrystalline silicon instead of the resist film. Then, using this sidewall as a mask, arsenic atoms are ion-implanted.

Next, as shown in FIG. 8C, selective oxidation is performed at a high temperature of about 1000.degree. Oxidation proceeds only in the region without the nitride film to form the field oxide film 85. The phosphorus and arsenic impurities that have been ion-implanted into the selective oxide film are diffused to form N − type diffusion regions 87 and N ± type diffusion regions 86. Since arsenic has a smaller diffusion coefficient than phosphorus, it forms the N ± type diffusion region 86. Next, the unoxidized nitride film 82 is removed to expose the clean surface of the silicon substrate 1, and the gate insulating film 88 and the gate electrode 89 are formed. After patterning the gate electrode 89 by a photo process, the gate electrode 89 and the field oxide film 85 are formed.
Is used as a mask to form a source region 90 and a drain region 91, which is completed. Since the gate insulating film is thin, ion implantation can be easily performed. As is clear from this step, the N ± type drain region 86 is formed by ion implantation well inside the window of the nitride film 82 that serves as a mask for selective oxidation. Therefore, after the selective oxidation, as shown in FIG. 8D, it is formed only under the sufficiently thick field oxide film. That is, it is not formed on the inclined portion called bird's beak. On the other hand, the N ⁻ type drain region 8
7 is formed by just ion-implanting into the window of the nitride film that serves as a mask for selective oxidation. Further, since the impurities are phosphorus atoms having a large diffusion coefficient, they are sufficiently formed even under the bird's beak after the selective oxidation.

The high withstand voltage MOS transistor of the present invention is characterized in that the gate insulating film is formed to a very thin film thickness of 100 to 200 Å. By using the film thickness in this region, the quality and yield of the high breakdown voltage transistor are improved. The gate insulating film is generally formed of a thermal oxide film. In the case of oxidation of 200 Å or more, some defects inside the surface of the silicon substrate cause defects inside the insulating film. Therefore, as the thickness exceeds 200Å, the dielectric strength voltage decreases. In the case of the high breakdown voltage transistor of the present invention, since it can be formed with an oxidation amount that uses only a slight defect-free layer existing on the surface of the silicon substrate, a high breakdown voltage characteristic in which no defects are introduced into the insulating film is obtained. That is, a high-voltage and high-yield high-voltage transistor can be obtained.

The high breakdown voltage MISFET described above has a structure in which a field insulating film is provided on a drain region having a low concentration in order to achieve a high breakdown voltage. The embodiment described below has a structure in which an inversion layer is used instead of the drain region having a low concentration in order to achieve a high breakdown voltage. The inversion drain region is electrically formed by a drain electrode provided via a thin insulating film.

FIG. 9 shows the reverse drain of the fourth embodiment of the present invention.
FIG. 9 is a cross-sectional view of a high breakdown voltage MISFET using an in region.
A case where the MISFET is an N-type transistor will be described.
It The impurity concentration on the surface of the P-type silicon substrate 201 is about 1
0²⁰atoms / cm³ N ⁺ The source region 202 of the mold
A drain region 203 is provided. Each area is
The source electrode 20 is provided through the contact hole of the edge film 213.
7 and the drain electrode 208. Source area 2
02 on the surface of the substrate 201 between the drain region 203 and
A first gate oxide film 205 is formed on a channel region.
When the first gate electrode 206 is provided via
Through the second gate insulating film 211 having a small thickness
Of the gate electrode 212 connected to the drain electrode 208
Is made. The drain electrode 208 of the insulating film 213
The contact hole is formed by the second gate electrode 212 and the drain.
It is formed in one shape on the scan area 203.

The operation of the high breakdown voltage MISFET shown in FIG. 9 will be described. When a high voltage is applied to the drain electrode 208, the electrode that controls the switching operation of the transistor is the first gate electrode 206. For example, when a high voltage of about 30 V is applied to the drain electrode 208, the same high voltage is applied to the second gate electrode 212. Therefore, the surface of the substrate 201 below the gate electrode 212 is also inverted, and the surface potential becomes an intermediate potential between 0V and 30V. That is, an inversion region is formed below the gate electrode 212, and that region effectively functions as a drain region. Further, the electrically formed drain region which is the inversion region is lowered to a voltage lower than the voltage of the N ⁺ type drain region 203.

Therefore, the effective channel length is the source region 2
02 and the inversion layer 215. This effective channel region is controlled by the gate electrode 206. The depletion layer of the inversion layer 215 does not extend so much toward the source region 202. The effective impurity concentration of the inversion layer 215 is the same as that of the substrate 201. Therefore, a depletion layer is formed uniformly in the direction of the substrate 201 and inward of the inversion layer 215. A part of the high voltage applied to the drain region 203 is applied to this depletion layer. The channel conductance of the transistor is determined by the short effective channel length and thin gate insulating film 205. Therefore, it is possible to flow a channel current more than double that of the conventional one.

Also, the second gate electrode 212 below the second
The gate insulating film 211 has a very thin structure with a thickness of 200 Å or less. The drain electrode 208 has a structure in which the drain region 203 and the second gate electrode 212 have the same potential. Therefore, the second gate insulating film 2
Almost no electric field is applied to 11. Therefore, 50
It can be thinned to ~ 100Å. Furthermore, since the thicknesses of the first gate insulating film 205 and the first gate insulating film 211 are both very thin, less than 200 Å, it is possible to reduce the change with time of the channel current when hot electrons are injected. . First gate electrode 2 on the gate insulating film
06 and the second gate electrode 212 are preferably formed of a polycrystalline silicon film. This is because the polycrystalline silicon film is hard to react with the oxide film.

In the case of the present invention shown in FIG. 9, the voltage applied to the drain region 203 drops within the substrate 201. The place where the voltage drop (potential change) is N
A contact surface between the ⁺ type drain region 203 and the inversion layer 215,
Inversion layer 215 and effective channel region (gate electrode 206
And the contact surface with the lower substrate surface). At least a high voltage of 30 V is dropped at two points in the substrate. Therefore, since the high voltage does not drop at one place, even if the high voltage is applied to the drain region 203, the breakdown in the silicon substrate hardly occurs. The high breakdown voltage MISFET of the present invention is effective for applications in which only the power supply voltage is applied to the first gate electrode.

FIG. 10 shows the high breakdown voltage of the fifth embodiment of the present invention.
It is a sectional view of MISFET. N⁺Type drain region 20
N around 3^- A type drain region 221 is provided
It N ^- The type drain region is at least the channel region side
To N⁺ If it is provided in contact with the mold drain region 203
Yes. Also N^- The type drain region 221 is at least as shown in FIG.
0 on the surface of the substrate 201 under the gate electrode 223
It is formed in part. N ^- Type drain region 221
The pure substance concentration is at least 5 × 10 5 on its surface. ¹⁶a
toms / cm³ Above, 5 × 10¹⁸atoms / cm³ 
It is preferable to set a low density between the following. Figure 1
0 in contact with the drain region 203 and N ^- Type dray
The surface area 3 of the substrate 201 is
The high voltage applied to the drain region 203 drops at several places.
It That is, the drain region 203 and the N^-Type drain region 2
21 and the inversion layer 215 and N.^- Type dray
Substrate surface in contact with the drain region 221 and the inversion layer 215.
There are three locations on the substrate surface that are in contact with the effective channel region.
The structure is such that the high drain voltage is stepped down at these three points.
There is. Therefore, from the high breakdown voltage MISFET of the embodiment of FIG.
High breakdown voltage characteristics can be obtained.

Also, a large amount of channel current can flow. N ⁻ type drain region 221 as compared with the inversion layer 215
Has a smaller resistance value. Therefore, the resistance connected in series to the effective channel region is reduced, and as a result, a large channel current (drain current) can be passed.

FIG. 11 is a sectional view of a high breakdown voltage MISFET according to the sixth embodiment of the present invention. With respect to the high breakdown voltage MISFET of the embodiment of FIG. 10, a P-type impurity region 231 is provided at a deeper side next to the channel region side of the N ⁺ type drain region 232 and the N ⁺ type source region 202 which are deeper and deeper.

First, the high concentration N ⁺ type drain region 23 is formed.
By 2, the drain resistance can be improved by lowering the drain resistance connected in series with the channel region. In this case, the depth of the N ⁺ -type drain region 232 is such that when a high voltage is applied to the region 232.
The depth is about the same as the width of the depletion layer. When the N ⁻ type drain region 221 is provided as shown in FIG.
It may be deeper than the width of the depletion layer. Although not shown, FIG.
In the first embodiment, high breakdown voltage characteristics can be obtained even if the N ⁻ type drain region 221 is not formed. In this case, the depth of the deep N ⁺ type drain region 232 is the substrate 20.
It is necessary to make the width shallower than the width of the depletion layer formed between 1 and 1. Even if the N ⁻ -type drain region 221 is not provided, an inversion layer is formed below the gate electrode 223, and the drain layer can be connected to the depletion layer of the deep N ⁺ -type drain region 232 to allow a large amount of drain output. When the deep N ⁺ type drain region 232 is provided as shown in FIG. 11, a punch-through phenomenon may occur with the source region 202 and the breakdown voltage may be lowered. To prevent the punch-through phenomenon, the P-type impurity region 231 may be provided at a deep position next to the source region 202.
If the concentration of the P-type impurity region 231 is higher than that of the substrate 201 by about one digit, punch-through can be prevented. P
The depth of the type impurity region 231 is deep N ⁺ type drain region 2
It is provided at the same level as 32.

FIG. 12 is a sectional view of a semiconductor integrated circuit of a seventh embodiment in which the high breakdown voltage MISFET of the present invention and a normal power supply voltage operation MISFET are formed on the same substrate surface. As shown in FIG. 12, a LVMOSFET operating with a power supply voltage
(Low Voltage MOSFET) and HVMOSFET (HighVolt
and a stage MOSFET) are formed on the surface of the same substrate 101. The structure of the HVMOSFET is a high breakdown voltage MISFET having the structure shown in FIGS. 9, 10 and 11.
In the LVMOSFET, an N ⁺ type source region 102 and an N ⁺ type drain region 103 are provided with a space between each other, and a gate electrode 105 is formed on a channel region, which is the surface of the substrate 101 between them, via a gate insulating film 104. It is provided.

In the semiconductor integrated circuit of FIG. 12, the LVM
The gate insulating films 104 and 114 of the OSFET and the HVMOSFET are simultaneously formed of 100 to 200 Å, and the gate electrodes 105 and 116 thereon are also formed of polycrystalline silicon. And the like. Therefore, LVMOSFET and H
It is formed at the same time as the VMOSFET, and the threshold voltage, which is an important electrical characteristic thereof, can be easily set to the same value.
That is, it is not necessary to control the electrical characteristics of the LVMOSFET and the HVMOSFET separately, and the circuit design is easy. Since the gate insulating film 104 of the LVMOSFET has a thin film thickness of 100 to 200Å, high integration is easy. The LVMOSFET can be easily formed with a design rule of 1 μm or less. Therefore, a highly integrated and high-speed operation circuit can be integrated.

FIG. 13 is a sectional view of another embodiment of the high breakdown voltage MISFET of the eighth embodiment of the present invention. P substrate 30
N ⁺ type source regions 30 spaced apart from each other on the surface
2 and a drain region 304 are provided. The N ⁺ type drain region 304 is not formed under the gate electrode 306. The concentration between the channel region formed in the semiconductor substrate 301 below the gate electrode 306 and the N ⁺ type drain region 304 is 1 × 10 ¹⁶ atmos / cm ³ to 1 ×.
10 ¹⁸ atoms / cm ³ and N ⁺ type drain region 304
A thinner drain region 303 is provided.
The N ⁻ type drain region 303 can also be considered as a drain resistance connected in series to the channel region.

Therefore, in order to allow a sufficient drain current to flow, the N ⁻ -type drain region 303 is generally formed deeper than the N ⁺ -type drain region 304. The gate insulating film of the high breakdown voltage MISFET shown in FIG. 13 is also 100Å to 200Å
The film thickness is set to between. Only 5V which is a power supply voltage is applied to the gate electrode 306. However, a voltage of 10 V or higher, which is higher than the power supply voltage of 5 V, is applied to the drain electrode 308.

As shown in FIG. 13, the high withstand voltage MI of the present invention.
In the SFET, the gate insulating film 305 is thinned,
In addition, high breakdown voltage characteristics can be obtained by reducing the concentration of the drain region provided below the drain region. For example, a case where the output voltage to the gate electrode 306 is 0V and the drain voltage is 30V to the drain electrode 308 will be described. When the drain voltage 30V applied, N ^-
The surface of the mold drain region is depleted by the voltage of the gate electrode 306. The resistance of the depletion region is determined by the gate insulating film 30.
There is a lot of resistance as well as 5. Therefore, the applied drain voltage is divided between the gate insulating film 305 and the depletion layer 310.
That is, high withstand voltage characteristics can be obtained. N ⁻ type drain region 30
3 has a structure in which the surface of the N ⁻ type drain region 303 in the overlapping portion of the gate electrode 306 and the gate electrode 306 is depleted to obtain high breakdown voltage characteristics. In order to make it easier to deplete, not only the concentration of the N ⁻ type drain region 303 is made thin, but also the thickness of the gate insulating film 305 is made thin. When the thickness of the gate insulating film is large as in the conventional case, the surface of the N ⁻ type drain region 303 is hard to be depleted because the electric field from the gate electrode 306 is weak. Gate insulating film 30
5 of the film thickness is thinned from 100Å to 200 Å, and, N ^-
The concentration of the mold drain region 303 is set to 1 × 10 ¹⁶ atoms /
Effective depletion is achieved by setting from cm ³ to 1 × 10 ¹⁸ atoms / cm ³ . In FIG. 13, the source region 302 has almost no effect on the high breakdown voltage characteristic. Therefore,
It may have the same structure as the drain region.

FIG. 14 is a sectional view of another embodiment of the high breakdown voltage MISFET of the ninth embodiment of the present invention. The embodiment of FIG. 14 is an example in which an N ⁻ -type drain region 311 is further provided below the N ⁻ -type drain region 303 in addition to the embodiment of FIG. Since the concentration of the N ⁺ type drain region is low, its resistance is generally high. In order to solve the problem, the N ⁺ type drain region 311 is provided below the N ⁻ type drain region 303. By providing the N ⁺ type drain region 311 at the bottom of the N ⁻ type drain region 303 away from the surface, the drain resistance can be reduced. The depth of the N ⁺ type drain region needs to be formed deeper than the depletion layer width generated on the N ⁻ type drain region side when a high voltage is applied. If it is formed shallower than the depletion layer, the breakdown voltage will decrease.

FIG. 15 is a sectional view of another embodiment of the high breakdown voltage MISFET of the tenth embodiment of the present invention. The drain region is composed of an N ⁺ type drain region 304, an N ⁻ type drain region 303, and a P ⁻ type drain region 312 in which P type impurities are diffused. The principle is
Is the same as the embodiment described above. By forming the surface of the N ⁻ type drain region 303 with a low concentration and forming the deep region with a high concentration, depletion is facilitated and the resistance is reduced. In the embodiment of FIG. 15, the N-type impurity concentration is relatively lowered by diffusing the P-type impurity of the opposite conductivity type in the drain region only on the surface. The P-type impurity introduction region 312 is provided on the surface of the N ⁻ -type drain region 303 and needs to be provided at least at the end of the gate electrode 306. As shown, it may not be connected to the N ⁺ type drain region 304.

High breakdown voltage MIS of FIGS. 13, 14 and 15
In the case of the FET, the diffusion layer in the drain region is simply made to have a high breakdown voltage structure. Therefore, it can be easily formed on the same substrate as the LVMOSFET having no N ⁻ type drain region for high breakdown voltage. LVMOSFET and HVMOSFE
The channel region with T, the gate insulating film, and the gate electrode have exactly the same structure. Therefore, the threshold voltage and conductance, which are important electrical characteristics of the MOSFET, can be controlled together. Therefore, it is not necessary to separately process-control the high breakdown voltage transistor and the low breakdown voltage transistor in terms of manufacturing. Only the withstand voltage characteristic is controlled by the structure of the drain region. Therefore, L
VMSOFET and HVMOSFET can be integrated with high controllability.

In the present invention, the LVMOSFET is a transistor applied with a power supply voltage, and is an HVMOSFE.
T refers to a transistor to which a high voltage that is three times the power supply voltage or more is applied. Therefore, more generally, according to the present invention, it is possible to provide a transistor to which a voltage whose operating voltage (applied voltage) is three times or more different is applied on the same substrate.

FIG. 16A is a schematic block diagram showing a semiconductor integrated circuit device according to the eleventh embodiment of the present invention. 5
It is a three-terminal voltage regulator (Vr) with a positive V voltage and a rated voltage of 24V. The error amplifier 1006 has a feedback resistor RA1.
004 and a part of the output voltage fed back by the RB 1005 and the reference voltage VR in the reference voltage circuit 1007.
The EF is compared, and the gate voltage required to maintain a constant output voltage Vout is output to the P-channel transistor 1002.
Is to be supplied to. Vin1001 is an input (terminal), Vout1002 is an output (terminal), GND100
8 represents a ground (ground).

FIG. 16B is a graph showing the relationship between Vin and Vout showing the operation of Vr in the eleventh embodiment of the present invention. A regulated 5V constant voltage is output from about 5.1V of ViN, and the constant voltage is maintained up to about 26V.

FIG. 17 is a detailed circuit diagram showing the semiconductor integrated circuit device of the eleventh embodiment of the present invention. The reference voltage circuit 1007 is a depletion transistor M7 200.
7 and an enhancement transistor M8 2008, the error amplifier 1006 drives a differential amplifier including transistors M1 to M4 by a constant current circuit of M5 transistor. M6 1002 is a P-channel MOS output transistor.

FIG. 18 is a plan view showing a semiconductor integrated circuit device according to the eleventh embodiment of the present invention. Output transistor M
It can be seen that the area 3002 of No. 6 occupies more than half of the entire area. However, chip size X3006 and Y30
Both 07 are within about 1 mm. In such a case, the chip size is referred to as 1 mm □.

FIG. 19A is a schematic block diagram showing a portion of the output transistor M6 according to the eleventh embodiment of the present invention. As shown, the potential between the gate, the source, and the substrate (representing the transistor's substrate) is set to VGS40.
04, the potential between the gate and the drain is VGD4005, and the potential between the drain, the source and the substrate is VDS4006.

FIG. 19B shows VGS with respect to the output current Iout of the output transistor M6 according to the eleventh embodiment of the present invention.
It is a graph which shows the value of. FIG. 20 shows Vin, Vout, VDS of the output transistor of the eleventh embodiment of the present invention.
9 is a table showing values in the case of VGD, VGS, and Iout.

It can be seen that VGS only goes up to about 6V at the maximum. When the output is 0 mA, VDS is actually applied up to the rated input voltage of 24V. FIG. 21 is a schematic sectional view showing an output transistor (PMOS) of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

The thickness Tox1 6001 of the gate insulating film is 400 Å (400 Å, which means that there is a variation in manufacturing in practice, and there is a width of ± 30 Å in 3σ. Other film thickness values are also "aim". That's what it means)
And other transistors on the same semiconductor substrate are 800Å
It is what As explained variously, the thickness of the gate insulating film of the transistors other than the output is 800 Å because it is rated at 24 V, and the thickness of the output transistor is 170 Å or more because it is 5 V output, and it is 370 Å or more from the viewpoint of securing the ESD resistance. It is because it is prescribed. LO
The drain of the COS drain structure is the FD drain (P ± type layer 60) of the depletion layer 6010 when an electric field is applied to the drain.
Since the electric field is carried on the A point 6007 at the end extending toward the (03) side, the gate insulating film thickness is substantially Tox2 6002 and 20
There will be from 00 to 3000Å. Therefore, like other 800Å transistors, it can withstand the 26V breakdown voltage and, at the same time, has sufficient TDDB. In this way, the output transistor has a sufficient g of 1.3 μA / V2.
It is possible to obtain m and obtain a high-performance and low-cost Vr semiconductor integrated circuit device with a chip size of about 1 mm □ that satisfies a rated ESD of 24 V and an output current of 0.5 A and a sufficient ESD tolerance. .

FIG. 22 illustrates a Vr semiconductor integrated circuit device according to the eleventh embodiment of the present invention, which is rated at 24V, 0.
It is a graph showing the chip size when the gate insulating film thickness of the output transistor for obtaining Vr of 5 A output is changed. It can be seen that the chip size can be significantly reduced compared to the conventional one.

FIG. 23 illustrates a Vr semiconductor integrated circuit device according to the eleventh embodiment of the present invention, which has a rating of 24 V and a distance of 1 m.
It is a graph showing how much output current can be obtained with a constant m □ chip size. It can be seen that, in the conventional case, only about 250 mA can be taken.

FIG. 24 is a schematic sectional view showing the relationship between the PMOS and NMOS of the semiconductor integrated circuit device according to the eleventh embodiment of the present invention. The FD drain N ± type layer 9002 has a dose of phosphorus 1.4E ¹³ / cm ² in consideration of the drain breakdown voltage and the series resistance of the drain (in the case of doses thereafter /
cm ² is omitted), and the field-doped field isolation N ± type layer 9010 is formed with a dose of phosphorus 3E ¹² in order to set the inversion voltage of the element isolation region to a desired value or more. Similarly to the N ± type layer, the drain P ± type layer 9011 is formed with a dose amount of boron 1.4E ^{14 in} consideration of the drain withstand voltage and the drain series resistance, and is a field-doped field-doped P ± type layer. The layer 9007 is also formed with a dose amount of boron 1E ¹⁴ in order to make the inversion voltage of the element isolation region equal to or higher than a desired value, and the dimension between the FD drain and the field isolation field isolation for element isolation is as shown in FIGS. 25 and 26. Can be decided

FIG. 25 shows the overlap length of the PMOS / drain low-concentration layer from the high-concentration layer (this length means that the high-concentration layer is surrounded by the low-concentration layer) and the FD drain-element. It shows the breakdown voltage between the FD drain and the field dope for element isolation when the distance between the field dopes for isolation is changed. The overlap length of the low concentration drain layer from the high concentration layer and the distance between the FD drain and the field dope for element isolation when the junction breakdown voltage is equal to or higher than the desired breakdown voltage are determined from this figure.

Further, FIG. 26 shows that the overlap length of the low concentration layer of the NMOS / drain from the high concentration layer and the distance between the FD drain and the field dope for element isolation are changed. It shows the breakdown voltage. The distance between the FD drain and the field dope for element isolation is determined from FIG.
016 and FIG. 24-d9017 are both 1 μm or more, and FIG.
4-a9006 is 0.5 μm or more, and FIG.
9 must be separated by 0.5 μm or more. This makes it possible to achieve both the junction breakdown voltage and the element isolation breakdown voltage. By forming the FD drain in the LOCOS drain structure separately from the field dope for isolation, it is possible to prevent the series resistance of the drain from increasing.

FIG. 27 is a schematic sectional view of an NMOS of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention. The LOCOS is formed on the N ^- epi layer on the P substrate as in the first embodiment.
An FD drain N ± type layer 12006 is formed in the drain structure, and a deep P ⁻ from the LOCOS end to the source region is formed.
A channel region is formed in the region 12003. With this structure, it is possible to prevent an increase in series resistance of the drain without lowering the breakdown voltage. In addition, since the gate oxide film is partly thicker, the gate input capacitance is reduced and switching Time becomes faster. FD drain N ± type layer 12006 and channel region 1
The distance between 2003 or the dimension e12008 is 0.5
With a thickness of at least μm, the breakdown voltage can be further increased. Further, the gate oxide film may be thinned to 400 Å as in the first embodiment. When an electric field is applied to the drain, the electric field is carried by the end of the depletion layer extending to the FD drain (N ± type layer 12006) side, so that the gate insulating film thickness is substantially 3
This is because there will be 000Å.

FIG. 28 is a schematic sectional view showing a Vr semiconductor integrated circuit device according to a thirteenth embodiment of the present invention. The drain structure is a DDD structure. N- formed with a dose of phosphorus 1E14 using the gate electrode as a mask
The thin drain of the P− type layer 13014 formed with the dose amount of the type layer 13003 and the boron 5E14 makes the extension of the depletion layer on the drain side favorable, and makes it possible to realize a desired drain breakdown voltage as in the LOCOS drain structure. It is a thing. However, the L length does not increase, and the area can be further reduced. After that, a side spacer is formed and ion implantation for the N + type layer and the P + type layer is performed. Also in such a DDD structure with a side spacer, the breakdown of the junction between the drain and the field-doped must be considered next time, but if the concentration of the field-doped is lowered too much, sufficient isolation breakdown voltage between elements cannot be obtained. , There, FIG. 28-f13006, g13
By separating them by 1 μm or more as in 010, it is possible to achieve both the junction breakdown voltage and the element isolation breakdown voltage.

FIG. 29 shows the ONO of the fourteenth embodiment of the present invention.
6A to 6C are cross-sectional views in order of the processes, showing a method for manufacturing a transistor having a structure. The structure of the gate insulating film is ONO for the output transistor.
The other transistors have a normal SiO ₂ single layer structure.

The manufacturing method of the ONO gate insulating film is as follows (a)
First, silicon is thermally oxidized (either Dry or Wet may be used at any temperature) to form a SiO ₂ layer of> 100 Å (referred to as a bottom oxide film). (B) Next, by LPCVD, SiH ₂ Cl at 750 ° C. to 770 ° C.
₂ and NH ₃ are introduced to deposit a SiN film. (C)
The SiN film is removed only from the other transistors, and (d) thereafter, the SiN film of the output transistor is oxidized by wet oxidation at 900 ° C. to 1000 ° C. to form a SiO ₂ layer (referred to as a top oxide film). Top oxide film is CVD
You may form by. Using LPCVD equipment, Si
H ₂ Cl ₂ and N ₂ O were introduced, and the pressure was adjusted to 60 P at 850 ° C.
It is formed by setting it to about a. If the top oxide film is formed by CVD, the heat treatment can be performed at a relatively low temperature, and the collapse of the channel doping impurity profile can be reduced. (E) Further, this time, the oxide film is removed only from the other transistors, and (f) the gate oxide film having a desired film thickness is formed by thermal oxidation. At this time, the output transistor is SiN
Since the film and the SiO ₂ film are formed, the oxidation hardly progresses. As described above, by controlling each film thickness,
The desired capacity and breakdown voltage can be realized.

FIG. 30A is a schematic sectional view showing a semiconductor integrated circuit device of a voltage regulator according to a fourteenth embodiment of the present invention. The structure of the gate insulating film is such that the output transistor and the other transistors also have the ONO structure. FIG. 30B is a table showing a film thickness configuration for each transistor of the ONO structure according to the 14th embodiment of the present invention.

With such a structure, the SiN film has a relative permittivity per unit film thickness that is about twice that of SiO2. Therefore, if the total film thickness is the same, the ONO structure is more Si.
A gm larger than that of the O2-layer transistor was obtained, and the area of the output transistor could be further reduced. TDD
Also in terms of B, it has become possible to realize a more reliable semiconductor integrated circuit device.

[0080]

As described above, according to the present invention, in the high breakdown voltage MISFET, the gate insulating film has a thickness of 100 to 200.
Å and the thin film structure have the effect of preventing an increase in the channel current per unit channel width and the change of the channel current with time. Furthermore, since the gate insulating film of the high breakdown voltage MISFET and the gate insulating film of the low voltage MISFET operating at the power supply voltage can be formed by a thin film of 100 to 200Å, the high speed LVMOSFET circuit and the high breakdown voltage MOS can be formed.
The FET and the FET can be formed on the same substrate while maintaining their characteristics.

By adopting a structure in which the gate insulating film thickness of the output transistor is thinner than the gate insulating film thickness of the other transistors (transistors constituting the error amplifier or the reference voltage circuit) on the same substrate, the output transistor is Sufficient gm of 1.3 μA / V2 can be obtained, with a chip size of 1 mm □, rated 24 V, output current 0.5.
A It is possible to realize a high-performance and low-cost Vr semiconductor integrated circuit device that has never been desired to satisfy the maximum sufficient ESD tolerance.

[Brief description of drawings]

FIG. 1 shows a low breakdown voltage MOS transistor of the present invention and a high breakdown voltage M.
FIG. 9 is a cross-sectional view of an integrated circuit in which an OS transistor and an OS transistor are formed over the same substrate.

FIG. 2 is a sectional view of a conventional high voltage MOS transistor.

FIG. 3 is a simplified circuit diagram of the integrated circuit of the present invention.

FIG. 4 is a characteristic diagram showing a gate insulating film thickness dependency of a current driving capability K value and a drain withstand voltage of a semiconductor device which is a high breakdown voltage MOS transistor of the present invention.

FIG. 5 is a cross-sectional view of another embodiment of a semiconductor device which is a high voltage MOS transistor of the present invention.

FIG. 6 is a cross-sectional view of another embodiment of a semiconductor device which is a high voltage MOS transistor of the present invention.

FIG. 7 is an enlarged cross-sectional view of the vicinity of the drain region of the semiconductor device of the high breakdown voltage MOS transistor of the present invention.

8A to 8D are cross-sectional views in order of the processes, showing a method for manufacturing a semiconductor device of a high voltage MOS transistor according to the present invention.

FIG. 9 is a cross-sectional view of a high breakdown voltage MISFET of the present invention.

FIG. 10 is a cross-sectional view of another embodiment of the high breakdown voltage MISFET of the present invention.

FIG. 11 is a cross-sectional view of another embodiment of the high breakdown voltage MISFET of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor integrated circuit including a high breakdown voltage MISFET of the present invention.

FIG. 13 is a cross-sectional view of another embodiment of the high breakdown voltage MISFET of the present invention.

FIG. 14 is a cross-sectional view of another embodiment of the high breakdown voltage MISFET of the present invention.

FIG. 15 is a cross-sectional view of another embodiment of the high breakdown voltage MISFET of the present invention.

FIG. 16A is a schematic block diagram showing a semiconductor integrated circuit device of Example 11 of the present invention. (B) shows Vin and V, which represent the operation of Vr in the eleventh embodiment of the present invention.
It is a graph showing the relationship of out.

FIG. 17 is a detailed circuit diagram showing a semiconductor integrated circuit device of Example 11 of the present invention.

FIG. 18 is a plan view showing a semiconductor integrated circuit device of Example 11 of the present invention.

FIG. 19A is a schematic block diagram showing a portion of an output transistor M6 according to an eleventh embodiment of the present invention.
(B) is an output transistor M6 of the eleventh embodiment of the present invention
5 is a graph showing the value of VGS with respect to the output current Iout of FIG.

FIG. 20 shows Vin, Vout, VDS, VGD, VGS, Iou of the output transistors of the eleventh embodiment of the present invention.
9 is a table showing values in the case of t.

FIG. 21 is a schematic sectional view showing an output transistor (PMOS) of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 22 is a chip for explaining the Vr semiconductor integrated circuit device according to the eleventh embodiment of the present invention, in which the gate insulating film thickness of the output transistor is changed to obtain Vr of 24V rating and 0.5A output. It is a graph showing a size.

FIG. 23 is a graph for explaining the Vr semiconductor integrated circuit device of the eleventh embodiment of the present invention, showing how far the output current can be obtained with a constant 24V rating and a 1 mm □ chip size.

FIG. 24 is a schematic cross-sectional view showing the relationship between PMOS and NMOS of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 25 is a graph showing a change in the protrusion length of the PMOS / drain low-concentration layer from the high-concentration layer and the distance between the FD drain and the field dope for element isolation in the semiconductor integrated circuit device according to the eleventh embodiment of the present invention. It is a graph showing the junction breakdown voltage from FD drain to field dope for element isolation.

FIG. 26 is a diagram showing a case where the protruding length of the NMOS / drain low-concentration layer from the high-concentration layer and the distance between the FD drain and the field isolation for element isolation are changed in the semiconductor integrated circuit device according to the eleventh embodiment of the present invention. It is a graph showing the junction breakdown voltage from FD drain to field dope for element isolation.

FIG. 27 is a schematic sectional view showing a Vr semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 28 is a schematic cross-sectional view showing a Vr semiconductor integrated circuit device of the thirteenth embodiment of the present invention.

FIG. 29 is a sectional view in order of the manufacturing steps of the output transistor having the ONO structure and the other transistors of the fourteenth embodiment of the present invention.

FIG. 30A is a schematic sectional view showing a semiconductor integrated circuit device of a voltage regulator according to a fourteenth embodiment of the present invention. (B) is a table | surface which shows the film thickness structure for every transistor of the ONO structure of the 14th Example of this invention.

FIG. 31 is a gate insulating film thickness (gate Tox) and gm under a constant condition in a general MOS transistor.
(This is called the so-called transconductance of MOS, the K value or the drain current drivability).
2 is a graph showing the relationship between the above relationship and the operating rated voltage at the same time.

[Explanation of symbols]

1 P-type substrate 2 Field oxide film (insulating film) 3 Gate oxide film (insulating film) 5 N ⁺ type source region 6 N ± type drain region 7 N ⁺ type drain region 13 Gate electrode 14 Low breakdown voltage MOS transistor 15 High breakdown voltage MOS Transistor

Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical location 7514-4M H01L 29/78 301 G (31) Claim number for priority right Japanese Patent Application No. 5-267596 (32) 5 (1993) October 26 (33) Priority claiming country Japan (JP) (72) Inventor Jun Koyamauchi 6-31-1, Kameido, Koto-ku, Tokyo Seiko Electronics Co., Ltd. (72) Inventor Ishii Kazutoshi Seiko Denshi Kogyo Co., Ltd. 63-11-1 Kameido, Koto-ku, Tokyo

Claims (13)

[Claims] 1. A source / drain region of a second conductivity type provided on a surface of a semiconductor region of the first conductivity type and spaced from each other, and a channel of the semiconductor region between the source region and the drain region. In a high breakdown voltage insulated gate field effect transistor comprising a formation region and a gate insulating film and a gate electrode provided on the channel formation region, the gate insulating film is an insulating film having a film thickness of 100 Å to 200 Å In addition, the surface impurity concentration of the drain region which overlaps with the gate electrode via the gate insulating film is 5 × 10 ¹⁶
atoms / cm ³ to 5 × 10 ¹⁸ atoms / cm ³
A high breakdown voltage insulated gate field effect transistor characterized in that 2. A source / drain region of a second conductivity type which is provided on the surface of the semiconductor region of the first conductivity type at a distance from each other, and a channel of the semiconductor region between the source region and the drain region. Region, a drain region having a low concentration provided in a part of the drain region in contact with the channel formation region, a gate insulating film provided on the channel formation region, and a drain region having a low concentration A high breakdown voltage insulating gate type field effect transistor comprising a high breakdown voltage insulating film thicker than the gate insulating film provided on the gate insulating film and a gate electrode provided on the gate insulating film and the high breakdown voltage insulating film, A high breakdown voltage insulated gate field effect transistor, characterized in that the gate insulating film is an insulating film having a film thickness between 100Å and 200Å. 3. A source / drain region of a second conductivity type provided on the surface of a semiconductor region of the first conductivity type at a distance from each other, and a first channel between the source region and the drain region. A formation region, a second channel formation region, a first gate electrode provided on the first channel formation region connected to the source region via a first gate insulating film, and the first channel electrode. On the second channel region provided between the drain region and the channel region of
A second gate electrode is provided via a second gate insulating film, and the thickness of one of the first gate insulating film and the second gate insulating film is 200 Å or less. A high breakdown voltage insulated gate field effect transistor, wherein the second gate electrode is electrically connected to the same potential through the drain region and the drain electrode. 4. A high withstand voltage insulated gate field effect transistor, comprising a high withstand voltage insulated gate field effect transistor and a low withstand voltage insulated gate field effect transistor provided on the same semiconductor region. A high withstand voltage semiconductor integrated circuit device, wherein the gate insulating film of the low withstand voltage insulated gate field effect transistor has the same film thickness between 100 and 200Å. 5. A semiconductor integrated circuit device characterized in that a thickness of a gate insulating film of a load driving MOS transistor is at least partially thinner than a thickness of the gate insulating film of another transistor on the same substrate. 6. The semiconductor integrated circuit device according to claim 5, wherein the gate insulating film is composed of several kinds of materials to form a multilayer structure. 7. The semiconductor integrated circuit device according to claim 5, having a structure in which the gate insulating film on the drain region at the gate end is partially thickened. 8. The semiconductor integrated circuit device according to claim 7, wherein the impurity region forming the drain region comprises a high concentration region and a low concentration region. 9. The high concentration region of the impurity region forming the drain region is the low concentration region and has a width of 1.0.
8. The semiconductor integrated circuit device according to claim 7, wherein the periphery is surrounded by .mu.m or more. 10. The impurity region forming the drain of the breakdown voltage insulated gate field effect transistor and the impurity region of opposite conductivity type for element isolation are adjacent to each other with a certain interval. Semiconductor integrated circuit device. 11. The semiconductor integrated circuit device according to claim 1, wherein the impurity region of the drain has a region having a low concentration as a double structure. 12. An impurity region forming a drain of a high breakdown voltage insulated gate field effect transistor and an impurity region of opposite conductivity type for element isolation are adjacent to each other with a certain interval. The semiconductor integrated circuit device described. 13. Gate oxide film, channel dope, Si
A method of manufacturing a semiconductor device, comprising forming a gate insulating film having a multilayer structure in the order of an N film and a CVD oxide film.