CN113451428A

CN113451428A - Double-half floating gate photoelectric memory and preparation process thereof

Info

Publication number: CN113451428A
Application number: CN202110720224.XA
Authority: CN
Inventors: 丁士进; 裴俊翔; 吴小晗; 张卫
Original assignee: Fudan University; Shanghai IC Manufacturing Innovation Center Co Ltd
Current assignee: Fudan University; Shanghai IC Manufacturing Innovation Center Co Ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2021-09-28
Anticipated expiration: 2041-06-28
Also published as: CN113451428B

Abstract

The invention provides a double-semi-floating gate photoelectric memory, which comprises a grid electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active channel layer, a source electrode and a drain electrode, wherein the grid electrode is connected with the charge blocking layer; the charge trapping layer comprises a first charge trapping layer and a second charge trapping layer, the thickness of the charge tunneling layer arranged on the upper surface of the first charge trapping layer is larger than that of the charge tunneling layer arranged on the upper surface of the second charge trapping layer, so that the double-half floating gate photoelectric memory can have an electric pulse programming characteristic under the condition of no monochromatic light illumination, the first charge trapping layer and the second charge trapping layer generate different threshold voltages under different wavelength illumination, the threshold voltages generated along with the increase of the grid pulse voltage are increased accordingly, and the double-half floating gate photoelectric memory has a multi-level storage characteristic, a better data retention characteristic, a better programming tolerance and an erasing tolerance. The invention also provides a preparation process of the double-half floating gate photoelectric memory.

Description

Double-half floating gate photoelectric memory and preparation process thereof

Technical Field

The invention relates to the technical field of semiconductor storage, in particular to a double-half floating gate photoelectric memory and a preparation process thereof.

Background

Compared with the traditional silicon-based material, the perovskite material has the advantages of direct band gap, high absorption coefficient, low energy loss, simple preparation process and the like, so that the perovskite material is widely concerned in various fields, such as solar cells, photoelectric detectors, photoelectric memories and the like. Common preparation methods of all-inorganic perovskite thin films are mainly divided into solution methods and vacuum methods. Different preparation processes usually select different precursors, different ligand solvents, different crystallization methods and post-treatments, etc., which in turn may affect the composition of the perovskite. Therefore, the selection of a proper perovskite preparation method is particularly important for improving the crystallization quality of the prepared film. Generally, solution processes have the advantages of simple operation and ease of preparation, and energy costs, especially for perovskite materials requiring low temperature annealing, are generally lower; the disadvantages are many parameters involved, it is difficult to control the scale and repeatability of the parameters strictly, and the inability to define patterning, which is incompatible with microelectronic processes. Vacuum thermal evaporation is a mature technology used in the field of coating, which can realize easy deposition of multiple thin films on a large area, and the deposited thin films have good uniformity and flatness. The vacuum thermal evaporation coating can accurately control the thickness of the film, and the repeatability of the film is high. For example, Cancan Tian et al prepared fully inorganic CsPbBr by CVD method₃The perovskite nanocrystal shows better cubic phase and optical performance, and the on-off ratio of the device is 10⁵. However, since the CVD method is commonly used for large-area production and the deposition thickness and ratio cannot be precisely controlled, CsPbBr prepared as described above₃The size of the perovskite nano crystal is 10-50 mu m, which is not beneficial to the integration of micro-nano devices.

The use of all-inorganic halogen perovskites in optoelectronic memory devices has also been rapidly developed based on the excellent photoelectric conversion properties of the perovskites, e.g., YanWang et al, CsPbBr₃Quantum dots (floating gate layer), PMMA (tunneling insulation layer) and pentacene (channel material) are transferred layer by layer to SiO₂On the/Si substrate, a three-terminal floating gate type photoelectric memory is constructed. Due to the total inorganic CsPbBr₃The quantum dot has narrow exciton binding energy, excellent light absorption performance, high carrier mobility, long carrier service life and high stability, and is one of ideal floating gate materials for constructing photoelectric memory. Pentacene and CsPbBr₃The quantum dots form II type heterojunction, which is beneficial to the separation of excitons at the interface and can realize the photoelectric storage performance of optical writing and electric erasing. Although the device has 10⁵Switching ratio and an erase window of 6V, but erase voltages up to-50V.

Therefore, there is a need to provide a novel dual-half floating gate photo memory and a manufacturing process thereof to solve the above-mentioned problems in the prior art.

Disclosure of Invention

The invention aims to provide a double-half floating gate photoelectric memory and a preparation process thereof, so that the double-half floating gate photoelectric memory can have an electric pulse programming characteristic under the condition of no monochromatic light illumination, different threshold voltages are generated by a first charge trapping layer and a second charge trapping layer under the illumination of different wavelengths, the threshold voltages generated along with the increase of the gate pulse voltage are increased, the double-half floating gate photoelectric memory has a multi-level storage characteristic, and a larger storage window is formed between different storage states, so that the problems of misreading or data crosstalk and the like can be avoided when the different storage states of a device are read, and meanwhile, the better data retention characteristic, the better programming tolerance and the better erasing tolerance are realized.

In order to achieve the above object, the dual-half floating gate photoelectric memory of the present invention comprises:

a gate electrode;

the charge blocking layer is arranged on the upper surface of the grid electrode;

a charge trapping layer including a first charge trapping layer disposed on an upper surface of a portion of the charge blocking layer and a second charge trapping layer disposed on an upper surface of another portion of the charge blocking layer;

a charge tunneling layer disposed on an upper surface of the first charge-trapping layer and an upper surface of the second charge-trapping layer, the charge tunneling layer disposed on the upper surface of the first charge-trapping layer having a thickness greater than a thickness of the charge tunneling layer disposed on the upper surface of the second charge-trapping layer;

an active channel layer disposed on an upper surface of the charge tunneling layer; and the number of the first and second groups,

and the source electrode and the drain electrode are respectively arranged on two sides of the active channel layer and cover part of the active channel layer.

The double-half floating gate photoelectric memory has the beneficial effects that: the charge trapping layer comprises a first charge trapping layer and a second charge trapping layer, the first charge trapping layer is arranged on the upper surface of one part of the charge blocking layer, the second charge trapping layer is arranged on the upper surface of the other part of the charge blocking layer, the charge tunneling layer is arranged on the upper surfaces of the first charge trapping layer and the second charge trapping layer, the thickness of the charge tunneling layer arranged on the upper surface of the first charge trapping layer is larger than that of the charge tunneling layer arranged on the upper surface of the second charge trapping layer, so that when the grid voltage is low, the thinner side of the charge tunneling layer, namely the side of the second charge trapping layer, can generate F-N tunneling to generate the threshold voltage, and when the grid voltage is high, the potential barriers on the two sides of the first charge trapping layer and the second charge trapping layer bend under the grid voltage stress, and F-N tunneling can occur, so that the threshold voltage of the device is further increased and tends to a new saturation state, namely the double-half floating gate photoelectric memory has the electrical pulse programming characteristic when no monochromatic light illumination condition exists; under different wavelength illumination conditions, the first charge trapping layer and the second charge trapping layer respectively absorb different wavelength illumination to generate electron-hole pairs, so that when the electric programming and erasing operations are realized, the first charge trapping layer and the second charge trapping layer generate different threshold voltages under different wavelength illumination, and the threshold voltages generated along with the increase of the grid pulse voltage are increased; when different grid voltages and illumination wavelengths are changed, the double-half floating gate photoelectric memory has the multi-level storage characteristic, and a larger storage window is arranged between different storage states, so that the problems of misreading or data crosstalk and the like can be avoided when different storage states of a reading device are read.

Preferably, the first charge trapping layer and the second charge trapping layer are each formed using perovskite quantum dots, and a band gap width of a constituent material of the first charge trapping layer and a band gap width of a constituent material of the second charge trapping layer are different from each other. The beneficial effects are that: the charge loss can be effectively inhibited, and the data storage time is prolonged.

Preferably, the thickness of the second charge trapping layer is greater than the thickness of the first charge trapping layer, and a difference between the thickness of the first charge trapping layer and the thickness of the second charge trapping layer is less than 5 nm. The beneficial effects are that: the method is favorable for improving the tunneling probability of electrons, and further improves the programming efficiency and the erasing efficiency of the double-half floating gate photoelectric memory.

Preferably, the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are both less than 20nm, and the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are not equal. The beneficial effects are that: the quantum dot is formed, and the data retention characteristic of the double-half floating gate photoelectric memory is improved.

Preferably, the charge tunneling layer disposed on the upper surface of the second charge trapping layer has a thickness of 5 to 7 nm. The beneficial effects are that: it is avoided that the charge tunneling layer is too thick and that electrons cannot pass through the charge tunneling layer to the second charge trapping layer at low voltages.

Preferably, the charge tunneling layer disposed on the upper surface of the first charge trapping layer has a thickness of 10-15 nm. The beneficial effects are that: such that at high voltages, electrons can pass through the charge tunneling layer to the first charge trapping layer.

Preferably, the active channel layer is made of any one of amorphous indium gallium zinc oxide and zinc oxide.

More preferably, the structural formula of the perovskite quantum dot is CsPbX_nY_mZ_pThe X, the Y and the Z are Br element, I element and Cl element respectively, the values of n, m and p are any one of 0, 1, 2 and 3, and the sum of n, m and p is equal to 3. The beneficial effects are that: the CsPbX_nY_mZ_pThe perovskite quantum dots have high light absorption coefficient and are stable at normal temperature.

Preferably, the charge tunneling layer includes a first charge tunneling layer and a second charge tunneling layer, a portion of the first charge tunneling layer is disposed between the charge blocking layer and the second charge trapping layer, another portion of the first charge tunneling layer is disposed on the upper surface of the first charge trapping layer, and the second charge tunneling layer is disposed on the upper surface of the second charge trapping layer and the upper surface of the first charge tunneling layer. The beneficial effects are that: the preparation process is simple and convenient, and can save time investment and cost investment.

Preferably, the double semi-floating gate photo memory further comprises an auxiliary charge blocking layer disposed between the charge blocking layer and the second charge trapping layer, and the auxiliary charge blocking layer is disposed adjacent to the first charge trapping layer.

Further preferably, the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are both less than 20nm, and the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are equal or unequal. The beneficial effects are that: the quantum dot is formed, and the data retention characteristic of the double-half floating gate photoelectric memory is improved.

Further preferably, the thickness of the first charge tunneling layer and the thickness of the second charge tunneling layer are equal or unequal.

Preferably, the double-half floating gate photoelectric memory further comprises a substrate, and the gate is arranged on the upper surface of the substrate. The beneficial effects are that: the substrate is arranged, so that the integration of subsequent components is facilitated in industrial preparation, and electric leakage can be effectively avoided.

Preferably, the invention also provides a preparation process of the double-half floating gate photoelectric memory, which comprises the following steps:

s1: forming the grid electrode;

s2: forming the charge blocking layer on the upper surface of the gate;

s3: forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer, forming a charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer, and making the thickness of the charge tunneling layer disposed on the upper surface of the first charge trapping layer larger than the thickness of the charge tunneling layer disposed on the upper surface of the second charge trapping layer;

s4: forming the active channel layer on the charge tunneling layer;

s5: and respectively forming the source electrode and the drain electrode on two sides of the active channel layer, and enabling the source electrode and the drain electrode to cover part of the active channel layer.

Preferably, in step S3, the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer, and the step of forming the charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer includes:

s31: forming the first charge trapping layer on a portion of the upper surface of the charge blocking layer;

s32: forming a first charge tunneling layer on an upper surface of the first charge trapping layer and an upper surface of another portion of the charge blocking layer;

s33: forming the second charge trapping layer on an upper surface of the first charge tunneling layer adjacent to the charge blocking layer;

s34: a second charge tunneling layer is formed on an upper surface of the second charge trapping layer and an upper surface of another portion of the first charge tunneling layer.

Preferably, in the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer in step S3, the first charge trapping layer and the second charge trapping layer are thermally evaporated by a two-step sequential method. The beneficial effects are that: by adopting a two-step sequential thermal evaporation method, the proportion and the deposition thickness of the precursor can be accurately controlled at a lower temperature, the charge loss can be effectively inhibited, and the data storage time is prolonged.

Drawings

FIG. 1 is a cross-sectional view of a dual semi-floating gate photo memory device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of a dual semi-floating gate photo memory device according to a second embodiment of the present invention;

FIG. 3 is a cross-sectional view of a dual semi-floating gate optoelectronic memory according to a third embodiment of the present invention;

FIG. 4 is a flow chart of a method for fabricating a dual half floating gate photo memory device according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the transfer characteristic curves of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the embodiment of the invention after programming in the initial state and at different voltages;

FIG. 6 is a schematic diagram showing a relationship curve between a programming window and a gate pulse voltage of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory under different wavelengths of light according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of programming characteristic curves of devices corresponding to different wavelengths of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a low gate pulse voltage in the embodiment of the invention;

FIG. 8 is a graph schematically illustrating the programming window and the illumination wavelength of the device corresponding to different low gate pulse voltages of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the embodiment of the present invention;

FIG. 9 is a schematic diagram of programming characteristic curves of devices corresponding to different wavelengths of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a high gate pulse voltage in the embodiment of the invention;

FIG. 10 is a graph schematically illustrating the programming window and the illumination wavelength of the device corresponding to different high gate pulse voltages of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the embodiment of the present invention;

FIG. 11 is a schematic diagram showing a relationship curve between an erase window and a gate pulse voltage of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-electric memory under different wavelengths of light according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of an erasing characteristic curve of a device corresponding to different wavelengths of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a low gate pulse voltage in the embodiment of the invention;

FIG. 13 is a schematic diagram showing a relationship curve between an erasing window and an illumination wavelength of a device corresponding to different low gate pulse voltages of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-electric memory in an embodiment of the present invention;

FIG. 14 is a schematic diagram of an erasing characteristic curve of a device corresponding to different wavelengths of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a high gate pulse voltage in the embodiment of the invention;

FIG. 15 is a schematic diagram showing a relationship curve between an erasing window and an illumination wavelength of a device corresponding to different high gate pulse voltages of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-electric memory in an embodiment of the present invention;

FIG. 16 is a schematic diagram of the storage characteristics of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory under different gate pulse voltages and different illumination wavelengths in the embodiment of the invention;

FIG. 17 is a schematic diagram of data retention characteristics of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory in an embodiment of the present invention;

FIG. 18 is a schematic diagram of the programming endurance curve and the erasing endurance curve of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

In order to overcome the problems in the prior art, the embodiment of the invention provides a double-half floating gate photoelectric memory and a preparation process thereof.

Fig. 1 is a structural cross-sectional view of a dual semi-floating gate photo memory according to a first embodiment of the invention.

In some embodiments of the present invention, referring to fig. 1, the dual-half floating gate photoelectric memory comprises a gate 1, a charge blocking layer 2, a charge trapping layer (not labeled in the figure), a charge tunneling layer 5, an active channel layer 6, a source electrode 7 and a drain electrode 8; the charge blocking layer 2 is disposed on the upper surface of the gate electrode 1, the charge trapping layer (not labeled) includes a first charge trapping layer 3 and a second charge trapping layer 4, the first charge trapping layer 3 is disposed on a portion of the upper surface of the charge blocking layer 2, and the second charge trapping layer 4 is disposed on another portion of the upper surface of the charge blocking layer 2; the charge tunneling layer 5 is disposed on the upper surface of the first charge-trapping layer 3 and the upper surface of the second charge-trapping layer 4, and the thickness of the charge tunneling layer 5 disposed on the upper surface of the first charge-trapping layer 3 is greater than the thickness of the charge tunneling layer 5 disposed on the upper surface of the second charge-trapping layer 4; the active channel layer 6 is arranged on the upper surface of the charge tunneling layer 5; the source electrode 7 and the drain electrode 8 are respectively disposed on two sides of the active channel layer 6 and cover a portion of the active channel layer 6. Wherein the arrangement positions of the source electrode 7 and the drain electrode 8 on both sides of the active channel layer 6 are exchangeable.

In some embodiments of the present invention, the first charge trapping layer and the second charge trapping layer are both made of perovskite quantum dots, and a band gap width of a constituent material of the first charge trapping layer and a band gap width of a constituent material of the second charge trapping layer are different.

In some embodiments of the present invention, a constituent material of the active channel layer is any one of amorphous indium gallium zinc oxide (a-IGZO) and zinc oxide (ZnO).

In some embodiments of the invention, the perovskite quantum dot has a structural formula of CsPbX_nY_mZ_pX, Y and Z are Br, I and Cl respectively, the values of n, m and p are any one of 0, 1, 2 and 3, the sum of n, m and p is equal to 3, and CsPbX_nY_mZ_pThe perovskite quantum dots have high light absorption coefficient and are stable at normal temperature.

In some embodiments of the invention, the first charge trapping layer comprises CsPbCl₂Br, the composition material of the second charge trapping layer is CsPbBr₃CsPbCl as described₂Br and CsPbBr₃The optical response waveband of the second charge trapping layer is stable at normal temperature, and the optical response waveband of the second charge trapping layer can be prevented from being overlapped with the optical response waveband of the a-IGZO channel material.

Some embodiments of the inventionIn an embodiment, the first charge trapping layer comprises CsPbI₂Br, the composition material of the second charge trapping layer is CsPbI₃。

In some embodiments of the present invention, the gate electrode is made of at least one of heavily doped p-type single crystal silicon, ITO, FTO, AZO, TiN, TaN, Cr, Au, Ti, Au, Ni, Au, Al, and Mo.

In some embodiments of the present invention, the charge blocking layer is made of Al₂O₃、SiO₂、HfO₂、ZrO₂HfAlO, ZrAlO and HfZrO₂Any one of them.

In some embodiments of the present invention, the charge tunneling layer is made of Al₂O₃、SiO₂、HfO₂、ZrO₂HfAlO, ZrAlO and HfZrO₂In any one of the above embodiments, a constituent material of the charge tunneling layer is the same as or different from a constituent material of the charge blocking layer.

In some embodiments of the present invention, the source electrode and the drain electrode are made of at least one of ITO, FTO, AZO, TiN, TaN, Cr, Au, Ti, Au, Ni, Au, Al, and Mo.

In some embodiments of the present invention, referring to fig. 1, the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the dual-half floating gate photo memory shown in fig. 1 are both less than 20nm, which is beneficial for forming quantum dots and improving the data retention characteristics of the dual-half floating gate photo memory, and the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the dual-half floating gate photo memory shown in fig. 1 are not equal, and the thickness of the second charge trapping layer 4 is greater than the thickness of the first charge trapping layer 3, so that the thickness of the charge tunneling layer 5 disposed on the upper surface of the first charge trapping layer 3 is greater than the thickness of the charge tunneling layer 5 disposed on the upper surface of the second charge trapping layer 4.

In some embodiments of the present invention, a difference between a thickness of the first charge trapping layer and a thickness of the second charge trapping layer is less than 5nm, which is beneficial to improving an electron tunneling probability, and further improving programming efficiency and erasing efficiency of the double-half floating gate photoelectric memory.

In some embodiments, the charge tunneling layer disposed on the top surface of the second charge-trapping layer has a thickness of 5-7nm, so as to avoid the charge tunneling layer being too thick for electrons to reach the second charge-trapping layer through the charge tunneling layer at low voltages.

In some embodiments, the charge tunneling layer disposed on the top surface of the first charge trapping layer has a thickness of 10-15nm, such that at high voltages, electrons can pass through the charge tunneling layer to the first charge trapping layer.

In some embodiments of the invention, the thickness of the charge blocking layer ranges from 30nm to 60nm, which is beneficial to realizing efficient erasing operation of the double-half floating gate photoelectric memory and simultaneously maintaining good data retention characteristics.

In some embodiments of the invention, the thickness range of the active channel layer is 20-60nm, which is beneficial to the double-half floating gate photoelectric memory to realize larger on-state current and form good digital programming effect and reliability.

In some embodiments of the invention, the double-half floating gate photoelectric memory further comprises a substrate, the grid electrode is arranged on the upper surface of the substrate, and the substrate is arranged, so that in industrial preparation, the integration of subsequent components is facilitated, and electric leakage can be effectively avoided.

In some embodiments of the present invention, a metal gate is disposed between the substrate and the charge blocking layer, and the substrate is made of a low resistance silicon wafer, a high resistance silicon wafer, glass, or a polymer.

In other specific embodiments of the present invention, the substrate and the gate are made of heavily doped p-type single crystal silicon, and the gate has a resistivity of 0.001 to 0.005 Ω · cm.

Fig. 2 is a structural cross-sectional view of a dual semi-floating gate photo memory according to a second embodiment of the invention.

In some embodiments of the present invention, referring to fig. 1 and 2, fig. 2 differs from fig. 1 in that: the double semi-floating gate photo memory device of fig. 2 further comprises an auxiliary charge blocking layer 9, the auxiliary charge blocking layer 9 being disposed between the charge blocking layer 2 and the second charge trapping layer 4, and the auxiliary charge blocking layer 9 being disposed adjacent to the first charge trapping layer 3.

In some embodiments of the present invention, referring to fig. 2, fig. 2 further differs from fig. 1 in that: the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the double semi-floating gate photoelectric memory shown in fig. 2 are both less than 20nm, which is beneficial to forming quantum dots, improving the data retention property of the double semi-floating gate photoelectric memory, and the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the double half floating gate photo memory shown in figure 2 are equal or unequal, because the second charge trapping layer 4 is disposed on the auxiliary charge blocking layer 9 in the dual half floating gate photo memory of figure 2, it is possible to realize that the thickness of the charge tunneling layer 5 disposed on the upper surface of the first charge trapping layer 3 is larger than the thickness of the charge tunneling layer 5 disposed on the upper surface of the second charge trapping layer 4 even if the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 are equal.

In some embodiments of the present invention, the auxiliary charge blocking layer 9 may be formed of the same or different material as the charge tunneling layer 5.

In some embodiments of the present invention, the auxiliary charge blocking layer 9 is made of the same or different material as the charge blocking layer 2.

FIG. 3 is a cross-sectional view of a dual half-floating gate photo-memory according to a third embodiment of the present invention.

In some embodiments of the present invention, referring to fig. 1 and 3, fig. 3 differs from fig. 1 in that: the charge tunneling layer (not labeled) in the dual-half floating gate photo memory shown in fig. 3 includes a first charge tunneling layer 51 and a second charge tunneling layer 52, a portion of the first charge tunneling layer 51 is disposed between the charge blocking layer 2 and the second charge trapping layer 4, another portion of the first charge tunneling layer 51 is disposed on the upper surface of the first charge trapping layer 3, the second charge tunneling layer 52 is disposed on the upper surface of the second charge trapping layer 4 and the upper surface of the first charge tunneling layer 51, that is, the first charge tunneling layer 51 is z-shaped, and is disposed along the upper surface of the first charge trapping layer 3, the adjacent surface of the first charge trapping layer 3 and the second charge trapping layer 4, and the lower surface of the second charge trapping layer 4, so that the fabrication process is simple and convenient, and the time investment and the cost investment can be saved, wherein the first charge tunneling layer 51 disposed between the charge blocking layer 2 and the second charge trapping layer 4 serves as an auxiliary charge blocking layer.

In some embodiments of the present invention, referring to fig. 3, fig. 3 further differs from fig. 1 in that: the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the double semi-floating gate photoelectric memory shown in fig. 3 are both less than 20nm, which is beneficial to forming quantum dots, improving the data retention property of the double semi-floating gate photoelectric memory, and the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 in the double half floating gate photo memory shown in figure 3 are equal or unequal, because the second charge trapping layer 4 is disposed on a portion of the upper surface of the first charge tunneling layer 51 in the dual half floating gate photo memory of figure 3, it is possible to realize that the thickness of the charge tunneling layer 5 disposed on the upper surface of the first charge trapping layer 3 is larger than the thickness of the charge tunneling layer 5 disposed on the upper surface of the second charge trapping layer 4 even if the thickness of the first charge trapping layer 3 and the thickness of the second charge trapping layer 4 are equal.

In some embodiments of the present invention, the thickness of the first charge tunneling layer 51 and the thickness of the second charge tunneling layer 52 are equal or unequal.

In some embodiments of the present invention, the composition material of the first charge tunneling layer 51 and the composition material of the second charge tunneling layer 52 are the same or different.

In some embodiments of the present invention, the radial lengths of the first charge trapping layer and the second charge trapping layer are equal or different, and the sum of the radial length of the first charge trapping layer and the radial length of the second charge trapping layer is less than or equal to the radial length of the charge blocking layer, and the projected areas of the second charge trapping layer and the first charge trapping layer on the upper surface of the charge blocking layer are not overlapped.

In the embodiment of the present invention, the thickness is a maximum length of the corresponding level in an axial direction, the radial length is a maximum length of the corresponding level in a radial direction, the axial direction is a direction shown as a in fig. 1, and the radial direction is a direction perpendicular to the axial direction.

Fig. 4 is a flowchart of a method for manufacturing a dual half floating gate photo memory according to an embodiment of the invention.

In some embodiments of the present invention, referring to fig. 4, the process for manufacturing the double-half floating gate photoelectric memory comprises the following steps:

s1: forming the grid electrode;

s2: forming the charge blocking layer on the upper surface of the gate;

s4: forming the active channel layer on the charge tunneling layer;

In some embodiments of the present invention, in the step S3, the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer, and the step of forming the charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer includes the following steps, referring to fig. 3:

s31: forming the first charge trapping layer 3 on a part of the upper surface of the charge blocking layer 2;

s32: forming a first charge tunneling layer 51 on an upper surface of the first charge trapping layer 3 and an upper surface of another portion of the charge blocking layer 2;

s33: forming the second charge trapping layer 4 on the upper surface of the first charge tunneling layer 51 adjacent to the charge blocking layer 2, such that the portion of the first charge tunneling layer 51 is disposed between the charge blocking layer 2 and the second charge trapping layer 4, so as to serve as an auxiliary charge blocking layer;

s34: a second charge tunneling layer 52 is formed on the upper surface of the second charge trapping layer 4 and the upper surface of another portion of the first charge tunneling layer 51.

In other embodiments of the present invention, in step S3, the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer, and the step of forming the charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer includes the following steps, referring to fig. 1:

s301: forming the first charge trapping layer 3 on a part of the upper surface of the charge blocking layer 2;

s302: forming the second charge trapping layer 4 on the other part of the upper surface of the charge blocking layer 2, and making the thickness of the second charge trapping layer 4 larger than that of the first charge trapping layer 3;

s303: providing a primary charge tunneling layer on an upper surface of the first charge-trapping layer 3 and an upper surface of the second charge-trapping layer 4;

s304: and etching the original charge tunneling layer by an etching process so that the upper surface of the original charge tunneling layer is positioned at the same horizontal plane to form the charge tunneling layer 5.

In still other embodiments of the present invention, in the step S3, the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer, and the step of forming the charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer includes the following steps, referring to fig. 2:

s311: forming the first charge trapping layer 3 on a part of the upper surface of the charge blocking layer 2;

s312: forming an auxiliary charge blocking layer 9 on the other part of the upper surface of the charge blocking layer 2;

s313: forming the second charge trapping layer 4 on the upper surface of the auxiliary charge blocking layer 9;

s314: providing a primary charge tunneling layer on an upper surface of the first charge-trapping layer 3 and an upper surface of the second charge-trapping layer 4;

s315: and etching the original charge tunneling layer by an etching process so that the upper surface of the original charge tunneling layer is positioned at the same horizontal plane to form the charge tunneling layer 5.

In some embodiments of the present invention, in step S312, an original auxiliary charge blocking layer is formed on another portion of the upper surface of the charge blocking layer 2 and the upper surface of the first charge trapping layer 3; and etching away the original auxiliary charge blocking layer on the upper surface of the first charge trapping layer 3 by an etching process to form the auxiliary charge blocking layer 9 on the other part of the upper surface of the charge blocking layer 2.

In other embodiments of the present invention, in step S312, a mask is used to deposit and form the auxiliary charge blocking layer 9 on another portion of the upper surface of the charge blocking layer 2.

In some embodiments of the present invention, in the step of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer in step S3, the first charge trapping layer and the second charge trapping layer are thermally evaporated by a two-step sequential method.

In some embodiments of the invention, the CsPbBr is prepared by thermal evaporation in a two-step sequential method₃A perovskite quantum dot comprising the steps of: reacting PbBr₂(367.01g/mol) and CsBr (212.81g/mol) were added as 1.1: 1, and placing the mixture into a beam source furnace. And putting the cleaned standby substrate into a base plate, setting the rotating speed of the base plate to be 10r/min, keeping the baffle of the base plate closed, closing the cavity and starting vacuumizing. When the pressure of the cavity is lower than 7 x 10^-4Pa, turn on PbBr₂Heating the beam source furnace, setting the heating rate to be 8 ℃/min, simultaneously observing the real-time evaporation rate displayed by the film thickness instrument, and waiting for PbBr₂When the evaporation rate is stabilized at 0.1nm/s, the substrate baffle is opened, the baffle is closed immediately after deposition to the target thickness, and PbBr is closed₂And (4) heating of the beam source furnace. And when the real-time evaporation rate is 0, starting heating of the CsBr beam source furnace, opening the substrate baffle again when the evaporation rate of the CsBr is stabilized at 0.05nm/s, depositing to the target thickness, immediately closing the baffle, and closing the heating of the CsBr beam source furnace. And continuously vacuumizing until the real-time rate displayed by the film thickness meter is 0, opening the cavity, taking out the sample, putting the sample into a tube furnace, annealing for 30min at 200 ℃, and then putting the sample into a glove box for storage.

In some embodiments of the invention, CsPbCl is prepared by thermal evaporation in a two-step sequential process₂A Br perovskite quantum dot comprising the steps of: mixing PbCl₂(278.1g/mol) and CsBr (212.81g/mol) were measured as follows: 1, and placing the mixture into a beam source furnace. And putting the cleaned standby substrate into a base plate, setting the rotating speed of the base plate to be 10r/min, keeping the baffle of the base plate closed, closing the cavity and starting vacuumizing. When the pressure of the cavity is lower than 7 x 10^-4Pa, opening PbCl₂Heating the beam source furnace, setting the heating rate to be 8 ℃/min, and simultaneously observing the real-time evaporation rate displayed by the film thickness instrument until PbCl is treated₂When the evaporation rate of (2) stabilized at 0.1nm/s, the substrate shutter was opened, the substrate was deposited to the target thickness and immediately the shutter was closed, PbCl was closed₂And (4) heating of the beam source furnace. And when the real-time evaporation rate is 0, starting heating of the CsBr beam source furnace, opening the substrate baffle again when the evaporation rate of the CsBr is stabilized at 0.05nm/s, depositing to the target thickness, immediately closing the baffle, and closing the heating of the CsBr beam source furnace. And continuously vacuumizing until the real-time rate displayed by the film thickness meter is 0, opening the cavity, taking out the sample, putting the sample into a tube furnace, annealing for 30min at 200 ℃, and then putting the sample into a glove box for storage.

In some embodiments of the present invention, the process for preparing the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory in the double-half floating gate photoelectric memory comprises the following steps:

s100: cleaning a silicon wafer substrate, wherein a heavily doped p-type monocrystalline silicon wafer is used as a substrate of a device and is used as the grid, and the resistivity of the heavily doped p-type monocrystalline silicon wafer is 0.001-0.005 omega-cm; during cleaning, firstly, cleaning the silicon wafer by adopting a standard RCA process, then removing a natural oxide layer on the surface of the silicon wafer by using hydrofluoric acid, and finally drying for later use by using a dryer, wherein the RCA process is a common wet chemical cleaning method and is not repeated herein;

s101: growing an alumina charge barrier layer, whole Al, by atomic layer deposition₂O₃The charge blocking layer is uniformly deposited by 40nm from the bottom to the top of the surface of the silicon substrate in the same reaction cavity;

s102: thermal evaporation growth of CsPbCl₂The Br perovskite quantum dot charge trapping layer is formed on the alumina charge blocking layer by adopting the two-step sequential method to thermally evaporate CsPbCl with uniform growth thickness of about 10nm₂Br perovskite quantum dot is regarded as the first electric charge and trapped in the layer;

s103: growing a first alumina charge tunneling layer on the CsPbCl by atomic layer deposition₂Growing a layer of alumina with the thickness of about 5nm on the upper surface of the Br perovskite quantum dot charge trapping layer and the upper surface of the alumina charge blocking layer by using an atomic layer deposition technology to serve as a first charge tunneling layer;

s104: thermal evaporation growth CsPbBr₃A perovskite quantum dot charge trapping layer, and CsPbBr with the thickness of about 10nm is uniformly grown on the first alumina charge tunneling layer by adopting the two-step sequential method through thermal evaporation₃The perovskite quantum dots are used as a second charge trapping layer of the device, and the second charge trapping layer and the first charge trapping layer are not overlapped;

s105: growing a second alumina charge tunneling layer on the CsPbBr by atomic layer deposition₃Growing alumina with the thickness of 5nm on the upper surface of the perovskite quantum dot charge trapping layer and the upper surface of the first alumina charge tunneling layer by using an atomic layer deposition technology to serve as a second charge tunneling layer; at this time, the CsPbBr₃An alumina charge tunneling layer over the perovskite quantum dot charge trapping layer having only a second alumina charge tunneling layer with a thickness of about 5nm, and the CsPbCl₂The alumina charge tunneling layer above the Br perovskite quantum dot charge trapping layer comprises the first alumina charge tunneling layer and the second alumina charge tunneling layer, and the thickness is about 10 nm;

s106: growing an a-IGZO channel film by adopting physical vapor deposition and defining a channel pattern, firstly depositing the a-IGZO film with the thickness of 30nm on the second aluminum oxide charge tunneling layer by adopting a radio frequency magnetron sputtering method under the room temperature environment, and then defining the channel pattern by a hard mask method so as to form an a-IGZO active channel layer;

s107: and preparing a source electrode and a drain electrode by thermal evaporation, defining a source and drain electrode pattern by adopting a customized electrode mask, and then preparing an Au source electrode and an Au drain electrode by a thermal evaporation method, wherein the deposition thickness is about 100 nm. And thus, the preparation of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory is completed. Before electrical testing, the devices were annealed at 200 ℃.

FIG. 5 is a schematic diagram of the transfer characteristic curves of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the initial state and after programming at different voltages in the embodiment of the invention.

In the programming test, an untested fresh device is selected, then the source electrode and the drain electrode are kept grounded, the pulse programming test is continuously carried out for fixing the gate programming time, different programming voltages are changed, and a series of transfer characteristic curves of the device are obtained, as shown in fig. 5. The mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory gradually moves in parallel in the positive direction along with the increase of the programming voltage from 6V to 14V, the programming window is increased from 0.8V to 4.2V, and therefore the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory has the electric pulse programming characteristic under the condition of no monochromatic light illumination.

FIG. 6 is a graph showing a relationship curve between a programming window and a gate pulse voltage of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under different wavelengths of light in the embodiment of the invention.

FIG. 6 is a graph of the threshold voltage applied to the transfer characteristic curves for different wavelengthsVoltage extraction, then making relation graph of threshold voltage and grid pulse voltage under different wavelengths, programming condition is that fixed programming time is 200 mus, fixed illumination intensity is 1mw/cm²When the illumination wavelength is 625nm and 565nm, different gate voltages are changed, the transfer characteristic curve of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory almost coincides with that under a dark environment (In dark), and the threshold voltage is increased along with the increase of the gate pulse voltage. It is noted that when the pulse voltage is lower than 9.5V, the transfer characteristic curve of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory moves horizontally in the positive direction with the increase of the gate pulse programming voltage, the threshold voltage also gradually increases, and the threshold voltage gradually approaches to saturation of 1.1V. Because the energy band of the alumina charge tunneling layer is bent under the action of the gate pulse voltage, but because the gate pulse voltage is smaller at the moment, the electrons in the a-IGZO active channel layer are mainly in the CsPbBr₃An alumina charge tunneling layer at one side of the perovskite quantum dot charge trapping layer, namely the second alumina charge tunneling layer enters the CsPbBr through F-N tunneling₃The perovskite quantum dot charge trapping layer is further trapped by the defects. And the CsPbCl₂The thickness of the alumina charge tunneling layer on one side of the Br perovskite quantum dot charge trapping layer is thick, the lower grid voltage is not enough to enable the energy band of the alumina charge tunneling layer on the side to be greatly bent, and therefore, under the barrier height, electrons cannot penetrate through CsPbCl₂The first alumina charge tunneling layer and the second alumina charge tunneling layer are arranged on the Br perovskite quantum dot charge trapping layer side. However, when the gate voltage is higher than 9.5V, the threshold voltage of the device starts to increase gradually again and tends to be saturated newly, as shown in fig. 6, from 1.1V to 5V. Because the gate voltage is larger at this time, the CsPbBr is increased₃Perovskite quantum dot charge trapping layer and CsPbCl₂The energy bands of the alumina charge tunneling layers with different thicknesses above the two sides of the Br perovskite quantum dot charge trapping layer are greatly bent, and electrons in the a-IGZO active channel layer can tunnel from the alumina on the two sides in an F-N tunneling mode under the action of grid voltageCharge tunneling layer into the CsPbBr₃Perovskite quantum dot charge trapping layer and CsPbCl₂A Br perovskite quantum dot charge trapping layer. As the number of trapped electrons increases further, the threshold voltage of the device will continue to increase until it reaches a new saturation state.

When the illumination wavelength is 530nm and 490nm respectively, as shown in fig. 6, the threshold voltage of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory is gradually increased from 1V to 2.3V when the gate pulse voltage is increased from 5V to 9.5V; when the gate pulse voltage is increased from 9.5V to 16V, the threshold voltage of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory is increased from 2.3V to 6.5V. Because of the CsPbBr₃The perovskite quantum dot charge trapping layer can absorb monochromatic illumination at 530nm and 490nm and generate a large number of electron-hole pairs, and photo-generated electrons can be continuously absorbed by the CsPbBr under the action of gate voltage₃Defects in the perovskite quantum dot charge trapping layer are trapped, so that the threshold voltage of the device is increased, and the programming window is increased. Therefore, since the CsPbBr₃The perovskite quantum dot charge trapping layer can generate photoresponse in the wave band, and the threshold voltage of the device is larger under the same grid pulse voltage.

When the illumination wavelength is 430nm and 405nm respectively, the gate pulse voltage is increased from 5V to 9.5V, and the threshold voltage of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory is gradually increased from 1.1V to 2.4V; when the gate pulse voltage is increased from 9.5V to 16V, the threshold voltage of the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory is increased from 2.4V to 9V. It can be seen that when the pulse voltage is lower than 9.5V, the two quantum dots in the first charge trapping layer and the second charge trapping layer of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory can generate photoresponse, but only one side of the alumina charge tunneling layer, namely the CsPbBr, is thinner due to the lower gate voltage₃F-N tunneling can occur on one side of the perovskite quantum dot charge trapping layer. When the gate voltage is higher than 9.5V, the barriers of the alumina charge tunneling layers at the two sides of the device are bent under the gate voltage stress and are all bentSufficient F-N tunneling occurs so the threshold voltage of the device increases further and tends to a new saturation state. It is worth mentioning that CsPbBr is responsible₃And CsPbCl₂Both Br perovskite quantum dots can absorb illumination of the wave band to generate electron-hole pairs, and a large number of photo-generated electrons are captured by defects, so that the threshold voltage of the device is obviously higher than that of the device under the first two wave bands under the same grid voltage.

FIG. 7 is a schematic diagram of programming characteristic curves of devices corresponding to different wavelengths of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a low gate pulse voltage in the embodiment of the invention; FIG. 8 is a graph schematically illustrating the programming window and the illumination wavelength of the device corresponding to different low gate pulse voltages of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory in the embodiment of the present invention; FIG. 9 is a schematic diagram of programming characteristic curves of devices corresponding to different wavelengths of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a high gate pulse voltage in the embodiment of the invention; fig. 10 is a graph schematically illustrating a programming window and an illumination wavelength of a device corresponding to different high gate pulse voltages of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo memory in an embodiment of the invention.

Referring to fig. 7, when a gate pulse voltage of 8V is applied, the transfer characteristic curves of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory at different wavelengths are shown, and it can be seen that when the illumination wavelength is 625nm, the transfer characteristic curves of the device are almost the same as those without illumination, because the perovskite quantum dots do not respond to illumination at the wavelength; when the illumination wavelength is 530nm, the CsPbBr is added₃The perovskite quantum dots can absorb the energy of the wavelength to generate electron-hole pairs, and the photo-generated electrons are absorbed by the CsPbBr under the action of positive gate voltage₃And the defects of the perovskite quantum dot charge trapping layer are trapped, and photogenerated holes enter the a-IGZO active channel layer in an F-N tunneling mode, so that the threshold voltage of the device is increased, and the transfer characteristic curve moves towards the positive direction. When the illumination wavelength is 430nm, CsPbBr is added₃Perovskite quantum dots and CsPbCl₂All Br perovskite quantum dots can absorb the wavelengthEnergy, but due to the CsPbCl₂The thickness of the alumina charge tunneling layer on one side of the Br perovskite quantum dot charge trapping layer is thick, the grid voltage is low and is not enough to cause the tunneling of photo-generated holes into the a-IGZO active channel layer, and therefore the transfer characteristic curve hardly moves compared with that under the illumination of 530 nm.

Referring to fig. 8, the gate pulse voltages are selected to be 7V, 7.5V and 8V, respectively, and when the illumination wavelengths are 625nm and 565nm, the threshold voltage of the device is about 1.2V; when the illumination wavelength is 530nm, 490nm, 430nm and 405nm, the threshold voltage of the device is about 2.3V. It can be seen that only the CsPbBr is present₃The perovskite quantum dot charge trapping layer has optical response on one side, and the threshold voltage of the device presents two storage states along with the change of the wavelength at low pulse voltage.

Referring to fig. 9, when the pulse programming voltage is 16V, the transfer characteristic curves of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-memory at different wavelengths, it can be seen that, unlike the low pulse gate voltage, when the illumination wavelength is 430nm, both perovskite quantum dots absorb photon energy to generate electron-hole pairs, and since the pulse gate voltage is 16V, which is higher at this time, it is enough to make the photo-generated holes pass through the 10nm thick alumina charge tunneling layer to enter the a-IGZO active channel layer by means of F-N tunneling, the threshold voltage of the device will further increase, and the transfer characteristic curves will continue to move to the positive direction.

Referring to fig. 10, the gate pulse voltages are selected to be 15V, 15.5V, and 16V, respectively, at this time, the gate voltage is high, and the aluminum oxide charge tunneling layers with different thicknesses on both sides of the device can generate F-N tunneling. When the illumination wavelength is 625nm and 565nm, the threshold voltage of the device is about 5V; when the illumination wavelength is 530nm and 490nm, the threshold voltage of the device is about 6.7V; when the illumination wavelength is 430nm and 405nm, the threshold voltage of the device is about 9V; it can be seen that the band bending of the alumina charge tunneling layer is large and the barrier height is reduced under high gate voltage, CsPbBr₃And CsPbCl₂Br two perovskite quantum dots can generate F-N tunneling, so that CsPbBr₃Perovskite quantum dot charge trapping layer and CsPbCl₂Br perovskite quantum dot charge trappingThe layers respectively generate a large number of electron-hole pairs in the corresponding wave bands capable of generating light, and the electron-hole pairs are further trapped by defects, so that the threshold voltage of the device is increased, and the threshold voltage of the device in fig. 10 shows three different storage states along with the change of the wavelength.

Fig. 11 is a schematic diagram of a relationship curve between an erase window and a gate pulse voltage of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under different wavelengths of light in the embodiment of the invention.

Fig. 11 shows the voltage erasing characteristics of the device under monochromatic illumination with different wavelengths, and the relationship between the threshold voltage and the gate voltage of the device is obtained by processing the transfer characteristic curve, and it can be seen that the erasing window of the device is almost unchanged and is close to 0 when the illumination wavelengths are 625nm and 565nm respectively. The perovskite quantum dot does not respond to the illumination of the wave band, so that the perovskite quantum dot is consistent with the erasing characteristic in the absence of illumination, and an erasing window is not formed. When the illumination wavelength is 530nm and 490nm, respectively, the device erase window increases from 0V to-3.5V as the gate voltage increases from-5V to-16V. It is noted that the device erase window increases from 0V to-2V and tends to saturate at gate voltages from-5V to-9.5V, and increases from-2V to-3.5V at gate voltages from-10V to-16V. The main reason is that when the gate voltage is small, only CsPbBr is present₃The thin alumina charge tunneling layer on one side of the perovskite quantum dot can generate F-N tunneling, and CsPbBr is in the wave band₃The perovskite quantum dots can absorb illumination to generate electron-hole pairs, and the barrier height on the thicker side is higher and is not enough to generate tunneling, so that the erasing window of the device tends to be saturated after being gradually enlarged.

FIG. 12 is a schematic diagram of an erasing characteristic curve of a device corresponding to different wavelengths of a mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a low gate pulse voltage in the embodiment of the invention; FIG. 13 is a schematic diagram showing a relationship curve between an erasing window and an illumination wavelength of a device corresponding to different low gate pulse voltages of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo-electric memory in an embodiment of the present invention; FIG. 14 is a schematic diagram of an erasing characteristic curve of a device corresponding to different wavelengths of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under a high gate pulse voltage in the embodiment of the invention; fig. 15 is a schematic diagram of a relationship curve between an erasing window and an illumination wavelength of a device corresponding to different high gate pulse voltages of a hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photo memory in an embodiment of the invention.

When the grid pulse voltage is lower, selecting the grid pulse voltage Vg to be-7V, fixing the erasing time to be 500 mu s, and setting the illumination intensity to be 1mw/cm²And testing the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory by changing different wavelengths. Referring to fig. 12, the wavelength of 625nm coincides with the transfer characteristic curve in a dark environment, indicating that illumination in this band has no effect on the device erasure characteristics because the perovskite quantum dots do not respond to illumination at 625 nm. And when the wavelength is 530nm, the device transfer characteristic curve is horizontally shifted to the negative direction, and the erasing window is about 1.8V. Mainly due to CsPbBr₃The perovskite quantum dots can absorb illumination at 530nm and generate electron-hole pairs, wherein holes neutralize the CsPbCl under the action of gate voltage₂Electrons trapped by defects in the Br perovskite quantum dot charge trapping layer cause the threshold voltage of the device to be reduced, and the transfer characteristic curve of the device moves towards the negative direction. Whereas the device transfer characteristic curves are hardly shifted compared to 530nm at a wavelength of 430 nm. The main reason is that CsPbBr is still present at this time₃And CsPbCl₂Both Br perovskite quantum dots can absorb illumination of 430nm and provide a large number of photo-generated electron-hole pairs, but the CsPbBr is low in grid voltage₃The thickness of an alumina charge tunneling layer on one side of the perovskite quantum dot charge trapping layer is thick, and electrons are not enough to enter CsPbBr in a mode of F-N tunneling₃The perovskite quantum dot charge trapping layer has no change in threshold voltage of the device, and the transfer characteristic curve of the device does not move.

Referring to FIG. 13, the erase window versus illumination wavelength for three representative mixed perovskite quantum dot floating gate a-IGZO thin film transistor photo-memories at low gate voltages (-8.5V, -9V, -9.5V) was chosen. It can be seen that the erase window of the device is about 0V in the 625nm and 565nm bands, and about 1.9V below the 530nm wavelength.

When the grid voltage is higher, selecting the grid voltage Vg to be-13V, fixing the erasing time to be 500 mu s, and setting the illumination intensity to be 1mw/cm²And testing the mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory by changing different wavelengths. Referring to fig. 14, it can be seen that the wavelength of 625nm coincides with the transfer characteristic curve in a dark environment, again since the perovskite quantum dots do not respond to 625nm illumination, 625nm illumination has no effect on the device erasure characteristic curve. When the wavelength is 530nm, the device transfer characteristic curve is horizontally shifted to the negative direction, and the erase window is increased from 0V to 3.5V. Mainly due to CsPbBr₃The perovskite quantum dot can absorb illumination at 530nm and generate electron-hole pairs, wherein holes neutralize CsPbBr under the action of grid voltage₃Electrons trapped by the defects in the perovskite quantum dot charge trapping layer cause the threshold voltage of the device to be reduced, and the transfer characteristic curve of the device moves towards the negative direction. And when the wavelength is 430nm, the device transfer characteristic curve is further shifted to the negative direction, and the erase window is increased from 3.5V to 4.9V. Mainly due to CsPbBr₃And CsPbCl₂Both the two kinds of Br perovskite quantum dots can absorb illumination of 430nm, and the grid voltage is higher at the moment, so that the CsPbBr can be used for preparing the high-performance quantum dots₃Perovskite quantum dot charge trapping layer and CsPbCl₂The energy bands of alumina charge tunneling layers with different thicknesses above the Br perovskite quantum dot charge trapping layer are bent enough to enable CsPbBr₃And CsPbCl₂The photon-generated electrons generated by two kinds of Br perovskite quantum dots can enter the charge trapping layer and electrons trapped by the defects in an F-N tunneling mode, so that the threshold voltage of the device is reduced, and the transfer characteristic curve further moves towards the negative direction.

Referring to fig. 15, the relationship between the erase window and the illumination wavelength of the a-IGZO thin film transistor photo-memory of the three representative perovskite quantum dot floating gates under high gate voltage (-14.5V, -15V, -15.5V) is chosen, and it can be seen that the erase window of the device is about 0V at 625nm and 565nm wave bands; at the wave bands of 530nm and 490nm, the erasing window of the device is about 3.5V; the device erase window is about 4.9V at the 430nm and 405nm bands.

FIG. 16 is a schematic diagram of the storage characteristics of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory under different gate pulse voltages and different illumination wavelengths in the embodiment of the invention.

The mixed perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory has multi-level storage characteristics by controlling different gate pulse voltages and different illumination wavelengths, and as shown in FIG. 16, four-level storage units can be realized by controlling different gate pulse voltages and different illumination wavelengths: memory state 1, memory state 2, memory state 3, memory state 4. Wherein the voltage pulse condition of the memory state 1 of the device is-13V/500 mu s, the illumination wavelength is 430nm, and the illumination intensity is 1mw/cm²(ii) a The voltage pulse condition of the storage state 2 is-8V/500 mu s, the illumination wavelength is 530nm, and the illumination intensity is 1mw/cm²(ii) a The voltage pulse condition of the storage state 3 is 8V/200 mus, the illumination wavelength is 530nm, and the illumination intensity is 1mw/cm²(ii) a The voltage pulse condition of the memory state 4 is 11V/200 mus, the illumination wavelength is 430nm, and the illumination intensity is 1mw/cm². It can be seen that a larger storage window is arranged between different storage states, so that the problems of misreading or data crosstalk and the like can be avoided when different storage states of the reading device are read.

FIG. 17 is a data retention characteristic curve diagram of the hybrid perovskite quantum dot floating gate a-IGZO thin film transistor photoelectric memory in the embodiment of the invention.

Referring to FIG. 17, memory state 1 and memory state 2 are two different erased states of the device, where memory state 1 erase condition is a wavelength of 430nm and an illumination intensity of 1mw/cm²A pulse voltage of-13V/500. mu.s, corresponding to a threshold voltage of-4.5V. The erasing condition of the storage state 2 is that the wavelength is 530nm and the illumination intensity is 1mw/cm²A pulse voltage of 8V/500. mu.s, corresponding to a threshold voltage of-1.8V. Memory state 3 and memory state 4 are two different programmed states of the device, where the programming condition for memory state 3 is a wavelength of 530nm and an illumination intensity of 1mw/cm²The pulse voltage of 8V/200 μ s corresponds to a threshold voltage of 2V. The programming condition of the memory state 4 is that the wavelength is 430nm and the illumination intensity is 1mw/cm²The pulse voltage of 11V/200 μ s corresponds to a threshold voltage of 6V. ThroughAfter 104s, the difference of the threshold voltage among the four storage states of the device can be kept more than 1V, and the good data retention characteristic is shown. After 104s, the difference of the threshold voltage between the storage state 1 and the storage state 4 is reduced from 10.5V to 9.8V, and the attenuation window is only 6.7%, so that on one hand, the perovskite quantum dot structure charge trapping layer prepared by thermal evaporation can effectively inhibit charge loss and improve data storage time; on the other hand, the alumina charge tunneling layer film prepared by ALD has better quality, so that a charge leakage channel is not easy to form, and the retention characteristic of the device is improved.

The endurance test method is to repeatedly perform programming and erasing operations on the memory to obtain the threshold voltage after each programming and erasing. The method comprises the following specific steps: 1, measuring an initial state transfer characteristic curve of a device; 2, adopting the programming conditions of 530nm of illumination wavelength and 1mw/cm of illumination intensity²Programming the device by using the pulse voltage of 8V/200 mu s to obtain the programmed threshold voltage; 3, then adopting the illumination wavelength of 530nm and the illumination intensity of 1mw/cm²-8V/500 μ s pulse voltage to erase the device and obtain the erased threshold voltage; 4, repeating the step 2 and the step 3 all the time; and 5, finally obtaining the relation between the threshold voltage and the cycle number after programming and erasing of the device. As can be seen from fig. 18, the device threshold voltage window remains stable, about 3.6V, until 600 program and erase cycles, and starts to decay as the program and erase operations continue, mainly due to long-term voltage stress, resulting in degradation of device performance. It is worth mentioning that after 1000 program and erase cycling operations, the threshold voltage window of the device is reduced from 3.64V to 3.11V, and the attenuation window is only 14.5%, which shows better program endurance and erase endurance.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims

1. A dual half floating gate optoelectronic memory, comprising:

a gate electrode;

2. The dual semi-floating gate optoelectronic memory of claim 1, wherein said first charge trapping layer and said second charge trapping layer are both fabricated using perovskite quantum dots, and wherein the band gap widths of the constituent materials of said first charge trapping layer and said second charge trapping layer are different.

3. The dual half floating gate photo memory of claim 1, wherein a difference between a thickness of the first charge trapping layer and a thickness of the second charge trapping layer is less than 5 nm.

4. The dual half-floating gate optoelectronic memory of claim 1, wherein the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are both less than 20nm, and the thickness of the first charge trapping layer and the thickness of the second charge trapping layer are not equal.

5. The dual half-floating gate photo memory of claim 1, wherein the charge tunneling layer disposed on the top surface of the second charge trapping layer has a thickness of 5-7 nm.

6. The dual half-floating gate photo memory of claim 1, wherein the charge tunneling layer disposed on the upper surface of the first charge trapping layer has a thickness of 10-15 nm.

7. The double semi-floating gate photoelectric memory of claim 2, wherein the perovskite quantum dot has a structure of CsPbX_nY_mZ_pThe X, the Y and the Z are Br element, I element and Cl element respectively, the values of n, m and p are any one of 0, 1, 2 and 3, and the sum of n, m and p is equal to 3.

8. The dual semi-floating gate photo memory of claim 1, wherein the charge tunneling layer comprises a first charge tunneling layer and a second charge tunneling layer, a portion of the first charge tunneling layer being disposed between the charge blocking layer and the second charge trapping layer, another portion of the first charge tunneling layer being disposed on the upper surface of the first charge trapping layer, and the second charge tunneling layer being disposed on the upper surface of the second charge trapping layer and the upper surface of the first charge tunneling layer.

9. The dual semi-floating gate photo-memory of claim 1, further comprising an auxiliary charge blocking layer disposed between said charge blocking layer and said second charge trapping layer, said auxiliary charge blocking layer being disposed adjacent to said first charge trapping layer.

10. The dual half floating gate optoelectronic memory of claim 8 or 9, wherein the thickness of said first charge trapping layer and the thickness of said second charge trapping layer are both less than 20nm, and the thickness of said first charge trapping layer and the thickness of said second charge trapping layer are equal or unequal.

11. The dual half-floating gate photo-memory of claim 8, wherein the thickness of the first charge tunneling layer and the thickness of the second charge tunneling layer are equal or unequal.

12. The dual half-floating gate optoelectronic memory of claim 1, further comprising a substrate, said gate disposed on an upper surface of said substrate.

13. The process for preparing a double-half floating gate photoelectric memory according to any one of claims 1 to 12, comprising the following steps:

s1: forming the grid electrode;

s2: forming the charge blocking layer on the upper surface of the gate;

s4: forming the active channel layer on the charge tunneling layer;

14. The process of claim 13, wherein the step S3 of forming the first charge trapping layer and the second charge trapping layer on the upper surface of the charge blocking layer and forming the charge tunneling layer on the upper surface of the first charge trapping layer and the upper surface of the second charge trapping layer comprises:

15. The process of claim 13, wherein in the step of forming the first and second charge trapping layers on the upper surface of the charge blocking layer in step S3, the first and second charge trapping layers are thermally evaporated by a two-step sequential method.