RO133227B1 - Optoelectronic memory structure with floating gate of germanium nanocrystals - Google Patents

Description

RO 133227 Β1

The present invention relates to a capacitor-type non-volatile memory structure for the detection and storage of information regarding both electrical and optical pulses and the method of obtaining them. The proposed structure is of the metal-oxide-semiconductor (MOS) type with a floating gate formed by nanocrystals (NC) of Ge in oxide (HfO ₂ ), where the metal gate electrode is replaced by a transparent electrode (conductive transparent oxide -TCO) .

Non-volatile (or semi-volatile) floating gate memories (NVMs) have had a long evolution since the 1967 article (Kahng, D., and Sze, S. M., Bell SystTech J (1967) 46,1288). Its structure consists in modifying the structure of the field-effect MOS transistor, having a layer with the role of a floating gate, separated from the semiconductor by a thin tunnelable insulator and isolated from the metal gate electrode above by another oxide layer. The floating gate can be metallic or made of polycrystalline semiconductor. The floating gate can be loaded with electrical charges by exchanging electrons with the semiconductor substrate. Two mechanisms of floating-gate electron injection have been used in bloom memory in floating-gate MOS transistors: electric-field Fowler-Nordheim tunneling (FNT) injection by applying a gate voltage and hot electron injection (CHE ) to high current pulses through the transistor channel (William D. Brown, Joe E. Brewer: Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices. IEEE Press, 1997). The second process, CHE, although it has low efficiency and high energy consumption, has the advantage of a faster process than in the case of FNT. (Skorobogatov S. (2005) Data Remanence in Flash Memory Devices. In: Rao J.R., Sunar B. (eds) Cryptographic Hardware and Embedded Systems - CHES 2005. CHES 2005. Lecture Notes in Computer Science, vol. 3659. Springer, Berlin , Heidelberg). Obviously, for floating-gate capacitor type memory, only the FNT method can be used for writing and erasing. One way of erasing the information stored in the NVM is by exposure to ultra-violet (UV) light. This procedure is a global wipe of a memory array. Another method is based on FNT, which can delete information from a single node. in the UV erasing process of a floating gate memory, an important role is played by the photoelectric effect at the edge of the metal gate electrode, this erasing process works in the case of a continuous floating gate (not with isolated nanoparticles). By both methods of erasing information, however, defects are produced in the tunnel layer responsible for memorizing information, thus reducing the endurance of the device by limiting the number of write-erase operations (C. Zhao, C. Z. Zhao, S. Taylor and P. R. Chalker, Materials 7, 5117 (2014)). Therefore, it is necessary to find less invasive information erasure-write methods, such as the one that is the subject of this patent application, by combining electrical stress of moderate applied voltages, with illumination with light in the visible-near-infrared range (VIS- NIR).

A shortcoming of floating-gate memory formed by a continuous layer (metallic or polycrystalline semiconductor) is that a single local defect can short-circuit the entire memory element. This was eliminated by replacing the floating gate layer with a layer containing nanocrystals, either metallic or semiconducting, isolated from each other. Thus, even if not all nanocrystals (hereafter referred to as - NC) remain charged, the memory still retains stored information (S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, IEEE Int. Electron Devices Meeting Tech. Dig., p. 521 (1995); T. R. Oldham, M. Suhail, P. Kuhn, E. Prinz, H. S. Kim, and K. A. LaBel, IEEE Trans Nuci. Sci., 52, 2366 ( 2005)). For Si and Ge NC-based memories, properties such as

RO 133227 Β1 fast writing and long retention time could be demonstrated (A. Bennett, A. Chelly, 1 A. Karsenty, I. Gadasi, Z. Priel, Y. Mandelbaum, T. Lu, I. Shlimak, and Z Zalevskya, J.

of Nanophotonics 10, 036001 (2016)). The charge loading process of semiconductor NCs is also influenced by the quantum effect of carrier confinement, which changes the limits of the valence and conduction bands depending on the NC size, and consequently the probability of carrier tunneling (E. G. Barbagiovanni, D.J. Lockwood, P.J. Simpson, L.

V. Goncharova, Appl. Phys. Rev., 1,11302 (2014)). In addition, the Coulomb blockade phenomenon occurs in nanocrystals, after charging an NC with an electron, charging with a second electron requires a higher energy. Thus, depending on the size and 9 uniformity of the NC, as well as the operating temperature, the memory device can have several levels of NC charge separated enough to operate in a multiple 11 logic, thus increasing the information density (S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, Appl. Phys. Lett. 68, 1377 (1996)). A simplified formula that 13 can be used to evaluate the charge stored in the NC is proposed in the work of S.

Tiwari et al. cited above. It corresponds to a linear dependence of the struck charge q 15 in a single NC, on the flat band voltage V _fb , the proportionality factor depending on the surface density of the NC, the thickness of the layers and the dielectric permittivity of these layers. The value of V^ corresponds to the electric voltage applied to the gate electrode at which the electric field in the tunnel layer is zero, the induced charge in the region of the Si support being zero. The variation AV _fb defines the load variation on the NC following writing or erasing processes that induce a hysteresis effect in the capacity curve as a function 21 of the gate voltage (CV). This variation can also characterize the influence of illumination on memory status, as presented in this patent application. 2. 3

Various techniques have been used for the production of Si and Ge NCs such as:

depositions by magnetron sputtering (MSD), ion implantation, physical vapor deposition, 25 laser sputtering, chemical vapor deposition (CVD), or by plasma - CVD (D. Lehninger,

J. Beyer, and J. Heitmann, Phys. Status Solidi A 215,1701028 (2018); M. L. Ciurea and 27 A. M. Lepadatu, Dig. J. Nanomater. Bios., 10,59 (2015)). compared to Si NCs, Ge ones offer various advantages, including a low thermal budget for their formation 29 (T.-C. Changa, F.-Y. Jiana, S.-C. Chenc, and Y .-T. Tsai, MaterialsToday 14,608 (2011)).

For memories with high performance, especially good retention, NCs must be well 31 electrically isolated from each other (A. M. Lepadatu, C. Palade, A. Slav, A. V. Maraloiu, S. Lazanu,

T. Stoica, C. Logofatu, V. S. Teodorescu and M. L. Ciurea, Nanotechnology, 28, 175707 33 (2017)). Controlling the number of NCs per memory element is also important in reducing device size. This could be achieved by selective growth of SiGe on very small areas followed by selective oxidation of Si (L. Vescan, T. Stoica,

B. Hollaender, A. Nassiopoulou, A. Olzierski, I. Raptis and E. Sutter, Appl. Phys. Lett., 37 82, 3517 (2003); T. Stoica and E. Sutter, Nanotechnology, 17, 4912 (2006); FIB FORUM, EU FP5-IST project, http://cordis.europa.eu/project/rcn/57788 en.html). 39

NC floating gate memories reported in the literature are usually based on Si or Ge NCs in SiO ₂ . Those with Ge NCs in SiO ₂ have the advantage of a lower thermal budget at high for-41, as shown above, but also a longer hole retention time than for electrons (M. Kanoun, C. Busseret, A .Poncet, A. Souifi, T. Baron, E. Gautier, Solid-State 43 Electronics 50,1310 (2006)). Using a high dielectric constant insulator such as HfO ₂ instead of SiO ₂ allows for a smaller equivalent oxide thickness, which is important for small size 45 FETs (P. Punchaipetch, Y. Uraoka, T. Fuyuki, A. Tomyo, E . Takahashi, T. Hayashi, A. Sano, and S. Horii, Appl. Phys. Lett. 89, 093502 (2006). 47

RO 133227 Β1 since the beginning of non-volatile memory, exposure to UV light has been a method of erasing written information by electrical pulses, in the case of a continuous floating gate. There have also been studies on the interaction of UV with nanocrystal memories. Thus, in a capacitor with NCs distributed throughout the gate oxide layer, UV illumination can induce rapid capacitance switching (M. Yang, TP Chen, L. Ding, Y. Liu, FR Zhu, and S. Fung, App. Phys. . Lett. 95,091111 (2009)). As previously shown, UV illumination can induce defects by reducing memory endurance, so lower energy photon illumination is desirable. Photocarrier generation effects that can contribute to the operation of an optoelectric memory can take place in the NC, and/or in the semiconductor support. Charge transfer between the NC and the Si support can also be activated by photoconduction in the case of oxides with a high dielectric constant and lower bandgap, such as TiO ₂ . The photoconductivity of Ge NC layers in TiO ₂ can be substantially increased by the field effect induced by the semiconductor support (A.-M. Lepadatu, A. Slav, C. Palade, I. Dascalescu, M. Enculescu, S. Iftimie, S. Lazanu, VS Teodorescu, ML Ciurea, and T. Stoica, Scientific Reports 8, 4898 (2018)). Capacitor structures with Ge NCs distributed in the insulating SiO ₂ layer acting as high illumination frequency photodetectors have also been designed (A. Bennett, A. Chelly, A. Karsenty, I. Gadasi, Z. Priel, Y. Mandelbaum , T. Luc, I. Shlimak, and Z. Zalevskya, J. of Nanophotonics 10,036001 (2016)). There are few publications dealing with the influence of light on the hysteresis curve of NC floating gate memory, especially in memory devices based on organic layers (H. Wang, Z. Ji, L. Shang, Y. Chen, M . Han, X. Liu, Y. Peng, M. Liu, Organic Electronics 12,1236 (2011); X. Gao, C.-H. Liu, X.-J. She, Q.-L. Li, J. . Liu, S.-D. Wang, Organic Electronics 15, 2486 (2014); J. Ying, J. Han, L. Xiang, W. Wang, W. Xie, Current Applied Physics 15, 770 (2015)). Photocapacitance measurements are commonly used to characterize interface states (eg MHWeng, S.Barker, R. Mahapatra, BJD Furnival, NG Wright, AB Horsfall, Materials Science Forum 679-680,350 (2011)). In Ni nanocrystal memories, low-voltage erasure is enhanced by the presence of visible light (JT Li, LC Liu, PH Ke, JS Chen and JS Jeng, J. Phys. D: Appl. Phys. 49,115104 (2016)) . The effect of illumination on the hysteresis curve was demonstrated in the case of memory based on Si NC in SiO ₂ (S. Chatbouri a, M. Troudi, A. Fargi, A. Kalboussi, A. Souifi, Superlattices Microstruct. 94, 93 (2016 )), as well as to Ge NC in HfO ₂ (C. Palade, A. Slav, AM Lepadatu, S. Lazanu, ML Ciurea and T. Stoica, IEEE Conference Publications: 2017 International Semiconductor Conference (CAS), 87 (2017) ).

As shown above, the history of floating-gate memories begins in 1967 with the publication of Kahng and Sze, and since then a whole series of patents have been published on the subject. The idea of replacing the floating gate with a NC layer proposed in 1995 by S. Tiwari etal. was later patented in 1999 (US 005937295A/1999/W. Chen, Th.P. Smith, S. Tiwari Nano-Structure Memory Device). A series of patents followed, describing methods for fabricating NC semiconductors as floating gates in non-volatile memories (US 006090666A/2000/ T. Ueda; K. Nakamura, Y. Fukushima, Method for Fabricating Semiconductor Nanocrystal and Semiconductor Memory Device using the Semiconductor Nanocrystal ; US006060743A/2000/N. Sugiyama; T. Tezuka, R. Katoh, A. Kurobe, T. Tanamoto, Semiconductor Memory Device Having Multilayer Group IV Nanocrystal, Quantum Dot Floating Gate and Method of Manufacturing the Same; US6656792B2/2003/ W. K. Choi, W. K. Chim, V. Ng, L. Chan, Nanocrystal Flash Memory Device and Manufacturing Method Therefor; US007045851B2/2006/ C.T. Black, K.W. Guarini, Nonvolatile Memory Device using Semiconductor Nanocrystals and Method

RO 133227 Β1 of Forming Same; US 20060166435A1/2006/LW Teo, SS Nagarao, EKB Quek, DK 1 Sohn, Synthesis of Ge Nanocrystal Memory Cell and Using a Block Layer to Control Oxidation Kinetics). Methods of manufacturing memories with floating gate 3 based on NC made with the nanowire growth technique as well as the use of insulating matrices with a high dielectric constant have also been patented (US 20070029600A1/2007/GM Cohen, Nanowire 5 Based Non-Volatile Floating -Gate Memory; US20130 062684A1/2013/S. Ding, H. Gou, SW Zhang, Gate Stack Structure and Fabricating Method used for Semiconductor 7 Flash Memory Device). Invention patent regarding the manufacture of memories with Ge NC with floating gate from Ge NC in SiO ₂ , (no. 131074 Bl, published RO-BOPI sect, inventions no. 9 4/2018 dated 30.04.2018, "Capacitor structure for non-volatile memory based on germanium nanocrystals immersed in silicon dioxide"), as well as patent application 11 regarding memories with Ge NC in high dielectric constant insulators - HfO ₂ (RO131968-A0/2017, entitled "Capacitive matrix for memory non-volatile, based on 13 germanium nanocrystals immersed in hafnium dioxide, and its manufacturing process") were developed by the members of the group that also includes the drafting team of the present patent application.

The effect of illumination on Si continuous floating gate memories has been the subject of 17 VIS-NIR or UV illumination patents (US3950738/1976/Y. Hayashi, K. Nagai, Y. Tarui, Semi-Conductor Non-Volatile Optical 19 Memory Device; USOO5401991A/1995Z Y. Imura, Optically Erasable Nonvolatile Semiconductor Memory). Various light-sensitive memory structures based on lll-V semiconductors have also been patented (US 4905063/19907 F. Beltram, F. Capasso, R. J. Malik, N.J. Shah, Floating Gate Memories; US6147901/2000/ H. Sakata, Y. Nagao, Y. 23 Matsushima, Semiconductor Memory Operating Electrically and Optically, Retaining Information Without Power Supply). 25

There are few patents on the influence of light on NC memories. A patented complex layered structure in which photovoltaic generation is stored 27 in the NC so that it can then be discharged (US20060268493A1/2006/T. Miyasaka, T. Murakami, Photochargeable Layered Capactor Comprising Photovoltaic Electrode Unit and 29 Layered Capactor Unit) refers more to energy generation and storage than memory effects. There is an NC-based floating gate memory patent with a 31 structure similar to the one that is the subject of this patent application, but in which the electrically controlled state of charge is optically detected by light reflection 33 (US 20060268493A1/2006/ T. Miyasaka , T. Murakami, Photochargeable Layered Capactor Comprising Photovoltaic Electrode Unit and Layered Capactor Unit). 35

The present patent proposal relates to a Ge NC floating gate capacitor memory structure to be sensitive to both electrical and light pulses. The structure consists of the following sequence of layers deposited by the MSD method on a Si wafer: transparent gate electrode TCO/ control oxide HfO ₂ / floating gate of 39 Ge NC in HfO ₂ / tunnel layer of HfO ₂ /Si substrate. The second electrode of the capacitor is metallic and is deposited on the back of the Si wafer. The structure can later be integrated, for example, with waveguides for monitoring various lighting events, or it can be integrated into an image storage matrix. 43

The technical problem that the present invention solves is the detection and storage of light pulses and electric voltage pulses by inter-dependently and cumulatively changing the value of the flat band voltage V/b. The response to the light pulse is dependent on the previous electrical write pulse or the overlap of the electrical pulse with 47

RO 133227 Β1 that of light, effect on which the operation of the optoelectric memory structure is based. In addition, photoelectric memory under illumination exhibits significantly improved memory characteristics over electric field memory, namely significantly reduced response time and write voltage.

The optoelectric memory structure with floating gate formed by NC of Ge in HfO ₂ , has the following component parts:

- HfO ₂ control oxide layer, 20...70 nm thick, obtained by MSD deposition;

- floating gate layer 5...10 nm thick, obtained by MSD deposition of Ge and HfO ₂ alloy in a volume proportion of 57...70% and treated by RTA after MSD deposition, for the formation of NCs with diameters comparable to gate layer thickness;

- tunnelable layer of HfO ₂ 5...8 nm thick, obtained by MSD deposition of HfO ₂ ;

- Si support with resistivity in the range of 5...15 Qcm;

- electrodes: 100 nm thick conductive TCO upper electrode and Al electrode on the back of the Si wafer, 50...150 nm thick, and

- a conductive transparent TCO electrode is made of ITO with a resistivity of less than 50 Ω/square and an optical transmission of more than 50% in the VIS-NIR range, it detects and stores the application of light pulses and electric voltage by changing in an interdependent and cumulative way of the flat band voltage V _fb , namely the response to the light pulse is dependent on the previous electrical writing pulse or the overlapping of the electrical pulse with the light pulse, and also presents a sensitivity reaching values of the order of 110 mV/mJ at low illuminations below 1 mJ in the VIS-NIR range.

The proposed optoelectric memory structure has several advantages compared to other possible floating gate memory structures:

- the floating gate is made of Ge NCs well insulated from each other, which gives a high stability of the charge stored in the NC and the possibility of forming individual capacitor structures; the floating gate consists of a single layer of Ge NCs well insulated from each other, but with high density (AM Lepădații, C. Palade, A. Slav, AV Maraloiu, S. Lazanu, T. Stoica, C. Logofatu, VS Teodorescu and ML Ciurea, Nanotechnology, 28, 175707 (2017)), which absorb light as in an effective GeNC/HfO ₂ environment generating photocarriers in Ge NC that can contribute to the modification of the memory state;

- the small thickness of the single layer of Ge NC provides a moderate absorption of light in this layer, the light transmitted through it generating photocarriers in the Si support that participate substantially in charge transfer processes;

- Ge NC in a single layer provides a precise spacing from the support, and thus the charge-discharge process with electric charge is well controlled;

- the use in the structure of the capacitor of an oxide with a high dielectric constant, HfO ₂ , corresponds to an amplification of the charge injection electric field, thus allowing the operation of the device at low voltages and the reduction of the size of the device;

- the use of a transparent TCO gate electrode provides high transparency in the VIS-NIR while still having a metallic conductance.

Next, an example of the invention is given in connection with fig. 1...2, which represents:

- fig. 1, schematic of a section through the structure of the optoelectric memory capacitor having an electrode transparent to VIS-NIR light, over a structure of three layers of HfO ₂ including the floating gate with Ge NC, the structure being deposited on a Si support provided on the back with an electrode of Al;

- fig. 2, the variation of the flat band voltage V^ as a function of the integrated power of the light pulses applied to the capacitor memory, following writing with two values of the gate voltage.

RO 133227 Β1

The memory processes are based on the transfer of electrical charges (electrons) between the 1 Si support and the Ge NC through the tunnel layer, with the participation of dark charge carriers as well as photocarriers generated by illumination. The charge-discharge process due to the 3 photo effect in the Si support is highly sensitized by the photo-generation of minority carriers in the support (electrons in the case of p-Si) and by photocarriers of the opposite direction in Ge NC. The 5 CV characteristic of the capacitor reveals a transition from high capacity in the regime of accumulation of majority carriers at the surface of the support, to lower capacities when a 7 surface depletion zone is induced in the support. The voltage to which the transition is made is the flat band voltage V _fb , which depends linearly on the state of charge of the NC. 9

According to the invention, the device is made in several technological steps:

- MSD deposition on Si supports of the three insulating layers of HfO ₂ containing 11 the floating gate intermediate layer in the form of an alloy of Ge and HfO ₂ , the Si supports being previously cleaned with the standard RCA process, after which the oxide was removed native; 13 RTA thermal treatments for the formation of Ge NCs in HfO ₂ as a floating gate; deposition of transparent TCO electrode by tin-doped indium oxide (ITO) MSD; deposition of 15 Al electrode on the back of the Si wafer, with prior removal of the native oxide.

To create the capacitor structure with optoelectric memory, 17 MSD depositions are used (fig. 1). P-doped Si 1 wafers with a resistivity of 5...15 Qcm were used. The wafers were pre-cleaned using a standard Si cleaning (RCA) technique, 19 consisting of immersing them in a 2:1 solution of sulfuric acid H ₂ SO ₄ and hydrogen peroxide H ₂ O ₂ at room temperature of 60°C, for 10 min, followed by washing in deionized water 21 (Dl). finally, the wafer is placed in 2% HF hydrofluoric acid solution in Dl water for 20 s to remove the native Si oxide. It is again washed in D1 water and dried by blowing with N ₂ . The wafers thus cleaned are passivated with hydrogen against oxidation in air, for a relatively short time, during which they are introduced into the MSD deposition chamber. 25 Next is the deposition of capacitor oxide layers by MSD using separate targets.

The basic vacuum in the installation is ~10' ⁷ mbar, the deposition of layers is carried out by MSD 27 in an Ar atmosphere at a pressure of 4...6 mbar. HfO ₂ deposition was performed in radio frequency plasma (RF 13.56 MHz) from HfO ₂ target, and Ge deposition was performed in DC plasma from 29 Ge target. Initially, the tunnel layer of HfO ₂ 21 was deposited with a nominal thickness of 5...8 nm, with a deposition rate of 1.0...1.5 nm/min. This was followed by the deposition of the floating gate layer 22 31 5...10 nm thick, by co-deposition of Ge and HfO ₂ , with deposition rates adjusted so as to obtain a volume concentration of 57...70% Ge in HfO ₂ . The layer 33 of control oxide 23 of HfO ₂ with a thickness of 20...70 nm was then deposited. The post-deposition RTA thermal treatment was carried out in an Ar atmosphere at 62O...65O°C for 6...10 min. The formation of a single NC layer of Ge 221 with diameters of around 6...7 nm, well isolated from each other, was thus achieved. Next is the deposition of the transparent electrode 3 through the MSD of the ITO layer, with a thickness of 37 around 100 nm and a resistivity of less than 50 Ω/square and an optical transmission of more than 50%.

The second electrode 4 was made of thermally evaporated Al on the back of the Si wafer, 39 thick 50...150 nm, after the native oxide layer was previously removed in HF solution, followed by immersion in water Dl and drying with N ₂ flow. 41

Experiments on the effect of illumination 5 on the writing and erasing of the optoelectric memory thus achieved were carried out using the light of a 43 tungsten filament lamp, with illumination intensities of 1...20 mW/cm ² . Light pulses were applied, following the changes produced by the light on the flat band voltage V _fb . For 45 this particular case of memory, the dependence of the voltage V _fb on the integrated light power applied to a capacitor of area 1 mm ² is shown in fig.2, for two states of the memory: 47 after relaxation to zero voltage 61; and following programming at -2 V 62. The variation with light exposure of voltage V^ is stronger in memory in the state after 49 negative voltage programming, where a slope of 110 mV/mJ was obtained below 1 mJ, having the tendency to saturate above 2 mJ. 51

Claims (1)

RO 133227 Β1 Claim Floating-gate optoelectric memory structure made of Ge nanocrystals in HfO ₂ , having the following component parts: - layer (23) HfO ₂ control oxide, 20...70 nm thick, obtained by MSD deposition; - floating gate layer 5...10 nm thick, obtained by MSD deposition of Ge and HfO ₂ alloy in a volume proportion of 57...70% and RTA treated after MSD deposition, for the formation of nanocrystals (221) of diameters comparable to the thickness of the gate layer (22); - tunnelable layer (21) of HfO ₂ 5...8 nm thick, obtained by MSD deposition of HfO ₂ ; - Si support (1) with resistivity in the range of 5...15 Qcm; - electrodes: upper TCO conductive electrode (3) 100 nm thick and Al electrode (4) on the back of the Si wafer, 50...150 nm thick, and characterized by the fact that the TCO conductive electrode (3) is made of ITO with resistivity less than 50 Ω/square and optical transmission more than 50% in the VIS-NIR range, detects and stores the application of light pulses and electrical voltage by interdependently and cumulatively changing the flat band voltage V _fb and namely, the response to the light pulse is dependent on the previous electrical writing pulse or on the overlap of the electrical pulse with the light one, and also presents a sensitivity reaching values of the order of 110 mV/mJ at low illuminations below 1 mJ in the VIS range -NIR.