CN112201658A - Floating gate type phototransistor memory based on self-assembly tunneling layer and preparation method thereof - Google Patents
Floating gate type phototransistor memory based on self-assembly tunneling layer and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a floating gate type phototransistor memorizer of self-assembly tunnel layer and its preparation method, including basement, insulating layer, floating gate layer, tunnel layer, semiconductor layer and top source drain electrode; blending the perovskite nano-particle solution with TMOS or TEOS to prepare a floating gate layer solution; cleaning and plasma treating a substrate with an insulating layer, depositing a floating gate layer solution on the substrate through a spin coating process, and annealing to form a floating gate layer and a tunneling layer; spin-coating TMOS or TEOS on the obtained tunneling layer by a spin coating process, annealing, and adjusting the thickness of the self-assembled tunneling layer by repeating the steps; spin-coating an organic polymer semiconductor material on the obtained tunneling layer by a spin coating process, and annealing to obtain a semiconductor layer; and preparing a source electrode and a drain electrode on the obtained semiconductor layer by a thermal evaporation method to obtain the self-assembled tunneling layer of the floating gate type phototransistor memory. The invention has higher stability, realizes repeatable multilevel storage and nonvolatile storage with multiple wavelengths, has simple process flow and is easy for large-scale industrialization.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a self-assembled tunneling layer floating gate type phototransistor memory and a preparation method thereof.
Background
With the explosive growth of consumer electronics and information markets, increasing the data storage capacity of storage devices has become a pressing need. The development of multilevel memories is a promising solution due to the limitation of moore's law bottleneck. Compared with the traditional electric memory, the photoelectric memory can realize multi-level storage capacity. In addition, the floating gate type nonvolatile photonic memory (FGTPM) based on the organic field effect transistor has good prospect in the semiconductor field due to the multistage data storage capacity, the transistor circuit compatibility and the excellent stability.
On the other hand, as a new star material in the semiconductor industry, the metal halide perovskite nanocrystal has excellent photoelectric characteristics such as adjustable band gap, high carrier mobility, long carrier life, high defect tolerance and the like, and is applied to the fields of solar cells, detectors, lasers, photoelectric crystals and the like, and also applied to nonvolatile photon memories based on organic field effect transistors. Currently, metal halide perovskite nanocrystals are often blended with organic cross-linked polymers to be used as floating gate layers, however, the structures often have the problems of small storage window, short retention time and the like, so that the structures are easy to be used in the field of organic thin film transistorsIt is often necessary to additionally deposit a dense charge tunneling layer (e.g., Al) between the dielectric layer and the semiconductor layer2O3) To achieve better charge trapping, but this results in complicated processing and increased cost, and high temperature and humidity also cause degradation of the perovskite during deposition of the charge tunneling layer. In addition, when the floating gate layer is prepared by a solution method, the polymer and the solvent thereof can also destroy the structure of the perovskite nanocrystal, so that the perovskite nanocrystal is agglomerated to different degrees, and the excellent performance is lost. Therefore, for organic field effect transistor non-volatile photonic memories based on perovskite nanocrystals, alternatives to current floating gate layers are sought&The scheme of the tunneling layer becomes a problem to be solved urgently.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a floating gate type phototransistor memory with a self-assembled tunneling layer and a method for manufacturing the same, which can achieve high stability of the floating gate type phototransistor memory, multi-level nonvolatile storage, and simplified process flow, and is easy for large-scale industrialization.
The invention is realized by adopting the following scheme: a floating gate type phototransistor memory of the self-assembly tunneling layer, including basement, insulating layer, floating gate layer, tunneling layer, semiconductor layer and top source drain electrode; the semiconductor device comprises a substrate, an insulating layer, a floating gate layer, a tunneling layer, a semiconductor layer and a top source drain electrode, wherein the insulating layer grows on the substrate, the floating gate layer grows on the insulating layer, the tunneling layer is tightly wrapped outside the floating gate layer, the semiconductor layer grows on the tunneling layer, and the top source drain electrode grows on the semiconductor layer.
Further, the substrate material can be selected from silicon, polyethylene terephthalate (PET) or polydimethylsiloxane.
Further, the insulating layer material can be selected from oxide, gallium nitride, silicon carbide or organic polymer.
Further, the floating gate layer adopts discrete perovskite nano-particle materials to serve as charge trapping centers; the floating gate layer is prepared by deposition through a spin coating process, and the particle size of the floating gate layer is 10-80 nm.
Furthermore, the tunneling layer is oligomeric silicon dioxide (OS), is tightly wrapped outside the floating gate layer material, and has a thickness of 20-200 nm.
Further, the oligomeric silicon dioxide is formed by hydrolysis self-assembly under a humidity annealing treatment after Tetramethoxysilane (TMOS) or Tetraethoxysilane (TEOS) is deposited using a spin coating process.
Furthermore, the semiconductor layer is made of an organic polymer semiconductor material, and the thickness of the semiconductor layer is 100-500 nm.
Furthermore, the top source drain electrode is made of indium tin oxide, gold, aluminum or silver, and the thickness of the top source drain electrode is 50-100 nm.
Furthermore, the invention also provides a preparation method of the floating gate type phototransistor memory with the self-assembled tunneling layer, which comprises the following steps:
step S1: blending the perovskite nano particle solution with tetramethoxysilane or tetraethoxysilane in a blending volume ratio of 2:1-1:3 to prepare a floating gate layer solution;
step S2: cleaning and plasma processing a substrate with an insulating layer, depositing a floating gate layer solution on the substrate by a spin coating process, and annealing in a humidity environment, wherein the spin coating rotation speed is 1000-3000rpm, the spin coating time is 45-60s, the annealing condition is humidity 70-80%, temperature is 50-70 ℃, and time is 10-30 min; tetramethoxysilane or tetraethoxysilane is hydrolyzed and self-assembled to form oligomeric silicon dioxide which is coated on the surface of the perovskite nano particles to form a floating gate layer and a tunneling layer;
step S3: spinning tetramethoxysilane or tetraethoxysilane on the tunneling layer obtained in the step S2 through a spin coating process, and annealing in a humidity environment, wherein the processing parameters are consistent with those in the step S2; controlling the thickness of the self-assembled tunneling layer by adjusting the number of times of repeating the step S3, wherein the number of times of repeating is 0-4;
step S4: spin-coating an organic polymer semiconductor material on the tunneling layer obtained in the step S2 or the step S3 through a spin-coating process, and annealing to obtain a semiconductor layer;
step S5: and (4) preparing a source electrode and a drain electrode on the semiconductor layer obtained in the step (S4) by a thermal evaporation method to obtain the floating gate type phototransistor memory with the self-assembled tunneling layer.
Further, the tunneling layer is deposited by a spin coating process in step S3, the rotation speed is 1000-.
Compared with the prior art, the invention has the following beneficial effects:
the floating gate type phototransistor memory prepared by the method provided by the invention has the advantages of high stability, high storage window, realization of multi-level storage function, effective expansion of storage capacity of devices, simple operation, low cost, easy popularization and application, remarkable economic and social benefits, realization of the function of optical writing and electric erasing of the obtained memory, realization of the regulation of the storage window by regulating the thickness of the protective layer, great potential for the application of the memory in the field of semiconductor storage, and suitability for the fields of large-scale integrated circuits and the like.
Drawings
Fig. 1 is a schematic structural diagram of a floating gate phototransistor memory according to an embodiment of the present invention, in which 100 is a substrate, 110 is an insulating layer, 120 is a floating gate layer, 130 is a tunneling layer, 140 is a semiconductor layer, and 150 is a top source/drain electrode 150.
Fig. 2 is a graph showing transfer characteristics of the floating gate type phototransistor memory according to the embodiment of the present invention.
Fig. 3 is a graph showing retention characteristics of the floating gate type phototransistor memory according to the embodiment of the present invention.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As shown in fig. 1, the present embodiment provides a floating gate phototransistor memory with a self-assembled tunneling layer 130, which includes a substrate 100, an insulating layer 110, a floating gate layer 120, a tunneling layer 130, a semiconductor layer 140, and a top source/drain electrode 150; the insulating layer 110 grows on the substrate 100, the floating gate layer 120 grows on the insulating layer 110, the tunneling layer 130 is tightly wrapped outside the floating gate layer 120, the semiconductor layer 140 grows on the tunneling layer 130, and the top source drain electrode 150 grows on the semiconductor layer 140;
when the floating gate layer 120 is illuminated, the memory enters a working state, the floating gate layer 120 absorbs photons to generate photon-generated carriers, and ground-state electrons in the semiconductor layer 140 are transferred to the floating gate layer 120 to fill valence band vacancies caused by light excitation. Meanwhile, due to the existence of the tunneling layer 130, generated photo-generated electrons are limited in the floating gate layer 120, so that the dissipation of current is inhibited, and the optical programming is realized. The trapped electrons are then erased by applying a negative gate bias to overcome the interfacial barrier of the corresponding tunneling layer 130, facilitating hole injection and achieving electrical erasure.
In the present embodiment, the material of the substrate 100 can be selected from silicon, polyethylene terephthalate (PET) or polydimethylsiloxane.
In the present embodiment, the material of the insulating layer 110 can be selected from oxide, gallium nitride, silicon carbide or organic polymer.
In this embodiment, the floating gate layer 120 is made of discrete perovskite nanoparticle material, which is used as a charge trapping center; the floating gate layer 120 is formed by deposition through a spin coating process, and the particle size of the floating gate layer is 10-80 nm.
In this embodiment, the tunneling layer 130 is an oligomeric silicon dioxide (OS), and is tightly wrapped outside the floating gate layer 120, and has a thickness of 20-200 nm.
In the present embodiment, the oligomeric silicon dioxide is formed by hydrolysis self-assembly under a humidity annealing treatment after Tetramethoxysilane (TMOS) or Tetraethoxysilane (TEOS) is deposited using a spin-on process.
In the present embodiment, the semiconductor layer 140 is made of an organic polymer semiconductor material and has a thickness of 100-500 nm.
In this embodiment, the top source/drain electrode 150 is made of indium tin oxide, gold, aluminum, or silver, and has a thickness of 50-100 nm.
Preferably, the present embodiment further provides a method for manufacturing a floating gate phototransistor memory with a self-assembled tunneling layer 130, comprising the following steps:
step S1: blending the perovskite nano particle solution with tetramethoxysilane or tetraethoxysilane in a blending volume ratio of 2:1-1:3 to prepare a floating gate layer 120 solution;
step S2: after cleaning and plasma processing the substrate 100 with the insulating layer 110, depositing the floating gate layer 120 solution on the substrate 100 through a spin coating process, and annealing in a humidity environment, wherein the spin coating rotation speed is 1000-3000rpm, the spin coating time is 45-60s, the annealing condition is humidity 70-80%, temperature is 50-70 ℃, and time is 10-30 min; tetramethoxysilane or tetraethoxysilane is hydrolyzed and self-assembled to form oligomeric silicon dioxide which is coated on the surface of the perovskite nano particles to form a floating gate layer 120 and a tunneling layer 130;
step S3: spin-coating tetramethoxysilane or tetraethoxysilane on the tunneling layer 130 obtained in the step S2 through a spin coating process, and annealing in a humidity environment, wherein the processing parameters are consistent with those in the step S2; controlling the thickness of the self-assembled tunneling layer 130 by adjusting the number of times of repeating the step S3, wherein the number of times of repeating is in the range of 0-4 times;
step S4: spin-coating an organic polymer semiconductor material on the tunneling layer 130 obtained in step S2 or step S3 by a spin-coating process, and annealing to obtain a semiconductor layer 140;
step S5: and (4) preparing a source electrode and a drain electrode on the semiconductor layer 140 obtained in the step (S4) by a thermal evaporation method to obtain the floating gate type phototransistor memory of the self-assembled tunneling layer 130.
In the present embodiment, the tunneling layer 130 is deposited by a spin coating process in step S3, the rotation speed is 1000-.
Preferably, in the present embodiment, the semiconductor layer 140 is annealed at a temperature of 120-150 ℃ for 10-15 min.
Preferably, in this embodiment, the floating gate type phototransistor memory sequentially includes, from bottom to top, a substrate 100, an insulating layer 110, a floating gate layer 120, a tunneling layer 130, a semiconductor layer 140, and a top source/drain electrode 150. And forming oligomeric silicon dioxide (OS) on the surface of the perovskite nanocrystal by using hydrolysis reaction, and forming an OS composite film wrapped with the perovskite nanocrystal through self-assembly. This thin film is applied to the floating gate layer 120 of a transistor optical memory where the discrete perovskite nanocrystals act as charge trapping centers and the outer-wrapped OS layer acts as a tunneling layer 130 while protecting the perovskite nanocrystals. Based on the optical storage device with the structure, the performance of the storage device is greatly improved while multi-level storage is realized, and the control on the storage performance can be realized by adjusting the thickness of the self-assembly tunneling layer 130 through a simple process flow.
Preferably, in the embodiment, the tunneling layer 130 is made of an oligomeric silicon dioxide, the tunneling layer 130 is deposited by a spin-coating process, the spin-coating speed is 1000-3000rpm, the spin-coating time is 45-60s, the annealing condition is humidity 70-80%, temperature 50-70 ℃, and time 10-30 min. The tunneling layer 130 is tightly wrapped outside the floating gate layer 120 material, and the thickness thereof is 20-200 nm.
Preferably, the method for manufacturing the self-assembled tunneling-layer floating gate phototransistor memory in the embodiment includes the following steps:
a1, blending the perovskite nano-particle solution with TMOS or TEOS to prepare a floating gate layer 120 solution;
a2, after cleaning and plasma processing the substrate 100 with the insulating layer 110, depositing the floating gate layer 120 solution on the substrate 100 by spin coating, and annealing to form the floating gate layer 120 and the tunneling layer 130;
a3, spin-coating TMOS or TEOS on the tunneling layer 130 obtained in the step A2 through a spin coating process, annealing, and adjusting the thickness of the self-assembly tunneling layer 130 by repeating the step;
a4, spin-coating an organic polymer semiconductor material on the tunneling layer 130 obtained in the step A2/A3 through a spin-coating process, and annealing to obtain a semiconductor layer 140;
and A5, preparing a source electrode and a drain electrode on the semiconductor layer 140 obtained in the step A4 by a thermal evaporation method, and obtaining the floating gate type phototransistor memory of the self-assembled tunneling layer 130.
In step A2, the spin-coating speed of the floating gate layer 120 and the tunneling layer 130 of the floating gate phototransistor memory of the self-assembled tunneling layer 130 is 1000-3000rpm, the spin-coating time is 45-60s, the annealing condition is 70-80% humidity, 50-70 ℃ and the time is 10-30 min.
In step A3, the method for adjusting the thickness of the tunneling layer 130 of the floating gate phototransistor memory having the self-assembled tunneling layer 130 is to determine whether to repeat step A3 and adjust the number of times of repeating step A3.
In step A4, the semiconductor layer 140 of the floating gate phototransistor memory of the self-assembled tunneling layer 130 is annealed at 120-150 ℃ for 10-15 min.
In step a5, the thickness of the top source-drain electrode 150 of the floating gate phototransistor memory of the self-assembled tunneling layer 130 is 50-100 nm.
Preferably, the embodiment is specifically exemplified as follows:
example 1
A1, cutting a silicon wafer containing 100nm silicon oxide into a size of 1.5cm multiplied by 1.5cm, carrying out ultrasonic cleaning for 15min by sequentially using acetone, isopropanol and ultrapure water, and drying by using nitrogen after cleaning to obtain a substrate 100 and an insulating layer 110;
a2, mixing Cs2AgBiBr6Blending the perovskite quantum dot solution (15mg/mL) and the TMOS solution (1.5mg/mL) according to the volume ratio of 3:2 to prepare the solution containing Cs2AgBiBr6A floating gate layer 120 solution of perovskite quantum dots;
a3, spin-coating the floating gate layer 120 solution obtained in the step A2 on the silicon wafer cleaned and dried in the step 1 at a spin-coating speed of 3000rpm for 60s after passing through a 0.22-micron filter head, annealing at 60 ℃ for 20min in an environment with 75% humidity, and performing hydrolysis and self-assembly on TMOS to form oligomeric silicon dioxide which wraps the surface of perovskite nano particles so as to form the floating gate layer 120 and the tunneling layer 130;
a4, spin-coating TMOS solution (1.5mg/mL) on the tunneling layer 130 obtained in the step A3 with a spin-coating time of 3000rpm at a spin-coating speed of 60s, and annealing at 60 ℃ for 20min in an environment with 75% humidity; repeating the steps once;
a5, dissolving 5mg of IDTBT in 1ml of chloroform, and heating at 60 ℃ for 2h under the air condition to prepare an organic semiconductor solution;
a6, spin-coating the organic semiconductor solution obtained in the step A5 on the tunneling layer 130 obtained in the step A4 for a spin-coating time of 60s at 1000rpm to prepare a semiconductor layer 140, and annealing at 120 ℃ for 15min under air conditions;
and A7, evaporating and plating a 50nm gold electrode on the semiconductor layer 140 obtained in the step A6 by a special mask in a thermal evaporation mode.
Example 2
A1, cutting a silicon wafer containing 100nm silicon oxide into a size of 1.5cm multiplied by 1.5cm, carrying out ultrasonic cleaning for 15min by sequentially using acetone, isopropanol and ultrapure water, and drying by using nitrogen after cleaning to obtain a substrate 100 and an insulating layer 110;
a2, mixing CsPbBr3Blending the perovskite quantum dot solution (15mg/mL) and the TMOS solution (1.5mg/mL) according to the volume ratio of 3:2 to prepare the CsPbBr-containing solution3A floating gate layer 120 solution of perovskite quantum dots;
a3, spin-coating the floating gate layer 120 solution obtained in the step A2 on the silicon wafer cleaned and dried in the step 1 at a spin-coating speed of 3000rpm for 60s after passing through a 0.22-micron filter head, annealing at 60 ℃ for 20min in an environment with 75% humidity, and performing hydrolysis and self-assembly on TMOS to form oligomeric silicon dioxide which wraps the surface of perovskite nano particles so as to form the floating gate layer 120 and the tunneling layer 130;
a4, spin-coating TMOS solution (1.5mg/ml) on the tunneling layer 130 obtained in the step A3 with a spin-coating time of 3000rpm at a spin-coating speed of 60s, and annealing at 60 ℃ for 20min in an environment with 75% humidity;
a5, dissolving 5mg of IDTBT in 1ml of chloroform, and heating at 60 ℃ for 2h under the air condition to prepare an organic semiconductor solution;
a6, spin-coating the organic semiconductor solution obtained in the step A5 on the tunneling layer 130 obtained in the step A4 for a spin-coating time of 60s at 1000rpm to prepare a semiconductor layer 140, and annealing at 120 ℃ for 15 min;
and A7, evaporating and plating a 50nm gold electrode on the semiconductor layer 140 obtained in the step A6 by a special mask in a thermal evaporation mode.
The transfer characteristic curve and the retention characteristic curve of the self-assembled tunneling layer floating gate phototransistor memory prepared in example 1 are shown in fig. 2 and fig. 3, respectively. As can be seen from fig. 2, the memory window of the floating gate phototransistor memory is as high as 58 volts. As can be seen from fig. 3, the floating gate phototransistor memory has good retention characteristics under different light intensities, and the memory has stable and repeatable operation characteristics.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (10)
1. The utility model provides a floating gate type phototransistor memory of self-assembling tunneling layer which characterized in that: the device comprises a substrate, an insulating layer, a floating gate layer, a tunneling layer, a semiconductor layer and a top source drain electrode; the semiconductor device comprises a substrate, an insulating layer, a floating gate layer, a tunneling layer, a semiconductor layer and a top source drain electrode, wherein the insulating layer grows on the substrate, the floating gate layer grows on the insulating layer, the tunneling layer is tightly wrapped outside the floating gate layer, the semiconductor layer grows on the tunneling layer, and the top source drain electrode grows on the semiconductor layer.
2. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the substrate material can be selected from silicon, polyethylene terephthalate or polydimethylsiloxane.
3. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the insulating layer material can be selected from oxide, gallium nitride, silicon carbide or organic polymers.
4. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the floating gate layer adopts a discrete perovskite nano-particle material and is used as a charge trapping center; the floating gate layer is prepared by deposition through a spin coating process, and the particle size of the floating gate layer is 10-80 nm.
5. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the tunneling layer is made of oligomeric silicon dioxide, is tightly wrapped outside the floating gate layer material and has the thickness of 20-200 nm.
6. The self-assembled tunneling layer floating gate phototransistor memory according to claim 5, wherein: the oligomeric silicon dioxide is formed by performing hydrolysis self-assembly on tetramethoxysilane or tetraethoxysilane after deposition by a spin coating process and performing humidity annealing treatment.
7. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the semiconductor layer is made of organic polymer semiconductor material, and the thickness of the semiconductor layer is 100-500 nm.
8. The self-assembled tunneling layer floating gate phototransistor memory according to claim 1, wherein: the top source drain electrode is made of indium tin oxide, gold, aluminum or silver, and the thickness of the top source drain electrode is 50-100 nm.
9. A method for fabricating a self-assembled tunneling layer floating gate phototransistor memory according to any one of claims 1 to 8, wherein: the method comprises the following steps:
step S1: blending the perovskite nano particle solution with tetramethoxysilane or tetraethoxysilane in a blending volume ratio of 2:1-1:3 to prepare a floating gate layer solution;
step S2: cleaning and plasma processing a substrate with an insulating layer, depositing a floating gate layer solution on the substrate by a spin coating process, and annealing in a humidity environment, wherein the spin coating rotation speed is 1000-3000rpm, the spin coating time is 45-60s, the annealing condition is humidity 70-80%, temperature is 50-70 ℃, and time is 10-30 min; tetramethoxysilane or tetraethoxysilane is hydrolyzed and self-assembled to form oligomeric silicon dioxide which is coated on the surface of the perovskite nano particles to form a floating gate layer and a tunneling layer;
step S3: spinning tetramethoxysilane or tetraethoxysilane on the tunneling layer obtained in the step S2 through a spin coating process, and annealing in a humidity environment, wherein the processing parameters are consistent with those in the step S2; controlling the thickness of the self-assembled tunneling layer by adjusting the number of times of repeating the step S3, wherein the number of times of repeating is 0-4;
step S4: spin-coating an organic polymer semiconductor material on the tunneling layer obtained in the step S2 or the step S3 through a spin-coating process, and annealing to obtain a semiconductor layer;
step S5: and (4) preparing a source electrode and a drain electrode on the semiconductor layer obtained in the step (S4) by a thermal evaporation method to obtain the floating gate type phototransistor memory with the self-assembled tunneling layer.
10. The method of claim 9, wherein the step of forming the self-assembled tunneling layer comprises: the tunneling layer is deposited by a spin coating process in step S3, wherein the rotation speed is 1000-3000rpm, the spin coating time is 45-60S, and the annealing condition is that the humidity is 70-80%, the temperature is 50-70 ℃, and the time is 10-30 min.
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